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HT1609L 2x40 Channel LCD Driver
Features
* * *
Operating voltage: 2.7V~5.2V Bias voltage: static~1/5 bias LCD driving voltage: 3.0V~5.0V
* *
2x40 internal LCD drivers available LCD driver with serial/parallel conversion function
Applications
* *
Electronic dictionaries Portable computers
* *
Remote controllers Calculators
General Description
The HT1609L is an LCD driver LSI with 2x40 output channels using CMOS technology. It is equipped with two sets of 40-bit bidirectional shift registers, 40-bit data latches, 40-bit LCD drivers, and logic control circuits. The HT1609L can convert serial data received from an LCD controller into parallel data and send out LCD driving waveforms to the LCD panel. The HT1609L is designed for general purpose LCD drivers. It can drive both static and dynamic drive LCDs. The LSI can be used as segment driver.
Block Diagram
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Pin Assignment
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Pad Assignment
Chip size: 162 x 102 (mil)2 * The IC substrate should be connected to VDD in the PCB layout artwork.
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Pad Coordinates
Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 X -75.27 -75.27 -75.27 -75.27 -75.27 -75.27 -75.27 -75.27 -75.27 -75.27 -75.27 -75.27 -75.27 -75.27 -75.27 -75.27 -75.27 -75.27 -70.34 -65.49 -60.65 -55.80 -50.96 -46.11 -41.27 -36.42 -31.58 -26.73 -21.89 -17.04 -12.20 -7.35 -2.51 2.34 7.18 12.03 16.87 21.72 26.56 31.41 36.25 41.10 45.94 50.79 55.63 60.48 65.32 70.17 Y 44.20 39.01 33.83 28.65 23.46 18.27 13.09 7.91 2.63 -2.55 -7.61 -12.66 -17.85 -23.12 -28.31 -33.58 -38.76 -43.99 -45.73 -45.73 -45.73 -45.73 -45.73 -45.73 -45.73 -45.73 -45.73 -45.73 -45.73 -45.73 -45.73 -45.73 -45.73 -45.73 -45.73 -45.73 -45.73 -45.73 -45.73 -45.73 -45.73 -45.73 -45.73 -45.73 -45.73 -45.73 -45.73 -45.73 Pad No. 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 X 75.22 75.22 75.22 75.22 75.22 75.22 75.22 75.22 75.22 75.22 75.22 75.22 75.22 75.22 75.22 75.22 75.22 75.22 70.17 65.32 60.48 55.63 50.79 45.94 41.10 36.25 31.41 26.56 21.72 16.87 12.03 7.18 2.34 -2.51 -7.35 -12.20 -17.04 -21.89 -26.73 -31.58 -36.42 -41.27 -46.11 -50.96 -55.80 -60.65 -65.49 -70.34
Unit: mil
Y -43.31 -38.25 -33.19 -28.14 -23.08 -18.02 -12.96 -7.91 -2.85 2.21 7.27 12.32 17.38 22.44 27.50 32.56 37.61 42.67 45.13 45.13 45.13 45.13 45.13 45.13 45.13 45.13 45.13 45.13 45.13 45.13 45.13 45.13 45.13 45.13 45.13 45.13 45.13 45.13 45.13 45.13 45.13 45.13 45.13 45.13 45.13 45.13 45.13 45.13
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Pad Description
Pad No.
1 2 3~6 7 8 9 10 11 12 13 14 15 16 17 18~57 58~96
Pad Name I/O
Y0 VEE V1~V4 VSS CLK1 SHF1 SHF2 VDD CLK2 DL1 DR1 DL2 DR2 ALT Y40~Y79 Y39~Y1 O -- I -- I I I -- I
Description
LCD driver output for channel 1 LCD power supply LCD bias supply voltage for LCD driver Power supply (ground) Clock to latch serial data on the falling edge Shift direction selection of channel 1 shift register Shift direction selection of channel 2 shift register Power supply ( positive ) Clock to shift serial data on the falling edge (Note 1) (Note 1) (Note 2) (Note 2)
I/O Data input/output of channel 1 shift register I/O Data input/output of channel 1 shift register I/O Data input/output of channel 2 shift register I/O Data input/output of channel 2 shift register I O O Alternate signal input for LCD driving waveform LCD driver outputs for channel 2 LCD driver outputs for channel 1
Note 1: Data is processed on the clock falling or rising edge as shown in the following table.
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The output levels of channel 1 and 2 are decided by the combination of ALT and latched data. Refer to the following table:
Latched Data
H (Selected) L (Non-selected)
ALT
H L H L
Channel 1 (Y0~Y39)
V1 V2 V3 V4
Channel 2 (Y40~Y79)
V1 V2 V3 V4
Note 2 : Shift direction of channel 1 and 2
Shift Direction of Channel 1 (Channel 2) SHF1 (SHF2)
H L
Shift Direction
Y39 to Y0 (Y79 to Y40) Y0 to Y39 (Y40 to Y79)
DL1 (DL2)
OUT IN
DR1 (DR2)
IN OUT
Absolute Maximum Ratings*
Supply Voltage .............................. -0.3V to 5.5V Input Voltage..................VSS-0.3V to VDD+0.3V Storage Temperature................. -50C to 125C Operating Temperature............... -20C to 70C
*Note: These are stress ratings only. Stresses exceeding the range specified under "Absolute Maximum Ratings" may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
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D.C. Characteristics
Symbol
VDD IDD ISTB VIL VIH VOL VOH VLCD Ta=25C
Parameter
Operating Voltage Operating Current Standby Current "L" Input Voltage "H" Input Voltage "L" Output Voltage "H" Output Voltage LCD Driving Voltage
Test Conditions VDD
-- 5V 5V 5V 5V 5V 5V --
Min.
2.7 -- -- -- 4 -- 4.6 3
Typ.
-- 100 1 -- -- -- -- --
Max.
5.2 300 5 1 -- 0.4 -- 5.0
Unit
V
A A
Conditions
-- No load -- -- -- IOL=+0.4mA IOH=-0.4mA VDD-VEE
V V V V V Ta=25C
A.C. Characteristics
Symbol
fCLK2 tWCKH tWCKL tSU tDH tDD tSUC1 tSUC2 tR/tF
Parameter
Data Shift Frequency Clock High Level Width Clock Low Level Width Data Setup Time Data Hold Time Data Delay Time Clock Setup Time Clock Setup Time Clock Rise/Fall Time
Test Conditions VDD
5V 5V 5V 5V 5V 5V 5V 5V 5V
Min.
-- 800 800 300 300 -- 500 500 --
Typ.
-- -- -- -- -- -- -- -- --
Max.
400 -- -- -- -- 500 -- -- 200
Unit
kHz ns ns ns ns ns ns ns ns
Conditions
-- -- -- -- -- -- CLK2 CLK1 CLK1 CLK 2 --
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Functional Description
The HT1609L is an LCD driver LSI with 2x40 segment output channel. It operates with a controller, such as HT163A, or another segment driver LSI HT1608, HT1608L and HT1609L.
Clock
Y79 (refer to Note 2).
Data input/output
The CLK1 is the clock to latch data on the falling edge. It latches the data input from the bidirectional shift register at the falling edge of CLK1 and transfers its outputs to the LCD driver circuit. The CLK2 is the clock to shift data on the falling edge. It shifts the serial data at the falling of CLK2 and transfers the output of each bit of the register to the latch circuit (refer to Note 1).
Bidirectional shift register
The DL1, DR1, DL2, DR2 are data input or output option function. When SHF1 (SHF2) is connected to VDD, the 40th bit data of the 1st (2nd) 40-bit shift register outputs from DL1 (DL2) ; when SHF1 (SHF2) is connected to VSS or open , the 1~40 (41~80) bits data from LCD controller enter into the 1st (2nd) 40-bit shift through DL1 (DL2). When SHF1 (SHF2) is connected to VDD, the 1~40 (41~80) bit data from the LCD controller enter into the 1st (2nd)40-bit shift register through DR1 (DR2); when SHF1 (SHF2) is connected to VSS or open , the 40th bit shift register outputs from DR1 (DR2) (refer to Note 2).
LCD driver circuit
The HT1609L supplies two sets of 40-bit shift register, which controls the shift direction by SHF1 & SHF2. The SHF1 controls the 1st 40bit shift register, and SHF2 controls the 2nd 40-bit shift register. When SHF1 is connected to VDD, the 1st shift direction is from Y39 to Y0; when SHF1 is connected to VSS, the shift direction changes from Y0 to Y39. When SHF2 is connected to VDD, the 2nd shift direction is from Y79 to Y40; when SHF2 is connected to VSS, the shift direction changes from Y40 to
Select one of the four levels of voltage V1, V2, V3,and V4 for driving an LCD and transfer it to the output terminals according to the combination of alternate signal (ALT) and the data in the latch circuit (refer to Note 1).
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Static driver
When the HT1609L is used as a static driver, data is transferred on the falling edge of CLK2 and latched on the falling edge of CLK1. The frequency of CLK1 becomes the frame frequency of the LCD driver. The frequency of ALT
has to be twice the frequency of CLK1. ALT has to be synchronized on the falling edge of CLK1. The power supply for the LCD driver is used by shortening V1, V4 or V2, V3. The application circuit connections are shown below:
Timing Diagrams
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Application Circuits
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