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Philips Semiconductors FAST Products
Product specification
9-Bit latched bidirectional Futurebus transceivers (open-collector)
* Multiple GND pins minimize ground bounce * Glitch-free power up/power down
operation
74F8962/8963
FEATURES
* Octal latched transceiver * Drives heavily loaded backplanes with
equivalent load impedances down to 10
power consumption and a series diode on the drivers to reduce capacitive loading. Incident wave switching to 9 is guaranteed. The voltage swing is much less for BTL, so is its receiver threshold region, therefore noise margins are excellent. BTL offers low power consumption, low ground bounce, EMI and crosstalk, low capacitive loading, superior noise margin and low propagation delays. This results in a high bandwidth, reliable backplane. The 74F8962 and 74F8963 A ports have TTL 3-state drivers and TTL receivers with a latch function. The 74F8963 is the non-inverting version of 74F8962.
* High drive (100mA) open collector drivers
on B port
DESCRIPTION
The 74F8962 and 74F8963 are octal bidirectional latched transceivers and are intended to provide the electrical interface to a high performance wired-OR bus. The B port inverting drivers are low-capacitance open collector with controlled ramp and are designed to sink 100mA from 2 volts. The B port inverting receivers have a 150mV threshold region. The B port interfaces to `Backplane Transceiver Logic' (BTL). BTL features a reduced (1V to 2V) voltage swing for lower
* Reduced voltage swing (1 volt) produces
less noise and reduces power consumption
* High speed operation enhances
performance of backplane buses and facilitates incident wave switching
* Compatible with IEEE 896 futurebus
standards
* Built-in precision band-gap reference
provides accurate receiver thresholds and improved noise immunity TYPE 74F8962 74F8963
TYPICAL PROPAGATION DELAY 6.5ns 5.5ns
TYPICAL SUPPLY CURRENT( TOTAL) 90mA 90mA
ORDERING INFORMATION
DESCRIPTION 44-pin Quad Flat Pack1 44-pin Plastic Leaded Chip Carrier Note to ordering information 1. Flatpack package is not available at this time. ORDER CODE COMMERCIAL RANGE VCC = 5V 10%, Tamb = 0C to +70C N74F8962Y, N74F8963Y N74F8962A, N74F8963A
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS AI0 - AI8 B0 - B8 OEAB, OEBA LEAB, LEBA AO0 - AO8 PNP latched inputs Data inputs with threshold circuitry Output enable inputs (active low) Latch enable inputs (active low) 3-state outputs DESCRIPTION 74F (U.L.) HIGH/LOW 1.0/0.167 5.0/0.167 1.0/0.033 1.0/0.033 150/40 OC/166.7 LOAD VALUE HIGH/LOW 20A/100A 100A/100A 20A/20A 20A/20A 3mA/24mA OC/100mA
B0 - B8 Open collector outputs Notes to input and output loading and fan out table 1. One (1.0) FAST unit load is defined as: 20A in the high state and 0.6mA in the low state. 2. OC = Open collector.
March 11, 1993
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853-1425 09230
Philips Semiconductors FAST Products
Product specification
9-Bit latched bidirectional Futurebus transceivers (open-collector)
PIN CONFIGURATION FLATPACK AND PLCC
74F8962
GND 6 AI2 AO2 A13 AO3 AI4 GND AO4 AI5 AO5 AI6 AO6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 AO7 21 22 23 24 25 26 27 GND 28 B7 AO1 5 AI1 AO0 4 3 AI0 2 VCC OEBA LEBA BO 1 44 43 42 GND 41 B1 40 39 38 37 36 35 34 33 32 31 30 29 GND B2 GND B3 GND B4 GND B5 GND B6 GND 24 25 43 44 EN1 EN2 EN3 EN4
74F8962/8963
IEC/IEEE SYMBOL
74F8962
2 3 4 5 7 8 9 10 11 13 14 15 16 17 19 20 21 22
42 1 4 2 3D 40
38
36
34
32
30
28
26
GND AI7
AI8 AO8
VCC LEAB OEAB B8
PIN DESCRIPTION
SYMBOL AI0 - AI8 B0 - B8 OEAB OEBA LEAB LEBA AO0 - AO8 GND VCC PINS 2, 4, 7, 9, 11, 14, 16, 19, 21 42, 40, 38, 36, 34, 32, 30, 28, 26 25 44 24 43 3, 5, 8, 10, 13, 15, 17, 20, 22 6, 12, 18, 27, 29, 31, 33, 35, 37, 39, 41 1, 23 TYPE Input I/O Input Input Input Input Output Ground Power PNP latched inputs. Data input / open collector output, high current drives. Output enable input. Enables the B outputs when low. Output enable input. Enables the A outputs when high. Latch enable input. Enables the AB latches low. Latch enable input. Enables the BA latches low. TTL 3-state outputs. Grounds Positive supply voltages NAME AND FUNCTION
March 11, 1993
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Philips Semiconductors FAST Products
Product specification
9-Bit latched bidirectional Futurebus transceivers (open-collector)
LOGIC SYMBOL FOR 74F8962
74F8962
2 3 4 5 7 8 9 10 11 13 14 15 16 17 19 20 21 22
74F8962/8963
AI0 AO0 AI1 AO1 AI2 AO2 AI3 AO3 AI4 AO4 AI5 AO5 AI6 AO6 AI7 AO7 AI8 AO8 25 24 43 44 OEAB LEAB LEBA OEBA B0 B1 B2 B3 B4 B5 B6 B7 B8
VCC = Pin 1, 23 GND = Pin 6, 12, 18, 27, 29, 31, 33, 35, 37, 39, 41
42 40 38
36
34 32
30 28 26
LOGIC SYMBOL FOR 74F8963
74F8963
2 3 4 5 7 8 9 10 11 13 14 15 16 17 19 20 21 22
AI0 AO0 AI1 AO1 AI2 AO2 AI3 AO3 AI4 AO4 AI5 AO5 AI6 AO6 AI7 AO7 AI8 AO8 25 24 43 44 OEAB LEAB LEBA OEBA B0 B1 B2 B3 B4 B5 B6 B7 B8
VCC = Pin 1, 23 GND = Pin 6, 12, 18, 27, 29, 31, 33, 35, 37, 39, 41
42 40 38
36
34 32
30 28 26
March 11, 1993
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Philips Semiconductors FAST Products
Product specification
9-Bit latched bidirectional Futurebus transceivers (open-collector)
LOGIC DIAGRAM
74F8962
OEAB LEBA LEAB OEBA 25 43 24 44 2 AI0 3 AO0 4 AI1 5 AO1 7 AI2 8 AO2 9 AI3 10 AO3 11 AI4 13 AO4 14 AI5 15 AO5 16 AI6 17 AO6 19 AI7 20 AO7 21 AI8 22 AO8 Q Data E AO8 Data E Q 26 B8 AI8 22 Q Data E Q Data E AO7 21 Data E Q Data E Q 28 B7 AI7 20 Q Data E Data E Q Q Data E 30 B6 AI6 17 AO6 19 Data E Q Data E Q Q Data E 32 B5 AI5 15 AO5 16 Data E Q Q Data E OEAB LEBA LEAB 25 43 24
74F8962/8963
74F8963
OEBA 44 Data E Q Data E Q Data E Q Data E Q Data E Q Q Data E Q Data E Q Data E Q Data E Q Data E 34 B4 36 B3 38 B2 40 B1 2 B0 AI0 3 AO0 4 AI1 5 AO1 7 AI2 8 AO2 9 AI3 10 AO3 11 AI4 13 AO4 14 Data E Q Q Data E 30 B6 32 B5
42
Data E Q Data E Q Data E Q Data E Q Data E Q
Q Data E Q Data E Q Data E Q Data E Q Data E
42
B0
40
B1
38
B2
36
B3
34
B4
28
B7
26
B8
VCC = Pin 1, 23 GND = Pin 6, 12, 18, 27, 29, 31, 33, 37, 39, 41
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Philips Semiconductors FAST Products
Product specification
9-Bit latched bidirectional Futurebus transceivers (open-collector)
FUNCTION TABLE FOR 74F8962
INPUTS AIn H L X H L X X X X X H L Bn* H L X - - H L X X X - - LEAB L L H L L X X H X H L L LEBA L L H X X L L X H H L L OEAB H H H L L H H L H L L L OEBA H H H H H L L H L L L L LATCH STATES AB H L Qn H L Qn Qn Qn Qn Qn H L BA H L Qn Qn Qn H L Qn Qn Qn L H OUTPUTS AOn Z Z Z Z Z L H Z Qn Qn H L Bn X X X L H** X X Qn X Qn L H** B and AO disabled
74F8962/8963
OPERATING MODE
AO 3-state, transparent data from AI to B
B disabled, transparent data from B to AO
AO 3-state, latched data to B B disabled, latched to AO Latched state to AO and B Read back from AI to B to AO (both latches transparent)
Notes to function table for 74F8962 1. H = High voltage level 2. L = Low voltage level 3. X = Don't care 4. - = Input not externally driven 5. Z = High impedance "off' state 6. Qn = High or low voltage level one setup time prior to the low-to-high LEXX transition. 7. H**= Goes to level of pullup voltage. 8. B* = Precaution should be taken to insure B inputs do not float. If they do they are equal to low state.
FUNCTION TABLE FOR 74F8963
INPUTS AIn H L X H L X X X X X H L Bn* H L X - - H L X X X - - LEAB L L H L L X X H X H L L LEBA L L H X X L L X H H L L OEAB H H H L L H H L H L L L OEBA H H H H H L L H L L L L LATCH STATES AB L H Qn L H Qn Qn Qn Qn Qn L H BA L H Qn Qn Qn L H Qn Qn Qn L L OUTPUTS AOn Z Z Z Z Z H L Z Qn Qn H L Bn X X X H L X X Qn X Qn H** L AO 3-state, latched data to B B disabled, latched to AO Latched state to AO and B Read back from AI to B to AO (both latches transparent) B disabled, transparent data from B to AO AO 3-state, transparent data from AI to B B and AO disabled OPERATING MODE
Notes to function table for 74F8963 1. H = High voltage level 2. L = Low voltage level 3. X = Don't care 4. - = Input not externally driven 5. Z = High impedance "off" state 6. Qn = High or low voltage level one setup time prior to the low-to-high LEXX transition. 7. H**= Goes to level of pullup voltage. 8. B* = Precaution should be taken to insure B inputs do not float. If they do they are equal to low state.
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Philips Semiconductors FAST Products
Product specification
9-Bit latched bidirectional Futurebus transceivers (open-collector)
ABSOLUTE MAXIMUM RATINGS
74F8962/8963
(Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free air temperature range.) SYMBOL VCC VIN Supply voltage Input voltage OEBA, OEAB, LEBA, LEAB AI0 - AI8, B0 - B8 IIN VOUT IOUT Input current Voltage applied to output in high output state Current applied to output in low output state AO0 - AO8 B0 - B8 Tamb Tstg Operating free air temperature range Storage temperature range PARAMETER RATING -0.5 to +7.0 -0.5 to +7.0 -0.5 to +5.5 -40 to +5 -0.5 to VCC 48 200 0 to +70 -65 to +150 UNIT V V V mA V mA mA
C C
RECOMMENDED OPERATING CONDITIONS
LIMITS SYMBOL VCC VIH Supply voltage High-level input voltage Except B0 - B8 B0 - B8 VIL Low-level input voltage Except B0 - B8 B0 - B8 IIk IOH IOL Input clamp current High-level output current Low-level output current AO0 - AO8 AO0 - AO8 B0 - B8 Tamb Operating free air temperature range 0 PARAMETER MIN 4.5 2.0 1.62 0.8 1.47 -18 -3 24 100 +70 NOM 5.0 MAX 5.5 UNIT V V V V V mA mA mA mA
C
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Philips Semiconductors FAST Products
Product specification
9-Bit latched bidirectional Futurebus transceivers (open-collector)
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.) SYMBOL IOH IOFF VOH VOL VIK II PARAMETER High-level output current Power-off output current High-level output voltage B0 - B8 B0 - B8 AO0 - AO84 AO0 - Low-level output voltage AO84 TEST CONDITIONS1 VCC = MAX, VIL = MAX, VIH = MIN, VOH = 2.1V VCC = 0.0V, VIL = MAX, VIH = MIN, VOH = 2.1V VCC = MAX, VIL = MAX, VIH = MIN, IOH = -3mA VCC = MIN, VIL = MAX VIH = MIN Input clamp voltage Input current at maximum input voltage OEAB, OEBA, LEAB, LEBA, AI0 - AI8 B0 - B8 OEAB, OEBA, LEAB, LEBA, AI0 - AI8 B0 - B8 OEAB, OEBA, LEAB, LEBA, AI0 - AI8 B0 - B8 IOZH IOZL IOS Off state output current, high-level voltage applied Off state output current, low-level voltage applied Short circuit output current3 AO0 - AO8 VCC = MIN, II = IIK VCC = MAX, VI = 7.0V VCC = MAX, VI = 5.5V VCC = MAX, VI = 2.7V VCC = MAX, VI = 2.1V VCC = MAX, VI = 0.5V VCC = MAX, VI = 0.3V VCC = MAX, VO = 2.7V VCC = MAX, VI = 0.5V V = MAX, Bn = 1.3V, OEBA = 0.8V, AO0 - 74F8962 CC 'F8960 OEAB = 2.7V AO8 only 74F8963 ICCH ICC Supply current (total) ICCL ICCZ VCC = MAX, Bn = 1.8V, OEBA = 0.8V, OEAB = 2.7V VCC = MAX VCC = MAX, VIL = 0.5V IOL = 24mA IOL = 100mA IOL = 4mA
74F8962/8963
LIMITS MIN TYP2 MAX 100 100 2.5 VCC 0.50 0.75 0.40 -1.2 100 1 20 100 -100 -100 50 -50 1.0 1.10
UNIT A A V V V V V A mA A A A A A A
B0 - B8
IIH
High-level input current
IIL
Low-level input current
-60
-150
mA
80 105 80
110 145 110
mA mA mA
NOTES TO DC ELECTRICAL CHARACTERISTICS 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. 2. All typical values are at VCC = 5V, Tamb = 25C. 3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, IOS tests should be performed last. 4. Due to test equipment limitations, actual test conditions are for VIH = 1.8V and VIL = 1.3V.
March 11, 1993
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Philips Semiconductors FAST Products
Product specification
9-Bit latched bidirectional Futurebus transceivers (open-collector)
AC ELECTRICAL CHARACTERISTICS FOR 74F8962
A PORT LIMITS Tamb = +25C SYMBOL PARAMETER TEST CONDITION VCC = +5.0V CL = 50pF, RL = 500 MIN tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tsk(o) Propagation delay Bn to AOn Propagation delay LEBA to AOn Output enable time to high or low, OEBA to AOn Output disable from high or low, OEBA to AOn Skew between receivers in same package Waveform 1, 2 Waveform 1, 2 Waveform 5, 6 Waveform 5, 6 Waveform 4 5.0 3.5 5.5 4.5 7.5 8.5 3.5 4.5 TYP 7.0 5.5 7.0 6.5 9.5 10.5 5.5 6.5 1.5 MAX 10.0 8.5 10.0 9.5 12.5 13.0 8.5 9.5 2.0 Tamb = 0C to +70C VCC = +5.0V 10% CL = 50pF, RL = 500 MIN 4.5 3.5 5.0 4.5 6.5 7.5 2.5 4.0 MAX 11.0 8.5 10.0 9.5 13.5 14.5 10.0 10.0 4.0 B PORT LIMITS Tamb = +25C SYMBOL PARAMETER TEST CONDITION VCC = +5.0V CD = 30pF, RU = 9 MIN tPLH tPHL tPLH tPHL tPLH tPHL tTLH tTHL tsk(o) Propagation delay AIn to Bn Propagation delay LEAB to Bn Output enable/disable time OEBA to Bn Transition time, Bn port 10% to 90%, 90% to 10% Skew between drivers in same package Waveform 1, 2 Waveform 1, 2 Waveform 1 Test circuit and waveforms Waveform 4 3.5 4.0 4.0 5.0 3.5 3.0 1.0 1.0 TYP 5.5 6.0 6.0 7.0 5.0 4.0 1.2 2.0 0.5 MAX 8.5 9.5 8.5 10.5 8.0 8.0 1.6 2.5 2.5 Tamb = 0C to +70C VCC = +5.0V 10% CD = 30pF, RU = 9 MIN 3.0 3.5 3.5 5.0 3.0 2.5 1.0 1.0 MAX 9.0 10.5 9.5 10.5 8.5 8.5 2.5 3.5 3.0
74F8962/8963
Tamb = 0C to +70C VCC = +5.0V 5% CL = 50pF, RL = 500 MIN 4.5 3.5 5.0 4.5 6.5 7.5 2.5 4.0 MAX 10.5 8.5 10.0 9.5 13.0 13.5 9.0 9.5 4.0 ns ns ns ns ns UNIT
Tamb = 0C to +70C VCC = +5.0V 5% CD = 30pF, RU = 9 MIN 3.0 3.5 3.5 5.0 3.0 2.5 1.0 1.0 MAX 9.0 10.0 9.5 10.5 8.0 8.5 2.5 3.5 3.0 ns ns ns ns ns UNIT
AC SETUP REQUIREMENTS FOR 74F8962
LIMITS Tamb = +25C SYMBOL PARAMETER TEST CONDITION VCC = +5.0V CL = 50pF, RL = 500 MIN tsu(H) tsu(L) th(H) th(L) tsu(H) tsu(L) th(H) th(L) tw(L) Setup time, high or low AIn to LEAB Hold time, high or low AIn to LEAB Setup time, high or low Bn to LEBA Hold time, high or low Bn to LEBA LEAB or LEBA pulse width, low Waveform 3 Waveform 3 Waveform 3 Waveform 3 Waveform 3 3.0 1.0 3.0 0.0 2.0 1.0 3.0 1.5 4.5 TYP MAX Tamb = 0C to +70C VCC = +5.0V 10% CL = 50pF, RL = 500 MIN 3.5 2.0 3.5 0.0 2.5 1.0 3.5 2.0 4.5 MAX Tamb = 0C to +70C VCC = +5.0V 5% CL = 50pF, RL = 500 MIN 3.0 1.5 3.0 0.0 2.0 1.0 3.0 2.0 4.5 MAX ns ns ns ns ns UNIT
March 11, 1993
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Philips Semiconductors FAST Products
Product specification
9-Bit latched bidirectional Futurebus transceivers (open-collector)
AC ELECTRICAL CHARACTERISTICS FOR 74F8963
A PORT LIMITS Tamb = +25C SYMBOL PARAMETER TEST CONDITION VCC = +5.0V CL = 50pF, RL = 500 MIN tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tsk(o) Propagation delay Bn to AOn Propagation delay LEBA to AOn Output enable time to high or low, OEBA to AOn Output disable time from high or low, OEBA to AOn Skew between receivers in same package Waveform 1, 2 Waveform 1, 2 Waveform 5, 6 Waveform 5, 6 Waveform 4 3.5 2.5 6.0 4.0 9.0 10.0 4.0 5.5 TYP 5.5 4.0 7.5 5.5 11.0 12.0 6.0 7.0 1.5 MAX 8.0 7.0 10.0 8.5 15.0 16.0 9.0 11.0 2.0 Tamb = 0C to +70C VCC = +5.0V 10% CL = 50pF, RL = 500 MIN 3.0 2.0 5.0 3.5 8.5 9.0 3.0 5.0 MAX 9.0 7.5 11.5 9.0 16.5 18.0 10.5 12.0 4.0 B PORT LIMITS Tamb = +25C SYMBOL PARAMETER TEST CONDITION VCC = +5.0V CD = 30pF, RU = 9 MIN tPLH tPHL tPLH tPHL tPLH tPHL tTLH tTHL tsk(o) Propagation delay AIn to Bn Propagation delay LEAB to Bn Output enable/disable time OEBA to Bn Transition time, Bn port 10% to 90%, 90% to 10% Skew between drivers in same package Waveform 1, 2 Waveform 1, 2 Waveform 1 Test circuit and waveforms Waveform 4 2.0 2.0 3.5 2.5 3.5 3.0 1.0 1.0 TYP 4.0 3.5 5.0 4.0 5.5 5.0 1.2 2.0 0.5 MAX 6.5 6.5 8.0 7.0 9.0 7.5 1.6 2.5 2.0 Tamb = 0C to +70C VCC = +5.0V 10% CD = 30pF, RU = 9 MIN 1.5 1.5 3.0 2.0 2.5 2.5 1.0 1.0 MAX 7.0 6.5 8.5 8.0 9.5 8.5 2.5 3.5 3.0
74F8962/8963
Tamb = 0C to +70C VCC = +5.0V 5% CL = 50pF, RL = 500 MIN 3.0 2.0 5.0 3.5 8.5 9.0 3.0 5.0 MAX 8.0 7.5 10.0 8.5 15.5 16.5 9.5 11.0 4.0 ns ns ns ns ns UNIT
Tamb = 0C to +70C VCC = +5.0V 5% CD = 30pF, RU = 9 MIN 2.0 2.0 3.5 2.5 2.5 2.5 1.0 1.0 MAX 7.0 6.5 8.5 8.0 9.0 8.0 2.5 3.5 3.0 ns ns ns ns ns UNIT
AC SETUP REQUIREMENTS FOR 74F8963
LIMITS Tamb = +25C SYMBOL PARAMETER TEST CONDITION VCC = +5.0V CL = 50pF, RL = 500 MIN tsu(H) tsu(L) th(H) th(L) tsu(H) tsu(L) th(H) th(L) tw(L) Setup time, high or low AIn to LEAB Hold time, high or low AIn to LEAB Setup time, high or low Bn to LEBA Hold time, high or low Bn to LEBA LEAB or LEBA pulse width, low Waveform 3 Waveform 3 Waveform 3 Waveform 3 Waveform 3 4.0 1.0 2.5 0.0 2.0 1.0 2.5 1.0 4.5 TYP MAX Tamb = 0C to +70C VCC = +5.0V 10% CL = 50pF, RL = 500 MIN 4.5 1.5 3.0 0.0 2.5 1.0 3.0 1.5 5.5 MAX Tamb = 0C to +70C VCC = +5.0V 5% CL = 50pF, RL = 500 MIN 4.0 1.0 2.5 0.0 2.0 1.0 3.0 1.0 5.5 MAX ns ns ns ns ns UNIT
March 11, 1993
9
Philips Semiconductors FAST Products
Product specification
9-Bit latched bidirectional Futurebus transceivers (open-collector)
AC WAVEFORMS
AIn, Bn, LEAB, LEBA OEAB VM tPLH AOn, Bn VM VM tPHL VM AIn, Bn, LEAB, LEBA VM tPHL VM VM
74F8962/8963
tPLH VM
An, Bn
Waveform 1. Propagation delay for data or output enable or latch enable to output
AIn, Bn VM VM th(L) tsu(L) LEAB, LEBA VM VM VM tsu(H) tw(L) VM VM
Waveform 2. Propagation delay for data or latch enable to output
AOn, Bn VM tsk(o)
th(H)
AOn, Bn
VM
Waveform 3. Data setup and hold times and LEAB/LEBA pulse widths
Waveform 4. Output skew
OEAB
VM tPZH
VM tPHZ VM 0V VOH -0.3V
OEAB
VM tPZL
VM tPLZ VM VOL +0.3V
An
An
Waveform 5. 3-state output enable time to high level and output disable time from high level
Waveform 6. 3-state output enable time to low level and output disable time from low level
NOTES TO AC WAVEFORMS 1. For all waveforms, VM = 1.5V. 2. The shaded areas indicate when the input is permitted to change for predictable output performance.
TEST CIRCUITS AND WAVEFORMS
SWITCH POSITION TEST SWITCH tPLZ, tPZL closed All other open
VIN PULSE GENERATOR RT D.U.T. tTLH (tr ) CL RL POSITIVE PULSE 90% VM 10% tw tTHL (tf ) AMP (V) 90% VM 10% Low V 90% VCC 7.0V VOUT RL NEGATIVE PULSE VM 10% tTHL (tf ) tw VM 10% tTLH (tr ) Low V 90% AMP (V)
Test circuit for 3-state outputs on A port
VCC 7.0V
Input pulse definition
VIN PULSE GENERATOR RT D.U.T. VOUT RU
INPUT PULSE REQUIREMENTS family tTLH tw 74F amplitude Low V VM rep. rate A port B port 3.0V 3.0V 0.0V 1.0V 1.5V 1.5V 1MHz 1MHz 500ns 500ns 2.5ns 4.0ns
tTHL 2.5ns 4.0ns
CD
Test circuit for outputs on B port DEFINITIONS: RL = Load resistor; see AC electrical characteristics for value. CL = Load capacitance includes jig and probe capacitance; see AC electrical characteristics for value. RU = Pull up resistor; see AC electrical characteristics for value. CD = Load capacitance includes jig and probe capacitance; see AC electrical characteristics for value. RT = Termination resistance should be equal to ZOUT of pulse generators.
March 11, 1993
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