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IDT54/74FCT273T/AT/CT FAST CMOS OCTAL D FLIP-FLOP WITH MASTER RESET
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
FAST CMOS OCTAL D FLIP-FLOP WITH MASTER RESET
FEATURES:
* * * *
IDT54/74FCT273T/AT/CT
DESCRIPTION:
* * * * *
Std., A, and C grades Low input and output leakage 1A (max.) CMOS power levels True TTL input and output compatibility: - VOH = 3.3V (typ.) - VOL = 0.3V (typ.) High Drive outputs (-15mA IOH, 48mA IOL) Meets or exceeds JEDEC standard 18 specifications Military product compliant to MIL-STD-883, Class B and DESC listed (dual marked) Power off disable outputs permit "live insertion" Available in the following packages: - Industrial: SOIC, SSOP, QSOP - Military: CERDIP, LCC
The FCT273T is an octal D flip-flop built using an advanced dual metal CMOS technology. The FCT273T has eight edge-triggered D-type flipflops with individual D inputs and O outputs. The common buffered Clock (CP) and Master Reset (MR) inputs load and reset (clear) all flip-flops simultaneously. The register is fully edge-triggered. The state of each D input, one setup time before the low-to-high clock transition, is transferred to the corresponding flip-flop's O output. All outputs will be forced low independently of Clock or Data inputs by a low voltage level on the MR input. The device is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage elements.
FUNCTIONAL BLOCK DIAGRAM
D0 CP
D1
D2
D3
D4
D5
D6
D7
D CP RD MR
Q
D CP RD
Q
D CP RD
Q
D CP RD
Q
D CP RD
Q
D CP RD
Q
D CP RD
Q
D CP RD
Q
O0
O1
O2
O3
O4
O5
O6
O7
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
1
JUNE 2002
DSC-2568/2
(c) 2002 Integrated Device Technology, Inc.
IDT54/74FCT273T/AT/CT FAST CMOS OCTAL D FLIP-FLOP WITH MASTER RESET
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
PIN CONFIGURATION
O0
MR O0 D0 D1 O1 O2 D2 D3 O3 GND
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
VCC O7 D7 D6 O6 O5 D5 D4 O4 CP
D0
3
2 1
20
19 18 17 16 15 14
D1 O1 O2 D2 D3
O7
INDEX
MR
VCC
4 5 6 7 8 9 10
D7 D6 O6 O5 D5
11
12
13
GND
CP
O3
CERDIP/ SOIC/ SSOP/ QSOP TOP VIEW
LCC TOP VIEW
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Description Max -0.5 to +7 -0.5 to VCC+0.5 -65 to +150 -60 to +120 Unit V V C mA VTERM(2) Terminal Voltage with Respect to GND VTERM(3) Terminal Voltage with Respect to GND TSTG IOUT Storage Temperature DC Output Current
PIN DESCRIPTION
Pin Names Dx MR CP Ox Data Inputs Master Reset (Active LOW) Clock Pulse Input (Active Rising Edge) Data Outputs Description
NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. No terminal voltage may exceed Vcc by +0.5V unless otherwise noted. 2. Inputs and Vcc terminals only. 3. Output and I/O terminals only.
FUNCTION TABLE(1)
Operating Mode Reset (Clear) Load "1" Load "0" MR L L H Inputs CP X Dx X h l Outputs Ox L H L
CAPACITANCE (TA = +25C, F = 1.0MHz)
Symbol CIN COUT Parameter(1) Input Capacitance Output Capacitance Conditions VIN = 0V VOUT = 0V Typ. 6 8 Max. 10 12 Unit pF pF
NOTE: 1. This parameter is measured at characterization but not tested.
NOTE: 1. H = HIGH voltage level steady state h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition L = LOW voltage level steady state I = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition X = Don't Care = LOW-to-HIGH Clock Transition
2
O4
D4
IDT54/74FCT273T/AT/CT FAST CMOS OCTAL D FLIP-FLOP WITH MASTER RESET
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Industrial: TA = -40C to +85C, VCC = 5.0V 5%; Military: TA = -55C to +125C, VCC = 5.0V 10%
Symbol VIH VIL IIH IIL II VIK IOS VOH Parameter Input HIGH Level Input LOW Level Input HIGH Current(4) Input LOW Current(4) Input HIGH Current(4) Clamp Diode Voltage Short Circuit Current Output HIGH Voltage Test Conditions(1) Guaranteed Logic HIGH Level Guaranteed Logic LOW Level VCC = Max. VCC = Max. VCC = Max., VI = VCC (Max.) VCC = Min., IIN = -18mA VCC = Max., VO = VCC = Min VIN = VIH or VIL GND(3) IOH = -6mA MIL IOH = -8mA IND IOH = -12mA MIL IOH = -15mA IND IOL = 32mA MIL IOL = 48mA IND -- VCC = Max. VIN = GND or VCC VI = 2.7V VI = 0.5V Min. 2 -- -- -- -- -- -60 2.4 2 -- -- -- Typ.(2) -- -- -- -- -- -0.7 -120 3.3 3 0.3 200 0.01 Max. -- 0.8 1 1 1 -1.2 -225 -- -- 0.5 -- 1 V mV mA A V mA V Unit V V A
VOL VH ICC
Output LOW Voltage Input Hysteresis Quiescent Power Supply Current
VCC = Min VIN = VIH or VIL
NOTES: 1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, +25C ambient. 3. Not more than one output should be tested at one time. Duration of the test should not exceed one second. 4. The test limit for this parameter is 5A at TA = -55C.
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IDT54/74FCT273T/AT/CT FAST CMOS OCTAL D FLIP-FLOP WITH MASTER RESET
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
Symbol ICC ICCD Parameter Quiescent Power Supply Current TTL Inputs HIGH Dynamic Power Supply Current(4) VCC = Max. VIN = 3.4V(3) VCC = Max. Outputs Open MR = VCC One Input Toggling 50% Duty Cycle VCC = Max. Outputs Open fCP = 10MHz 50% Duty Cycle MR = VCC One Bit Toggling fi = 5MHz 50% Duty Cycle VCC = Max. Outputs Open fCP = 10MHz 50% Duty Cycle MR = VCC Eight Bits Toggling fi = 2.5MHz 50% Duty Cycle VIN = VCC VIN = GND Test Conditions(1) Min. -- -- Typ.(2) 0.5 0.15 Max. 2 0.25 Unit mA mA/ MHz
IC
Total Power Supply Current(6)
VIN = VCC VIN = GND VIN = 3.4V VIN = GND VIN = VCC VIN = GND VIN = 3.4V VIN = GND
--
1.5
3.5
mA
--
2
5.5
--
3.8
7.3(5)
--
6
16.3(5)
NOTES: 1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, +25C ambient. 3. Per TTL driven input; (VIN = 3.4V). All other inputs at VCC or GND. 4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. 5. Values for these conditions are examples of ICC formula. These limits are guaranteed but not tested. 6. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ICC DHNT + ICCD (fCP/2+ fiNi) ICC = Quiescent Current ICC = Power Supply Current for a TTL High Input (VIN = 3.4V) DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current caused by an Input Transition Pair (HLH or LHL) fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices) fi = Output Frequency Ni = Number of Outputs at fi All currents are in milliamps and all frequencies are in megahertz.
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IDT54/74FCT273T/AT/CT FAST CMOS OCTAL D FLIP-FLOP WITH MASTER RESET
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE - INDUSTRIAL
Symbol tPLH tPHL tPLH tPHL tSU tH tW tW tREM Parameter Propagation Delay CP to Ox Propagation Delay MR to Ox Set-up Time HIGH or LOW Dx to CP Hold Time HIGH or LOW Dx to CP CP Pulse Width HIGH or LOW MR Pulse Width LOW Recovery Time MR to CP Condition(1) CL = 50pF RL = 500 74FCT273AT Min.(2) Max. 2 7.2 2 2 1.5 6 6 2 7.2 -- -- -- -- -- 74FCT273CT Min.(2) Max. 2 5.8 2 2 1.5 6 6 2 6.1 -- -- -- -- -- Unit ns ns ns ns ns ns ns
SWITCHING CHARACTERISTICS OVER OPERATING RANGE - MILITARY
Symbol tPLH tPHL tPLH tPHL tSU tH tW tW tREM Parameter Propagation Delay CP to Ox Propagation Delay MR to Ox Set-up Time HIGH or LOW Dx to CP Hold Time HIGH or LOW Dx to CP CP Pulse Width HIGH or LOW MR Pulse Width LOW Recovery Time MR to CP Condition(1) CL = 50pF RL = 500 54FCT273T Min.(2) Max. 2 15 2 3.5 2 7 7 5 15 -- -- -- -- -- 54FCT273AT Min.(2) Max. 2 8.3 2 2 1.5 6 6 2.5 8.3 -- -- -- -- -- 54FCT273CT Min.(2) Max. 2 6.5 2 2 1.5 6 6 2.5 6.8 -- -- -- -- -- Unit ns ns ns ns ns ns ns
NOTES: 1. See test circuit and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays.
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IDT54/74FCT273T/AT/CT FAST CMOS OCTAL D FLIP-FLOP WITH MASTER RESET
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
TEST CIRCUITS AND WAVEFORMS
V CC 500 VIN Pulse Generator RT D.U.T . VOUT 7.0V
SWITCH POSITION
Test Open Drain Disable Low Enable Low All Other Tests Switch Closed Open
50pF CL
500
DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
Octal link
Test Circuits for All Outputs
DATA INPUT TIMING INPUT ASYNCHRONOUS CONTROL PRESET CLEAR ETC. SYNCHRONOUS CONTROL PRESET CLEAR CLOCK ENABLE ETC.
tSU
tH
tREM
3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V
Octal link
LOW-HIGH-LOW PULSE tW HIGH-LOW-HIGH PULSE
Octal link
1.5V
1.5V
tSU
tH
Pulse Width
Set-Up, Hold, and Release Times
ENABLE SAME PHASE INPUT TRANSITION tPLH OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION tPHL tPHL 3V 1.5V 0V VOH 1.5V VOL 3V 1.5V 0V
Octal link
DISABLE 3V 1.5V
CONTROL INPUT tPZL OUTPUT NORMALLY LOW OUTPUT NORMALLY HIGH SWITCH CLOSED tPZH SWITCH OPEN 3.5V 1.5V tPHZ 0.3V 1.5V 0V tPLZ
0V 3.5V 0.3V VOL VOH 0V
Octal link
Propagation Delay
Enable and Disable Times
NOTES: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. 2. Pulse Generator for All Pulses: Rate 1.0MHz; tF 2.5ns; tR 2.5ns.
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IDT54/74FCT273T/AT/CT FAST CMOS OCTAL D FLIP-FLOP WITH MASTER RESET
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
ORDERING INFORMATION
XXXX IDT XX FCT Temp. Range Device Type XX Package X Process Blank B Industrial MIL-STD-883, Class B Industrial Options Small Outline IC Shink Small Outline Package Quarter-size Small Outline Package Military Options CERDIP Leadless Chip Carrier
SO PY Q
D L
273T 273AT 273CT
Octal D Flip-Flop with Master Reset
54 74
- 55C to +125C - 40C to +85C
CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054
for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com
for Tech Support: logichelp@idt.com (408) 654-6459
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