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2 Megabit Flash + 1 Megabit SRAM ComboMemory
SST31LH021
Advance Information
FEATURES: * Organized as 256K x 8 flash + 128K x 8 SRAM * Single 3.0-3.6V Read and Write Operations * Concurrent Operation - Read from or write to SRAM while erase/ program Flash * Superior Reliability - Endurance: 100,000 Cycles (typical) - Greater than 100 years Data Retention * Low Power Consumption: - Active Current: 10 mA (typical) for Flash or SRAM Read - Standby Current: 10 A (typical) * Sector Erase Capability - Uniform 4 KByte sectors * Fast Read Access Times: - Flash: 70 ns - SRAM: 25 ns PRODUCT DESCRIPTION The SST31LH021 is a 256K x 8 CMOS flash memory bank combined with a 128K x 8 CMOS SRAM memory bank manufactured with SST's proprietary, high performance SuperFlash technology. The SST31LH021 device writes (SRAM or programs or erases flash) with a 3.0-3.6V power supply. The monolithic SST31LH021 device conforms to JEDEC standard pinouts and Software Data Protect (SDP) commands for x8 EEPROMs in TSOP packages. Featuring high performance byte program, the flash memory bank provides a maximum byte program time of 20 sec. The entire flash memory bank can be erased and programmed byte-by-byte in typically 4 seconds, when using interface features such as Toggle Bit or Data# Polling to indicate the completion of Program operation. To protect against inadvertent flash write, the SST31LH021 device has on-chip hardware and software data protection schemes. Designed, manufactured, and tested for a wide spectrum of applications, the SST31LH021 device is offered with a guaranteed endurance of 10,000 cycles. Data retention is rated at greater than 100 years. The SST31LH021 operates as two independent memory banks with respective bank enable signals. The SRAM and Flash memory banks are superimposed in the same memory address space. Both memory banks share common address lines, data lines, WE# and OE#. The memory bank selection is done by memory bank enable signals. The SRAM bank enable signal, BES# selects
(c) 1999 Silicon Storage Technology, Inc. 353-06 5/99
* Latched Address and Data for Flash * Flash Fast Sector Erase and Byte Program: - Sector Erase Time: 18 ms typical - Bank Erase Time: 70 ms typical - Byte Program Time: 14 s typical - Bank Rewrite Time: 4 seconds typical * Flash Automatic Erase and Program Timing - Internal VPP Generation * Flash End of Write Detection - Toggle Bit - Data# Polling * CMOS I/O Compatibility * JEDEC Standard Command Set * Packages Available - 32-Pin TSOP (8mm x 14mm) - 40-Pin TSOP (10mm x 14mm)
1 2 3 4 5 6 7
the SRAM bank and the flash memory bank enable signal, BEF# selects the flash memory bank. The WE# signal has to be used with Software Data Protection (SDP) command sequence when controlling the Erase and Program operations in the flash memory bank. The SDP command sequence protects the data stored in the flash memory bank from accidental alteration. The SST31LH021 provides the added functionality of being able to simultaneously read from or write to the SRAM bank while erasing or programming in the flash memory bank. The SRAM memory bank can be read or written while the flash memory bank performs Sector Erase, Bank Erase, or Byte Program concurrently. All flash memory Erase and Program operations will automatically latch the input address and data signals and complete the operation in background without further input stimulus requirement. Once the internally controlled erase or program cycle in the flash bank has commenced, the SRAM bank can be accessed for read or write. The SST31LH021 device is suited for applications that use both nonvolatile flash memory and volatile SRAM memory to store code or data. For all system applications, the SST31LH021 device significantly improves performance and reliability, while lowering power consumption, when compared with multiple chip solutions. The SST31LH021 inherently uses less energy during erase and program than alternative flash technologies. The total energy consumed is a function of the applied voltage, current, and time of application. Since for any
8 9 10 11 12 13 14 15 16
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. ComboMemory is a trademark of 1 Silicon Storage Technology, Inc. These specifications are subject to change without notice.
2 Megabit Flash + 1 Megabit SRAM ComboMemory SST31LH021
Advance Information given voltage range, the SuperFlash technology uses less current to program and has a shorter erase time, the total energy consumed during any Erase or Program operation is less than alternative flash technologies. The monolithic ComboMemory eliminates redundant functions when using two separate memories of similar architecture; therefore, reducing the total power consumption. The SuperFlash technology provides fixed Erase and Program times, independent of the number of Erase/ Program cycles that have occurred. Therefore the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Program times increase with accumulated Erase/Program cycles. The SST31LH021 device also improves flexibility by using a single package and a common set of signals to perform functions previously requiring two separate devices. To meet high density, surface mount requirements, the SST31LH021 device is offered in 32-pin and 40-pin TSOP packages. See Figure 1 for the pinouts. Device Operation The ComboMemory uses BES# and BEF# to control operation of either the SRAM or the flash memory bank. Bus contention is eliminated as the monolithic device will not recognize both bank enables as being simultaneously active. If both bank enables are asserted (i.e., BEF# and BES# are both low), the BEF# will dominate while the BES# is ignored and the appropriate operation will be executed in the flash memory bank. SST does not recommend that both bank enables be simultaneously asserted. All other address, data, and control lines are shared; which minimizes power consumption and area. The device goes into standby when both bank enables are raised to VIHC. SRAM Operation With BES# low and BEF# high, the SST31LH021 operates as a 128K x8 CMOS SRAM, with fully static operation requiring no external clocks or timing strobes. The SRAM is mapped into the first 128 KByte address space of the device. Read and Write cycle times are equal. SRAM Read The SRAM Read operation of the SST31LH021 is controlled by OE# and BES#, both have to be low with WE# high, for the system to obtain data from the outputs. BES# is used for SRAM bank selection. When BES# and BEF# are high, both memory banks are deselected. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when OE# is high. Refer to the Read cycle timing diagram, Figure 2, for further details. SRAM Write The SRAM Write operation of the SST31LH021 is controlled by WE# and BES#, both have to be low for the system to write to the SRAM. BES# is used for SRAM bank selection. During the Byte Write operation, the addresses and data are referenced to the rising edge of either BES# or WE#, whichever occurs first. The write time is measured from the last falling edge to the first rising edge of BES# and WE#. Refer to the Write cycle timing diagram, Figure 3, for further details. Flash Operation With BEF# active, the SST31LH021 operates as a 256K x 8 flash memory. The flash memory bank is read using the common address lines, data lines, WE# and OE#. Erase and Program operations are initiated with the JEDEC standard SDP command sequences. Address and data are latched during the SDP commands and internally timed Erase and Program operations. Flash Read The Read operation of the SST31LH021 device is controlled by BEF# and OE#, both have to be low, with WE# high, for the system to obtain data from the outputs. BEF# is used for flash memory bank selection. When BEF# and BES# are high, both banks are deselected and only standby power is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when OE# is high. Refer to the Read cycle timing diagram (Figure 4) for further details. Flash Erase/Program Operation SDP commands are used to initiate the flash memory bank Program and Erase operations of the SST31LH021. SDP commands are loaded to the flash memory bank using standard microprocessor write sequences. A command is loaded by asserting WE# low while keeping BEF# low and OE# high. The address is latched on the falling edge of WE# or BEF#, whichever occurs last. The data is latched on the rising edge of WE# or BEF#, whichever occurs first.
(c) 1999 Silicon Storage Technology, Inc.
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Advance Information Flash Byte Program Operation The flash memory bank of the SST31LH021 device is programmed on a byte-by-byte basis. The Program operation consists of three steps. The first step is the three-byte-load sequence for Software Data Protection. The second step is to load byte address and byte data. During the Byte Program operation, the addresses are latched on the falling edge of either BEF# or WE#, whichever occurs last. The data is latched on the rising edge of either BEF# or WE#, whichever occurs first. The third step is the internal Program operation which is initiated after the rising edge of the fourth WE# or BEF#, whichever occurs first. The Program operation, once initiated, will be completed, within 20 s. See Figures 5 and 6 for WE# and BEF# controlled Program operation timing diagrams and Figure 15 for flowcharts. During the Program operation, the only valid Flash Read operations are Data# Polling and Toggle Bit. During the internal Program operation, the host is free to perform additional tasks. Any SDP commands loaded during the internal Program operation will be ignored. Flash Sector Erase Operation The Sector Erase operation allows the system to erase the flash memory bank on a sector by sector basis. The sector architecture is based on uniform sector size of 4 KBytes. The Sector Erase operation is initiated by executing a six-byte-command load sequence for software data protection with sector erase command (30H) and sector address (SA) in the last bus cycle. The address lines A12-A17 will be used to determine the sector address. The sector address is latched on the falling edge of the sixth WE# pulse, while the command (30H) is latched on the rising edge of the sixth WE# pulse. The internal Erase operation begins after the sixth WE# pulse. The end of Erase can be determined using either Data# Polling or Toggle Bit methods. See Figure 9 for timing waveforms. Any SDP commands loaded during the Sector Erase operation will be ignored. Flash Bank Erase Operation The SST31LH021 flash memory bank provides a Bank Erase operation, which allows the user to erase the entire flash memory bank array to the "1's" state. This is useful when the entire bank must be quickly erased. The Bank Erase operation is initiated by executing a six-byte software data protection command sequence with Bank Erase command (10H) with address 5555H in the last byte sequence. The internal Erase operation begins with the rising edge of the sixth WE# or BEF# pulse, whichever occurs first. During the internal Erase operation, the only valid Flash Read operations are Toggle Bit and Data# Polling. See Table 4 for the command sequence,
(c) 1999 Silicon Storage Technology, Inc.
Figure 10 for timing diagram, and Figure 18 for the flowchart. Any SDP commands loaded during the Bank Erase operation will be ignored. Flash Write Operation Status Detection The SST31LH021 flash memory bank provides two software means to detect the completion of a flash memory bank Write (Program or Erase) cycle, in order to optimize the system Write cycle time. The software detection includes two status bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The end of write detection mode is enabled after the rising edge of WE#, which initiates the internal Program or Erase operation. The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a Data# Polling or Toggle Bit read may be simultaneous with the completion of the Write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either DQ7 or DQ6. In order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. If both reads are valid, then the device has completed the Write cycle, otherwise the rejection is valid. Flash Data# Polling (DQ7) When the SST31LH021 flash memory bank is in the internal Program operation, any attempt to read DQ7 will produce the complement of the true data. Once the Program operation is completed, DQ7 will produce true data. The flash memory bank is then ready for the next operation. During internal Erase operation, any attempt to read DQ7 will produce a `0'. Once the internal Erase operation is completed, DQ7 will produce a `1'. The Data# Polling is valid after the rising edge of the fourth WE# (or BEF#) pulse for Program operation. For Sector or Bank Erase, the Data# Polling is valid after the rising edge of the sixth WE# (or BEF#) pulse. See Figure 7 for Data# Polling timing diagram and Figure 16 for a flowchart. Flash Toggle Bit (DQ6) During the internal Program or Erase operation, any consecutive attempts to read DQ6 will produce alternating 0's and 1's, i.e., toggling between 0 and 1. When the internal Program or Erase operation is completed, the toggling will stop. The flash memory bank is then ready for the next operation. The Toggle Bit is valid after the rising edge of the fourth WE# (or BE#) pulse for Program operation. For Sector or Bank Erase, the Toggle Bit is valid after the rising edge of the sixth WE# (or BEF#) pulse. See Figure 8 for Toggle Bit timing diagram and Figure 16 for a flowchart.
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2 Megabit Flash + 1 Megabit SRAM ComboMemory SST31LH021
Advance Information Flash Memory Data Protection The SST31LH021 flash memory bank provides both hardware and software features to protect nonvolatile data from inadvertent writes. Flash Hardware Data Protection Noise/Glitch Protection: A WE# or BEF# pulse of less than 5 ns will not initiate a write cycle. VDD Power Up/Down Detection: The Write operation is inhibited when VDD is less than 1.5V. Write Inhibit Mode: Forcing OE# low, BEF# high, or WE# high will inhibit the Flash Write operation. This prevents inadvertent writes during power-up or power-down. Flash Software Data Protection (SDP) The SST31LH021 provides the JEDEC approved software data protection scheme for all flash memory bank data alteration operations, i.e., Program and Erase. Any Program operation requires the inclusion of a series of three-byte sequence. The three byte-load sequence is used to initiate the Program operation, providing optimal protection from inadvertent Write operations, e.g., during the system power-up or power-down. Any Erase operation requires the inclusion of six-byte load sequence. The SST31LH021 device is shipped with the software data protection permanently enabled. See Table 4 for the specific software command codes. During SDP command sequence, invalid SDP commands will abort the device to the read mode, within TRC. Concurrent Read and Write Operations The SST31LH021 provides the unique benefit of being able to read from or write to SRAM, while simultaneously erasing or programming the Flash. The device will ignore all SDP commands when an Erase or Program operation is in progress. This allows data alteration code to be executed from SRAM, while altering the data in Flash. The following table lists all valid states. CONCURRENT READ/WRITE STATE TABLE Flash Program/Erase Program/Erase SRAM Read Write Product Identification The product identification mode identifies the device as the SST31LH021 and manufacturer as SST. This mode may be accessed by hardware or software operations. The hardware device ID read operation is typically used by a programmer to identify the correct algorithm for the SST31LH021 flash memory bank. Users may wish to use the software product identification operation to identify the part (i.e., using the device code) when using multiple manufacturers in the same socket. For details, see Table 3 for hardware operation or Table 4 for software operation, Figure 11 for the software ID entry and read timing diagram and Figure 17 for the ID entry command sequence flowchart. TABLE 1: PRODUCT IDENTIFICATION TABLE Address Manufacturer's Code Device Code 0000H 0001H Data BF H 18 H
353 PGM T1.0
Product Identification Mode Exit/Reset In order to return to the standard read mode, the Software Product Identification mode must be exited. Exiting is accomplished by issuing the Exit ID command sequence, which returns the device to the Read operation. Please note that the software-reset command is ignored during an internal Program or Erase operation. See Table 4 for software command codes, Figure 12 for timing waveform and Figure 17 for a flowchart. Design Considerations SST recommends a high frequency 0.1 F ceramic capacitor to be placed as close as possible between VDD and VSS, e.g., less than 1 cm away from the VDD pin of the device. Additionally, a low frequency 4.7 F electrolytic capacitor from VDD to VSS should be placed within 5 cm of the VDD pin.
Note that Product Identification commands use SDP; therefore, these commands will also be ignored while an Erase or Program operation is in progress.
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Advance Information FUNCTIONAL BLOCK DIAGRAM OF SST31LH021
1,048,576 bit SRAM Cell Array
Address Buffers
1 2
A16 - A0
BES# BEF# OE# WE#
Control Logic
I/O Buffers
DQ7 - DQ0
3 4
A17
Address Buffers & Latches
2,097,152 bit EEPROM Cell Array
353 ILL B1.3
5
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 A17 VSS NC NC A10 DQ7 DQ6 DQ5 DQ4 VDD VDD NC DQ3 DQ2 DQ1 DQ0 OE# VSS BEF# A0
A11 A9 A8 A13 A14 A17 WE# VDD BES# A16 A15 A12 A7 A6 A5 A4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Standard Pinout Top View Die Up
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
OE# A10 BEF# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3
353 ILL F01A.1
A16 A15 A14 A13 A12 A11 A9 A8 WE# NC BES# NC NC A7 A6 A5 A4 A3 A2 A1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
6 7 8 9 10 11
Standard Pinout Top View Die Up
353 ILL F01.0
32-PIN TSOP PACKAGE (8mm x 14mm) FIGURE 1: PIN ASSIGNMENTS TABLE 2: PIN DESCRIPTION Symbol Pin Name A17-A0 Address Inputs
40-PIN TSOP PACKAGE (10mm x 14mm)
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Functions To provide memory addresses. During Flash Sector Erase A17-A12 address lines will select the sector. A17-A0 to provide flash address, A16-A0 to provide SRAM addresses. To output data during read cycles and receive input data during write cycles. Data is internally latched during a Flash Erase/Program cycle. The outputs are in tri-state when OE# or BES# and BEF# are high. To activate the SRAM memory bank when BES# is low. To activate the Flash memory bank when BEF# is low. To gate the data output buffers. To control the write operations. To provide 3.0-3.6V supply
353 PGM T2.5
13 14 15 16
DQ7-DQ0
Data Input/output
BES# BEF# OE# WE# VDD Vss
SRAM Memory Bank Enable Flash Memory Bank Enable Output Enable Write Enable Power Supply Ground
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Advance Information TABLE 3: OPERATION MODES SELECTION Mode BES# BEF# Flash Read X VIL Flash Program X VIL Flash Erase X VIL SRAM Read SRAM Write Standby Flash Write Inhibit VIL VIL VIHC X X X VIH VIH VIH VIH VIHC X X VIH VIL VIL OE# VIL VIH VIH VIL X X VIL X X VIL VIL WE# VIH VIL VIL VIH VIL X X VIH X VIH VIH A9 AIN AIN X AIN AIN X X X X VH AIN DQ DOUT DIN X DOUT DIN High Z High Z/DOUT High Z/DOUT High Z/DOUT Manufacturer Code (BF) Device Code (18) ID Code Address AIN AIN Sector address, XXh for Bank Erase AIN AIN X X X X A17 - A1 = VIL, A0 = VIL A17 - A1 = VIL, A0 = VIH See Table 4
353 PGM T3.3
Product Identification Hardware Mode Software Mode
TABLE 4: SOFTWARE COMMAND SEQUENCE FOR FLASH MEMORY BANK
1st Bus Write Cycle Addr(1) Data Byte Program 5555H AAH Sector Erase 5555H AAH Bank Erase 5555H AAH Software ID Entry 5555H AAH Software ID Exit 5555H AAH
Notes: Address format A14-A0 (Hex), Addresses A15, A16 and A17 are a "Don't Care" for the Command sequence. (2) SA for Sector Erase; uses A -A x 17 12 address lines (3) BA = Program Byte address Notes for Software ID Entry Command Sequence 1. With A17 -A1 =0; SST Manufacturer Code = BFH, is read with A0 = 0, 31LH021 Device Code = 18H, is read with A0 = 1. 2. The device does not remain in Software Product ID Mode if powered down.
(1)
Command Sequence
2nd Bus Write Cycle Addr(1) Data 2AAAH 55H 2AAAH 55H 2AAAH 55H 2AAAH 55H 2AAAH 55H
3rd Bus Write Cycle Addr(1) Data 5555H A0H 5555H 80H 5555H 80H 5555H 90H 5555H F0H
4th Bus Write Cycle Addr(1) Data BA(3) Data 5555H AAH 5555H AAH
5th Bus Write Cycle Addr(1) Data 2AAAH 2AAAH 55H 55H
6th Bus Write Cycle Addr(1) Data SAx(2) 30H 5555H 10H
353 PGM T4.1
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under "Absolute Maximum Stress Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Temperature Under Bias ................................................................................................................. -55C to +125C Storage Temperature ...................................................................................................................... -65C to +150C D. C. Voltage on Any Pin to Ground Potential ............................................................................. -0.5V to VDD+ 0.5V Transient Voltage (<20 ns) on Any Pin to Ground Potential ......................................................... -1.0V to VDD+ 1.0V Voltage on A9 Pin to Ground Potential ................................................................................................ -0.5V to 13.2V Package Power Dissipation Capability (Ta = 25C) ........................................................................................... 1.0W Surface Mount Lead Soldering Temperature (3 Seconds) ............................................................................... 240C Output Short Circuit Current(1) ................................................................................................................................................................. 50 mA
Note: (1) Outputs shorted for no more than one second. No more than one output shorted at a time.
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Advance Information OPERATING RANGE Range Ambient Temp Commercial 0 C to +70 C Industrial -40 C to +85 C AC CONDITIONS OF TEST VDD 3.0-3.6V 3.0-3.6V Input Rise/Fall Time ......... 5 ns Output Load ..................... CL = 30 pF See Figures 13 and 14
1 2
TABLE 5: DC OPERATING CHARACTERISTICS VDD = 3.0-3.6V Limits Symbol Parameter Min Max IDD Power Supply Current Read Flash SRAM Concurrent Operation Write Flash SRAM Standby VDD Current Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage 0.7VDD Input High Voltage (CMOS) VDD-0.3 Output Low Voltage Output High Voltage VDD-0.2 Supervoltage for A9 pin 11.4 Supervoltage Current for A9 pin 12 20 35 15 20 30 1 1 0.8
3
Units Test Conditions VDD = VDD Max, all DQs open, Address input = VIL/VIH, at f=1/TRC Min. OE# = VIL, WE# = VIH BEF# = VIL, BES# = VIH BEF# = VIH, BES# = VIL BEF# = VIH, BES# = VIL OE# = VIH, WE# = VIL BEF# = VIL, BES# = VIH BEF# = VIH, BES# = VIL VDD = VDD Max. BEF# = BES# = VIHC VIN =GND to VDD, VDD = VDD Max. VOUT =GND to VDD, VDD = VDD Max. VDD = VDD Min. VDD = VDD Max. VDD = VDD Max. IOL = 100 A, VDD = VDD Min. IOH = -100A, VDD = VDD Min. BEF# = OE# =VIL, WE# = VIH BEF# = OE# = VIL, WE# = VIH, A9 = VH Max.
353 PGM T5.5
4 5 6 7 8 9 10 11 12 13
mA mA mA mA mA A A A V V V V V V A
ISB ILI ILO VIL VIH VIHC VOL VOH VH IH
0.2 12.6 200
TABLE 6: RECOMMENDED SYSTEM POWER-UP TIMINGS Symbol Parameter TPU-READ TPU-WRITE(1)
(1)
Minimum 100 100
Units s s
353 PGM T6.0
Power-up to Read Operation Power-up to Write Operation
14
TABLE 7: CAPACITANCE (Ta = 25 C, f=1 Mhz, other pins open) Parameter Description Test Condition CI/O CIN(1)
(1)
Maximum 12 pF 6 pF
353 PGM T7.0
I/O Pin Capacitance Input Capacitance
VI/O = 0V VIN = 0V
15 16
Note: (1)This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
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Advance Information TABLE 8: RELIABILITY CHARACTERISTICS Symbol Parameter Minimum Specification NEND TDR(1) VZAP_HBM(1) VZAP_MM(1) ILTH(1)
(1)
Units Cycles Years Volts Volts mA
Test Method JEDEC Standard A117 JEDEC Standard A103 JEDEC Standard A114 JEDEC Standard A115 JEDEC Standard 78
353 PGM T8.1
Endurance Data Retention ESD Susceptibility Human Body Model ESD Susceptibility Machine Model Latch Up
10,000 100 2000 200 100 + IDD
Note: (1)This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 9: SRAM MEMORY BANK READ CYCLE TIMING PARAMETERS VDD = 3.0-3.6V Symbol Parameter Min Max TRC Read Cycle Time 25 TAA Address Access Time 25 TBE Bank Enable Access Time 25 TOE Output Enable Access Time 12 TBLZ(1) BES# to Active Output 0 TOLZ(1) Output Enable to Active Output 0 TBHZ(1) BES# to High-Z Output 10 (1) TOHZ Output Disable to High-Z Output 10 TOH Output Hold from Address Change 0
Unit ns ns ns ns ns ns ns ns ns
353 PGM T9.1
Note: (1) This parameter is measured only for initial qualification and after the design or process change that could affect this parameter.
TABLE 10: SRAM MEMORY BANK WRITE CYCLE TIMING PARAMETERS VDD = 3.0-3.6V Symbol Parameter Min Max TWC Write Cycle Time 25 TBW Bank Enable to End of Write 12 TAW Address Valid to End of Write 12 TAS Address Set-up Time 0 TWP Write Pulse Width 12 TWR Write recovery Time 0 TOES OE# High Setup Time 0 TOEH OE# High Hold Time 0 TDS Data Set-up Time 12 TDH Data Hold from Write Time 0
Unit ns ns ns ns ns ns ns ns ns ns
353 PGM T10.1
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Advance Information AC CHARACTERISTICS TABLE 11: FLASH READ CYCLE TIMING PARAMETERS VDD = 3.0-3.6V Symbol Parameter Min TRC Read Cycle time 70 TBE Bank Enable Access Time TAA Address Access Time TOE Output Enable Access Time (1) TBLZ BEF# Low to Active Output 0 (1) TOLZ OE# Low to Active Output 0 TBHZ(1) BEF# High to High-Z Output TOHZ(1) OE# High to High-Z Output (1) Output Hold from Address Change 0 TOH
Max 70 70 35
15 15
Units ns ns ns ns ns ns ns ns ns
353 PGM T11.2
1 2 3 4 5 6 7
Note: (1)This parameter is measured only for initial qualification and after the design or process change that could affect this parameter.
TABLE 12: FLASH PROGRAM/ERASE CYCLE TIMING PARAMETERS VDD = 3.0-3.6V Symbol Parameter Min Max TBP Byte Program time 20 TAS Address Setup Time 0 TAH Address Hold Time 30 TBS WE# and BEF# Setup Time 0 TBH WE# and BEF# Hold Time 0 TOES OE# High Setup Time 0 TOEH OE# High Hold Time 10 TBP BEF# Pulse Width 40 TWP WE# Pulse Width 40 TWPH WE# Pulse Width High 30 TBPH BEF# Pulse Width High 30 TDS Data Setup Time 40 TDH Data Hold Time 0 Software ID Access and Exit Time 150 TIDA TSE Sector Erase 25 TSBE Bank Erase 100
Units s ns ns ns ns ns ns ns ns ns ns ns ns ns ms ms
353 PGM T12.1
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Advance Information
TRC ADDRESS A16-0
TAA
BES#
TBE
OE# VIH WE# TOLZ
TOE
TOHZ TBHZ HIGH-Z DATA VALID
DQ7-0
HIGH-Z
TBLZ
TOH DATA VALID
353 ILL F02.1
FIGURE 2: SRAM READ CYCLE TIMING DIAGRAM
TWC ADDRESS A16-0 ADDRESS TAW OE# TOES TBW BES# TWP WE# TAS TDS I/O DATA VALID
353 ILL F03.2
TOEH
TWR
TDH
FIGURE 3: SRAM WRITE CYCLE TIMING DIAGRAM
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Advance Information
TRC ADDRESS A17-0
TAA
1 2
BEF#
TBE
OE# VIH WE# TOLZ
TOE
3
TOHZ TBHZ HIGH-Z DATA VALID
4 5 6 7
DQ7-0
HIGH-Z
TBLZ
TOH DATA VALID
353 ILL F18.0
FIGURE 4: FLASH READ CYCLE TIMING DIAGRAM
8 9
INTERNAL PROGRAM OPERATION STARTS TBP ADDRESS A17-0 5555 TAH TWP WE# TAS OE# TCH BEF# TCS DQ7-0 AA SW0 55 SW1 A0 SW2 DATA BYTE (ADDR/DATA) TWPH TDS 2AAA 5555 ADDR TDH
10 11 12 13 14 15
353 ILL F04.0
16
FIGURE 5: WE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM
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Advance Information
INTERNAL PROGRAM OPERATION STARTS TBP ADDRESS A17-0 5555 TAH TCP BEF# TAS OE# TCH WE# TCS DQ7-0 AA SW0 55 SW1 A0 SW2 DATA BYTE (ADDR/DATA) TCPH TDS 2AAA 5555 ADDR TDH
353 ILL F05.0
FIGURE 6: BEF# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM
ADDRESS A17-0 TCE BEF# TOEH OE# TOE WE# TOES
DQ7
D
D#
D#
D
353 ILL F06.0
FIGURE 7: DATA# POLLING TIMING DIAGRAM
(c) 1999 Silicon Storage Technology, Inc.
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2 Megabit Flash + 1 Megabit SRAM ComboMemory SST31LH021
Advance Information
1
ADDRESS A17-0 TBE BEF# TOEH OE# TOE TOES
2 3 4
WE#
5
DQ6
6
TWO READ CYCLES WITH SAME OUTPUTS 353 ILL F07.0
7
FIGURE 8: TOGGLE BIT TIMING DIAGRAM
8 9
SIX-BYTE CODE FOR SECTOR ERASE TSE SAX
ADDRESS A17-0
5555
2AAA
5555
5555
2AAA
10 11 12
BEF#
OE# TWP WE#
13
AA SW0
Note:
DQ7-0
55 SW1
80 SW2
AA SW3
55 SW4
30 SW5
14
353 ILL F08.0
15 16
The device also supports BE# controlled Sector Erase operation. The WE# and BE# signals are interchangeable as long as minimum timings are met. (See table 10) SAX = Sector Address
FIGURE 9: WE# CONTROLLED SECTOR ERASE TIMING DIAGRAM
(c) 1999 Silicon Storage Technology, Inc.
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2 Megabit Flash + 1 Megabit SRAM ComboMemory SST31LH021
Advance Information
SIX-BYTE CODE FOR BANK ERASE ADDRESS A17-0 5555 2AAA 5555 5555 2AAA 5555
TSBE
BEF#
OE# TWP WE#
DQ7-0
AA SW0
Note:
55 SW1
80 SW2
AA SW3
55 SW4
10 SW5
353 ILL F17.1
The device also supports BE# controlled Bank Erase operation. The WE# and BE# signals are interchangeable as long as minimum timings are met. (See table 10)
FIGURE 10: WE# CONTROLLED BANK ERASE TIMING DIAGRAM
Three-byte sequence for Software ID Entry ADDRESS A14-0 5555 2AAA 5555 0000 0001
BEF#
OE# TWP WE# TWPH DQ7-0 AA SW0 55 SW1 90 SW2 TAA BF MFG ID 18 DEVICE ID
353 ILL F09.1
TIDA
FIGURE 11: SOFTWARE ID ENTRY AND READ
(c) 1999 Silicon Storage Technology, Inc.
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2 Megabit Flash + 1 Megabit SRAM ComboMemory SST31LH021
Advance Information
THREE-BYTE SEQUENCE FOR SOFTWARE ID EXIT AND RESET
1 2
ADDRESS A14-0
5555
2AAA
5555
DQ7-0
AA
55
F0 TIDA
3 4
BEF#
OE# TWP WE# T WHP SW0 SW1 SW2
353 ILL F10.0
5 6 7
FIGURE 12: SOFTWARE ID EXIT AND RESET
8 9 10 11 12 13 14 15 16
(c) 1999 Silicon Storage Technology, Inc.
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2 Megabit Flash + 1 Megabit SRAM ComboMemory SST31LH021
Advance Information
VIHT VHT
INPUT REFERENCE POINTS
VHT
OUTPUT
VLT VILT
VLT
353 ILL F11.0
AC test inputs are driven at VIHT (0.9 VDD) for a logic "1" and VILT (0.1 VDD) for a logic "0". Measurement reference points for inputs and outputs are at VHT (0.7 VDD) and VLT (0.8 V) Input rise and fall times (10% 90%) are <5 ns.
Note: VHT-VHIGH Test VLT-VLOW Test VIHT-VINPUT HIGH Test VILT-VINPUT LOW Test
FIGURE 13: AC INPUT/OUTPUT REFERENCE WAVEFORMS
TEST LOAD EXAMPLE VDD TO TESTER RL HIGH
TO DUT CL RL LOW
353 ILL F12.0
FIGURE 14: A TEST LOAD EXAMPLE
(c) 1999 Silicon Storage Technology, Inc.
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2 Megabit Flash + 1 Megabit SRAM ComboMemory SST31LH021
Advance Information
Start
1 2 3
Write data: AA Address: 5555
Write data: 55 Address: 2AAA
4 5
Write data: A0 Address: 5555
6 7 8 9 10 11
353 ILL F13.0
Load Byte Address/Byte Data
Wait for end of Program (TBP, Data# Polling bit, or Toggle bit operation) Program Completed
12 13 14 15 16
FIGURE 15: BYTE PROGRAM ALGORITHM
(c) 1999 Silicon Storage Technology, Inc.
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2 Megabit Flash + 1 Megabit SRAM ComboMemory SST31LH021
Advance Information
Internal Timer Byte Program/Erase Initiated
Toggle Bit Byte Program/Erase Initiated
Data# Polling Byte Program/Erase Initiated
Wait TBP, TSBE, or TSE
Read byte
Read DQ7
Program/Erase Completed
Read same byte
No
Is DQ7 = true data? Yes
No
Does DQ6 match? Yes
Program/Erase Completed
Program/Erase Completed
353 ILL F14.0
FIGURE 16: WAIT OPTIONS
(c) 1999 Silicon Storage Technology, Inc.
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2 Megabit Flash + 1 Megabit SRAM ComboMemory SST31LH021
Advance Information
1
Software Product ID Entry Command Sequence
Write data: AA Address: 5555
Software Product ID Exit & Reset Command Sequence
Write data: AA Address: 5555 Write data: F0 Address: XX
2 3 4
Write data: 55 Address: 2AAA
Write data: 55 Address: 2AAA
Wait TIDA
5 6 7
Write data: 90 Address: 5555
Write data: F0 Address: 5555
Return to normal operation
Wait TIDA
Wait TIDA
8 9
Read Software ID
Return to normal operation
353 ILL F15.0
10 11 12 13
FIGURE 17: SOFTWARE PRODUCT COMMAND FLOWCHARTS
14 15 16
(c) 1999 Silicon Storage Technology, Inc.
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2 Megabit Flash + 1 Megabit SRAM ComboMemory SST31LH021
Advance Information
Chip Erase Command Sequence
Write data: AA Address: 5555
Sector Erase Command Sequence
Write data: AA Address: 5555
Write data: 55 Address: 2AAA
Write data: 55 Address: 2AAA
Write data: 80 Address: 5555
Write data: 80 Address: 5555
Write data: AA Address: 5555
Write data: AA Address: 5555
Write data: 55 Address: 2AAA
Write data: 55 Address: 2AAA
Write data: 10 Address: 5555
Write data: 30 Address: SAX
Wait TSCE
Wait TSE
Chip erased to FFH
Sector erased to FFH
353 ILL F16.0
FIGURE 18: ERASE COMMAND SEQUENCE
(c) 1999 Silicon Storage Technology, Inc.
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2 Megabit Flash + 1 Megabit SRAM ComboMemory SST31LH021
Advance Information
Concurrent Operation Load SDP Command Sequence
1 2 3
Flash Program/Erase Initiated
4 5
Wait for End of Write Indication
Read or Write SRAM
6 7 8
End Wait
Flash Operation Completed
9 10
End Concurrent Operation
353 ILL F19.0
11 12
FIGURE 19: CONCURRENT OPERATION FLOWCHART
13 14 15 16
(c) 1999 Silicon Storage Technology, Inc.
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2 Megabit Flash + 1 Megabit SRAM ComboMemory SST31LH021
Advance Information Device SST31LH021 Speed Suffix1 Suffix2 - XXX XX XX Package Modifier H = 32 leads I = 40 leads Numeric = Die modifier Package Type W = TSOP (die up) 8mm x 14mm, or 10mm x 14mm U = Unencapsulated die Temperature Range C = Commercial = 0 to 70C I = Industrial = -40 to 85C Minimum Endurance 4 = 10,000 cycles Read Access Speed 70 = 70 ns
SST31LH021 Valid combinations SST31LH021-70-4C-WI SST31LH021-70-4C-U1 SST31LH021-70-4C-WH SST31LH021-70-4I-WI SST31LH021-70-4I-WH
Example : Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations.
(c) 1999 Silicon Storage Technology, Inc.
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2 Megabit Flash + 1 Megabit SRAM ComboMemory SST31LH021
Advance Information PACKAGING DIAGRAMS
PIN # 1 IDENTIFIER 1.05 0.95 .50 BSC
1 2
8.10 7.90
.270 .170
3 4
12.50 12.30
0.15 0.05
5 6
0.70 0.50
14.20 13.80
7
Note: 1. Complies with JEDEC publication 95 MO-142 BA dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in metric (min/max). 3. Coplanarity: 0.1 (.05) mm.
32.TSOP-WH-ILL.2
8
32-PIN THIN SMALL OUTLINE PACKAGE (TSOP) 8MM X 14MM SST PACKAGE CODE: WH
9
1.05 0.95 .50 BSC
PIN # 1 IDENTIFIER
10 11
.270 .170
10.04 9.96
12 13
12.50 12.30
0.15 0.05
14 15
0.60 0.40
14.20 13.80
Note:
1. Complies with JEDEC publication 95 MO-142 CA dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in metric (min/max). 40.TSOP-WI-ILL.0 3. Coplanarity: 0.1 (.05) mm.
16
40-PIN THIN SMALL OUTLINE PACKAGE (TSOP) 10MM X 14MM SST PACKAGE CODE: WI
(c) 1999 Silicon Storage Technology, Inc.
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2 Megabit Flash + 1 Megabit SRAM ComboMemory SST31LH021
SALES OFFICES SST Area Offices
Customer Service Northwest USA, Rocky Mtns. & West Canada Central & Southwest USA East USA & East Canada North America - Distribution Asia Pacific East Asia Europe Northern Europe (408) 523-7754 (408) 523-7661 (727) 771-8819 (978) 356-3845 (941) 505-8893 (408) 523-7762 (81) 45-471-1851 (44) 1932-230555 (45) 3833-5000
Advance Information International Sales Representatives & Distributors
Australia ACD Belgium Memec Benelux China/Hong Kong Actron Technology Co., Ltd. (HQ) Hong Kong Actron Technology Co., Ltd. - Shanghai Actron Technology Co., Ltd. - Shenzhen Actron Technology Co., Ltd. - Chengdu Actron Technology Co., Ltd. - Beijing Actron Technology Co., Ltd. - Wuhan Actron Technology Co., Ltd. - Xian MetaTech Limited (HQ) - Hong Kong MetaTech Limited - Beijing MetaTech Limited - Shanghai MetaTech Limited - Chengdu MetaTech Limited - Fuzhou MetaTech Limited - Shenzhen Serial System Ltd. - Hong Kong Serial System Ltd. - Chengdu Serial System Ltd. - Shanghai Serial System Ltd. - Shenzhen Denmark C-88 AS Finland Memec Finland Oy France A2M - Bron A2M - Sevres Germany Endrich Bauelemente Vertriebs GMBH - Bramstedt Endrich Bauelemente Vertriebs GMBH - Nagold India Team Technology - Bangalore Team Technology - Hyderabad Team Technology - New Delhi Ireland Curragh Technology Israel Spectec Electronics Italy Carlo Gavazzi Cefra SpA Japan Asahi Electronics Co., Ltd. - Tokyo Asahi Electronics Co., Ltd. - Kitakyushu Microtek, Inc. - Osaka Microtek, Inc. - Tokyo Ryoden Trading Co., Ltd. - Osaka Ryoden Trading Co., Ltd. - Tokyo Silicon Technology Co., Ltd. Korea Bigshine Korea Co., Ltd. Malaysia MetaTech (M) SDN BHD Serial System SDN BHD Serial System - Kuala Lumpur Netherlands Memec Benelux Norway Endrich Elektronikk AS Singapore MetaTech (S) Pte Ltd. Serial System Ltd. (HQ) South Africa KH Distributors Spain Tekelec Espana S.A. Sweden Memec Scandinavia Switzerland Leading Technologies Taiwan, R.O.C. GCH-Sun Systems Co., Ltd. (GSS) PCT Limited Tonsam Corporation United Kingdom Ambar Components, Ltd.
(61) 3-762 7644 (32) 1540-0080 (852) 2727-3978 (86) 21-6482-8021 (86) 755-376-2763 (86) 28-553-2896 (86) 10-6261-0042 (86) 27-8788-7226 (86) 29-831-4585 (852) 2421-2379 (86) 10-6858-2188 (86) 21-6485-7530 (86) 28-5577-415 (86) 591-378-1033 (86) 755-321-9726 (852) 2950-0820 (86) 28-524-0208 (86) 21-6473-2080 (86) 755-212-9076 (45) 7010-4888 (358)9 350 8880 (33) 4 72 37 0414 (33) 1 46 23 7900
North American Sales Representatives
Alabama M-Squared, Inc. - Huntsville Arizona QuadRep, Inc. California Costar - Northern Falcon Sales & Technology - San Marcos Westar Rep Company, Inc. - Calabasas Westar Rep Company, Inc. - Irvine Colorado Lange Sales, Inc. Florida M-Squared, Inc. - Clearwater M-Squared, Inc. - Coral Springs M-Squared, Inc. - Longwood Georgia M-Squared, Inc. - Atlanta Illinois Oasis Sales Corporation - Northern Rush & West Associates - Southern Indiana Applied Data Management Iowa Rush & West Associates Kansas Rush & West Associates Maryland Nexus Technology Sales Massachusetts A/D Sales Michigan Applied Data Management Minnesota Cahill, Schmitz & Cahill Missouri Rush & West Associates North Carolina M-Squared, Inc. - Charlotte M-Squared, Inc. - Raleigh New Jersey Nexus Technology Sales New Mexico QuadRep, Inc. New York Nexus Technology Sales Reagan/Compar - Endwell Reagan/Compar - E. Rochester Ohio Applied Data Management - Cincinnati Applied Data Management - Cleveland Oregon Thorson Pacific, Inc. Pennsylvania Nexus Technology Sales Texas Technical Marketing, Inc. - Carrollton Technical Marketing, Inc. - Houston Technical Marketing, Inc. - Austin Utah Lange Sales, Inc. Washington Thorson Pacific, Inc. Wisconsin Oasis Sales Corporation Canada Electronics Sales Professionals - Ottawa Electronics Sales Professionals - Toronto Electronics Sales Professionals - Montreal Thorson Pacific, Inc. - B.C.
(205) 830-0498 (602) 839-2102 (408) 946-9339 (760) 591-0504 (818) 880-0594 (949) 453-7900 (303) 795-3600 (727) 669-2408 (954) 753-5314 (407) 682-6662 (770) 447-6124 (847) 640-1850 (314) 965-3322 (317) 257-8949 (319) 398-9679 (913) 764-2700 (301) 663-4159 (978) 851-5400 (734) 741-9292 (612) 699-0200 (314) 965-3322 (704) 522-1150 (919) 848-4300 (201) 947-0151 (505) 332-2417 (516) 843-0100 (607) 754-2171 (716) 218-4370 (513) 579-8108 (440) 946-6812 (503) 293-9001 (215) 675-9600 (972) 387-3601 (713) 783-4497 (512) 343-6976 (801) 487-0843 (425) 603-9393 (414) 782-6660 (613) 828-6881 (905) 856-8448 (514) 344-0420 (604) 294-3999
(49) 4192-897910 (49) 7452-60070 (91) 80-526-1102 (91) 40-231130 (91) 11-220-5624 (353) 61 316116 (972) 3-6498404 (39) 2-424-1471 (81) 3-3350-5418 (81) 93-511-6471 (81) 6-6263-5080 (81) 3-5300-5515 (81) 6-6399-3443 (81) 3-5396-6218 (81) 3-3795-6461 (82) 2-832-8881 (60)4-658-4276 (60) 4-657-0204 (60) 3-737-1243 (31) 40-265-9399 (47) 22 52 13 20 (65) 748-4844 (65) 280-0200 (27) 11 845-5011 (34) 91 371-7768 (46)8-459-7900 (41) 27-721-7440/43 (886) 2-2555-0880 (886) 2-2698-0098 (886) 2-2651-0011 (44) 1296-397396
Revised 5-18-99
Silicon Storage Technology, Inc. * 1171 Sonora Court * Sunnyvale, CA 94086 * Telephone 408-735-9110 * Fax 408-735-9036 www.SuperFlash.com or www.ssti.com * Literature FaxBack 888-221-1178, International 732-544-2873
(c) 1999 Silicon Storage Technology, Inc.
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