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| INTEGRATED CIRCUITS DATA SHEET SAA7724H Car radio digital signal processor Preliminary specification 2003 Nov 18 Philips Semiconductors Preliminary specification Car radio digital signal processor CONTENTS 1 2 2.1 2.2 2.3 3 4 5 6 6.1 6.2 6.2.1 6.2.2 6.2.3 6.2.4 6.2.5 6.3 6.3.1 6.3.2 6.4 6.4.1 6.4.2 6.4.3 6.4.4 6.5 6.6 6.6.1 6.6.2 6.7 6.7.1 6.7.2 6.8 6.8.1 6.8.2 6.8.3 6.8.4 6.8.5 6.8.6 6.9 6.9.1 FEATURES GENERAL INFORMATION DSP radio system SAA7724H Sample rates ORDERING INFORMATION BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION Voltage regulator Audio analog front-end Selector diagram Realization of the common mode input with AIN Realization of the differential ADIFF input Realization of the auxiliary input with volume control Supplies and references AD decimation paths (DAD) LDF and AUX decimation path ADF and audio decimation path Digital audio input/output General External I2S-bus input/output ports External SPDIF input EPICS host I2S-bus port Sample rate converter IF_AD IF_AD single block diagram IF_AD detailed functional description AUDIO_EPICS specific information AUDIO_EPICS start-up AUDIO_EPICS memory overview SDAC output path DAC upsampling filter DAC noise shaper DAC CoDEM scrambler Multi-bit SDAC Analog summer function SDAC application diagram Reset block functional overview Asynchronous reset 6.10 6.10.1 6.10.2 6.10.3 6.10.4 6.11 6.12 6.12.1 6.12.2 6.12.3 6.12.4 6.12.5 7 8 9 10 10.1 11 11.1 11.1.1 11.2 11.3 11.4 11.5 12 12.1 12.2 12.3 13 14 14.1 14.2 14.3 14.4 14.5 15 16 17 18 Clock circuit and oscillator Circuit description External clock input mode Crystal oscillator supply Application guidelines PLL circuits RDS General description RDS I/O modes RDS demodulator RDS bit buffer RDS/RBDS decoder LIMITING VALUES THERMAL RESISTANCE DC CHARACTERISTICS AC CHARACTERISTICS Timing diagrams I2C-BUS CONTROL SAA7724H I2C-bus protocol Protocol of the I2C-bus commands MPI data transfer formats Reset initialization Defined I2C-bus address I2C-bus memory map specification I2S-BUS CONTROL Basic system requirements Serial data Word select PACKAGE OUTLINE SOLDERING Introduction to soldering surface mount packages Reflow soldering Wave soldering Manual soldering Suitability of surface mount IC packages for wave and reflow soldering methods DATA SHEET STATUS DEFINITIONS DISCLAIMERS PURCHASE OF PHILIPS I2C COMPONENTS 2003 Nov 18 2 Philips Semiconductors Preliminary specification Car radio digital signal processor 1 FEATURES SAA7724H * AM and FM digitize at IF * AM and FM narrow-band/IF AGC * AM and FM IF filtering * AM and FM adjustable channel detection/variable IF * IF filter for WX * AM and FM demodulation * AM and FM stereo decoding * AM and FM stereo pilot detection * FM pilot notch * AM pilot filter * FM stereo blend, high blend, high cut, soft muting and de-emphasis * AM stereo blend, LP filter, high cut and soft muting * AM and FM noise blanker * AM and FM gain adjust and calibration (audio) * FM multipath detection * FM multipath correction * Diversity switching * Radio Data System (RDS) and Radio Broadcast Data System (RBDS) demodulation and decoding * Tape head calibration, equalization, Dolby B and AMS (from analog tape input) 1.1 Sample rates The SAA7724H runs at a master clock of 43.2 MHz. Audio processing runs at a sample rate of 43.2 MHZ 1 x f s = 42.1875 kHz = ------------------------1024 * CD gain adjust, calibration and compression (from analog or digital SPDIF/I2S-bus input) * Parametric equalization * Volume control * Bass control * Treble control * Balance/fade control * DC blocking filter * Dual source select * Dual playback * Channel delays * Analog summer for four channels (through inputs MONO1 and MONO2) * Audio limiting. 2003 Nov 18 3 Philips Semiconductors Preliminary specification Car radio digital signal processor 2 2.1 GENERAL INFORMATION DSP radio system 2.2 SAA7724H SAA7724H The Digital Signal Processing (DSP) radio system (see Fig.1) consists of: * Analog tuner (also called RF/IF) * SAA7724H * Audio power amplifier * Microcontroller * IF co-processor * Audio co-processor. The microcontroller interfaces to the RF/IF and SAA7724H via an I2C-bus. Analog tape and CD inputs are input from other parts of the radio. The IF co-processor and audio co-processor interfaces to the SAA7724H via an I2S-bus. The SAA7724H digitizes up to two IF signals and performs DSP to generate left front, right front, left rear, and right rear audio and RDS/RBDS data output. The SAA7724H also samples analog baseband tape, FM MPX, AUX inputs, analog and digital CD, performs signal processing on these sampled waveforms and multiplexes the proper signal to the output. A microcontroller interface allows the SAA7724H to be controlled and monitored. The SAA7724H is composed of hardwired and programmable DSP circuitry, with programmable parameters, such as injection frequencies, filter coefficients and control parameters. Some functions or groups of functions are implemented with programmable sequence processors. handbook, full pagewidth AUDIO CO-PROCESSOR 10.7 MHz/FM 450 kHz/AM IF ANALOG TUNER I2Sbus IF CO-PROCESSOR I2Sbus AUDIO POWER AMPLIFIER SAA7724H I2Cbus Tape, CD analog, Aux, CD digital, FM MPX MICROCONTROLLER MGW194 Fig.1 System overview. 2003 Nov 18 4 Philips Semiconductors Preliminary specification Car radio digital signal processor 3 ORDERING INFORMATION TYPE NUMBER SAA7724H PACKAGE NAME QFP100 DESCRIPTION plastic quad flat package; 100 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm SAA7724H VERSION SOT317-3 2003 Nov 18 5 Philips Semiconductors Preliminary specification Car radio digital signal processor 4 BLOCK DIAGRAM SAA7724H handbook, full pagewidth VDD(REG) VDD(I/O2) VDD(I/O3) VSS(I/O1) VSS(I/O2) VSS(I/O3) VSS(I/O4) 58 VDACN VDACP 10 VDDA2 9 1 8 26 33 34 44 45 AAD IFSS1 IFSS2 MONO1_N MONO1_P MONO2_N MONO2_P ADIFF_RP ADIFF_RN ADIFF_LP ADIFF_LN AIN1_R AIN1_REF AIN1_L AIN2_R AIN2_REF AIN2_L 85 86 3 2 5 4 99 100 97 98 89 88 87 96 95 94 AUDIOAD_2 ADF1_2 16 ch1_wide_narrow AUDIOAD_1 SELECTOR ADF1_1 16 AUXAD_2 LDF_2 16 4 AUXAD_1 LDF_1 16 4 aux1_sel_lev_voice COMP FILTER aux2_sel_lev_voice COMP FILTER LPF_1 LPF_2 ADF2_1 8 DC OFFSET SAT ch1_dc_offset ADF2_2 8 DC OFFSET SAT ch2_dc_offset ch2_wide_narrow SPDIF1 EXT_IIS_WS1 EXT_IIS_BCK1 EXT_IIS_IO1 14 20 SPDIF_1 A IFSS2H IFSS1H IFSS2L AAD2L AAD1L EXTIIS_1 IFSS1L AAD2H AAD1H SRC_1 SRC-EPICS bus 21 22 EXT_IIS_IO2 EXT_IIS_BCK2 EXT_IIS_WS2 SPDIF2 25 24 23 15 EXTIIS_2 SAA7724H SRC_2 SPDIF_2 DIT1 SWB-EPICS bus and FLAG IF_IN1 IF_VG IF_IN2 IFP_IIS_IN1 IFP_IIS_I2O6 IFP_IIS_I3O4 IFP_IIS_OUT1 IFP_IIS_OUT2 IFP_IIS_OUT3 IFP_IIS_OUT5 IFP_IIS_WS IFP_IIS_BCK 82 83 84 38 39 40 41 42 43 35 47 46 B IF_AD AND DITHER IF_AD AND DITHER DIT2 BOOT ROM IFP SWB AND INTERFACES MPX1 IFP status C D E MPX2 F IFP I2S-bus FLAG G MGW191 Fig.2 Block diagram (continued in Fig.3). 2003 Nov 18 6 Philips Semiconductors Preliminary specification Car radio digital signal processor SAA7724H handbook, full pagewidth VSSD6 VDDD1(MEM) CONREG GAPREG FEBREG 64 65 66 67 68 69 70 71 79 72 73 74 80 81 90 91 92 VOLTAGE REGULATOR VREFAD 93 11 VDD(IF) VSS(IF) VREFIF VADCN VADCP VDDD2 VDDD3 VDDA1 VSSD1 VSSD2 VSSD5 VSSD3 SAA7724H INTERPOLATOR 128 NOISE SHAPER RFV LFV RRV LRV F R SDAC_F 12 6 SDAC_R 7 27 28 29 37 SRC-EPICS bus EPICS I2S-bus DIO 36 30 31 32 54 55 ch.st. SPDIF_1 ch.st. SPDIF_2 IIC_REG 56 57 59 60 lock SPDIF_1 lock SPDIF_2 AUDIO_EPICS 61 62 63 SWB-EPICS bus and LFLAG IIS_IN1 IIS_IN2 IIS_IN3 IIS_WS IIS_BCK IIS_OUT1 IIS_OUT2 IIS_OUT3 DSP_IO0 DSP_IO1 DSP_IO2 DSP_IO3 DSP_IO4 DSP_IO5 DSP_IO6 DSP_IO7 DSP_IO8 A B C D E MPX1 RDSDEM_1 RDSDEC_1 TCB MPX2 RDS RDSDEM_2 RDSDEC_2 MPI OSCILLATOR AND CLOCK RESET PLL1 PLL2 IFP status AUDIO_EPICS SRC_EPICS F G FLAG sel_rds_clk1_davn2 sel_davn2_rds_flag 50 RDS_CLK2 51 RDS_DATA2 52 RDS_CLK1_DAVN2 53 RDS_DATA1_DAVN1 49 48 13 SDA SCL A0 17 19 18 RTCB TSCAN SHTCB 16 RESET 75 78 77 76 VDD(OSC) VSS(OSC) OSC_OUT OSC_IN MGW192 Fig.3 Block diagram (continued from Fig.2) 2003 Nov 18 7 Philips Semiconductors Preliminary specification Car radio digital signal processor 5 PINNING Functional pin description SYMBOL VDD(REG) MONO1_P MONO1_N MONO2_P MONO2_N RRV LRV VDACN VDDA2 VDACP RFV LFV A0 SPDIF1 SPDIF2 RESET TSCAN SHTCB RTCB EXT_IIS_WS1 EXT_IIS_BCK1 EXT_IIS_IO1 EXT_IIS_WS2 EXT_IIS_BCK2 EXT_IIS_IO2 VSS(I/O1) IIS_IN1 IIS_IN2 IIS_IN3 IIS_OUT1 IIS_OUT2 IIS_OUT3 VSS(I/O2) VDD(I/O2) IFP_IIS_OUT5 IIS_BCK IIS_WS IFP_IIS_IN1 2003 Nov 18 PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 DESCRIPTION SAA7724H Table 1 supply voltage for 2.5 V regulator circuit and bias for ADCs (3.3 V) differential positive analog input to AUX_AD2, AUDIOAD_1 and AUDIOAD_2 differential negative analog input to AUX_AD2, AUDIOAD_1 and AUDIOAD_2 differential positive analog input to AUX_AD2, AUDIOAD_1 and AUDIOAD_2 differential negative analog input to AUX_AD2, AUDIOAD_1 and AUDIOAD_2 analog audio voltage output for the right-rear speaker analog audio voltage output for the left-rear speaker negative reference voltage for the SDAC analog supply voltage for the SDAC (2.5 V) positive reference voltage for the SDAC analog audio voltage output for the right-front speaker analog audio voltage output for the left-front speaker slave subaddress for I2C-bus selection SPDIF input channel 1 from digital media source SPDIF input channel 2 from digital media source reset input (active LOW) scan control shift clock test control block asynchronous reset test control block (active LOW) word select input from digital media source 1 (I2S-bus) bit clock input from digital media source 1 (I2S-bus) data input/output digital media source 1 (I2S-bus) word select input from digital media source 2 (I2S-bus) bit clock input from digital media source 2 (I2S-bus) data input/output digital media source 2 (I2S-bus) ground supply 1 for external digital ports data channel input 1 (front channels) from external DSP IC (I2S-bus) data channel input 2 (rear channels) from external DSP IC (I2S-bus) data channel input 3 from external DSP IC (I2S-bus) data channel output 1 for external DSP IC activated by en_host_io (I2S-bus) data channel output 2 to external DSP IC activated by en_host_io (I2S-bus) data channel output 3 to external DSP IC activated by en_host_io (I2S-bus) ground supply 2 for external digital ports supply voltage 2 for external digital ports (3.3 V) IFP data channel output 5 to external DSP IC activated by ifp_iis_en; can also be used as 256 x fs clock output enabled by en_256FS (I2S-bus) clock output for external DSP IC enabled by en_host_io (I2S-bus) word select output for external DSP IC enabled by en_host_io (I2S-bus) IFP data channel input 1 from external DSP IC (I2S-bus) 8 Philips Semiconductors Preliminary specification Car radio digital signal processor SAA7724H SYMBOL IFP_IIS_I2O6 IFP_IIS_I3O4 IFP_IIS_OUT1 IFP_IIS_OUT2 IFP_IIS_OUT3 VDD(I/O3) VSS(I/O3) IFP_IIS_BCK IFP_IIS_WS SCL SDA RDS_CLK2 RDS_DATA2 RDS_CLK1_DAVN2 RDS_DATA1_DAVN1 DSP_IO0 DSP_IO1 DSP_IO2 DSP_IO3 VSS(I/O4) DSP_IO4 DSP_IO5 DSP_IO6 DSP_IO7 DSP_IO8 VSSD6 VDDD1(MEM) VSSD1 VDDD2 VSSD2 VSSD5 VDDD3 VSSD3 CONREG FEBREG GAPREG VSS(OSC) OSC_IN PIN 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 DESCRIPTION IFP data channel input 2 from external DSP IC or output data channel 6 to external DSP IC selected by ifp_iis_io_mode (I2S-bus) IFP data channel input 3 from external DSP IC or output data channel 4 to external DSP IC selected by ifp_iis_io_mode (I2S-bus) IFP data channel output 1 to external DSP IC activated by ifp_iis_en (I2S-bus) IFP data channel output 2 to external DSP IC activated by ifp_iis_en (I2S-bus) IFP data channel output 3 to external DSP IC activated by ifp_iis_en (I2S-bus) supply voltage 3 for external digital ports (3.3 V) ground supply 3 for external digital ports IFP output clock for external DSP IC enabled by ifp_iis_en (I2S-bus) IFP word select output for external DSP IC enabled by ifp_iis_en (I2S-bus) serial clock input (I2C-bus) serial data input/output (I2C-bus) RDS2 bit clock input/output; default input enabled by rds2_clkin RDS2 data output of RDS2 demodulator DAVN2 or RDS1 bit clock input/output; default input enabled by rds1_clkin RDS1 data output of RDS1 demodulator or RDS1 decoder DAVN1 general purpose input/output for EPICS (F0 of status register) general purpose input/output for EPICS (F1 of status register) general purpose input/output for EPICS (F2 of status register) general purpose input/output for EPICS (F3 of status register) ground supply 4 for external digital ports general purpose input/output for EPICS (F4 of status register) general purpose input/output for EPICS (F5 of status register) general purpose input/output for EPICS (F6 of status register) general purpose input/output for EPICS (F7 of status register) general purpose input/output for EPICS (F8 of status register) ground supply for digital circuitry digital supply voltage 1 for memories (2.5 V) digital ground supply 1 digital supply voltage 2 (2.5 V) digital ground supply 2 digital ground supply 5 digital supply voltage 3 (2.5 V) digital ground supply 3 2.5 V regulator control output 2.5 V regulator feedback input band gap reference decoupling pin for voltage regulator ground supply for crystal oscillator circuitry crystal oscillator input: local crystal oscillator sense for gain control or forced input in slave mode 2003 Nov 18 9 Philips Semiconductors Preliminary specification Car radio digital signal processor SAA7724H SYMBOL OSC_OUT VDD(OSC) VSS(IF) VREFIF VDD(IF) IF_IN1 IF_VG IF_IN2 IFSS1 IFSS2 AIN1_L AIN1_REF AIN1_R VDDA1 VADCP VADCN VREFAD AIN2_L AIN2_REF AIN2_R ADIFF_LP ADIFF_LN ADIFF_RP ADIFF_RN PIN 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 DESCRIPTION crystal oscillator output: drive output to crystal positive supply voltage for crystal oscillator circuitry IF_AD ground supply IF_AD reference voltage output IF_AD 2.5 V supply voltage analog input to IF_AD1 from tuner IF output IF_AD virtual ground analog input to IF_AD2 from tuner IF output analog IFSS1 input to AUXAD_1 analog IFSS2 input to AUXAD_2 analog input 1 to AAD for left input buffer signal common reference voltage input for AIN1 input buffer analog input 1 to AAD for right input buffer signal analog supply voltage 1 for AUXAD and AAD analog circuitry (2.5 V) positive reference voltage input for AAD ground reference voltage input for AAD common mode reference voltage output for AAD, AUXAD and buffers analog input 2 to AAD for left input buffer signal common reference voltage input for AIN2 input buffer analog input 2 to AAD for right input buffer signal analog input to AAD for left positive differential signal analog input to AAD for left negative differential signal analog input to AAD for right positive differential signal analog input to AAD for right negative differential signal 2003 Nov 18 10 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... Table 2 Application requirements and padcell type per pin 2003 Nov 18 11 Philips Semiconductors Car radio digital signal processor SYMBOL VDD(REG) MONO1_P MONO1_N MONO2_P MONO2_N RRV LRV VDACN VDDA2 VDACP RFV LFV A0 SPDIF1 SPDIF2 RESET TSCAN SHTCB RTCB EXT_IIS_WS1 EXT_IIS_BCK1 EXT_IIS_IO1 EXT_IIS_WS2 EXT_IIS_BCK2 EXT_IIS_IO2 VSS(I/O1) IIS_IN1 IIS_IN2 IIS_IN3 PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 - - - - - - - - - - - - DIGITAL I/O LEVELS APPLICATION DIGITAL FUNCTION - - - - - - - - - - - - input - - input input input input input input bi-directional input input bi-directional - input input input - - - - - - - - - - - - - - - PIN STATE AFTER RESET HYSTERESIS REQUIRED - - - - - - - - - - - - yes - - yes yes yes yes yes yes yes yes yes yes - yes yes yes INTERNAL PULL-DOWN - - - - - - - - - - - - pull-down - - pull-down pull-down pull-down pull-down pull-down pull-down pull-down pull-down pull-down pull-down - pull-down pull-down pull-down CELL NAME(1) vddco apio apio apio apio apio apio vssco vddco vddco apio apio ipthdt5v apio apio ipthdt5v ipthdt5v ipthdt5v ipthdt5v ipthdt5v ipthdt5v bpts10tht5v ipthdt5v 0 to 5 V DC tolerant - - 0 to 5 V DC tolerant 0 to 5 V DC tolerant 0 to 5 V DC tolerant 0 to 5 V DC tolerant 0 to 5 V DC tolerant 0 to 5 V DC tolerant 0 to 5 V DC tolerant 0 to 5 V DC tolerant 0 to 5 V DC tolerant 0 to 5 V DC tolerant - 0 to 3.3 V DC 0 to 3.3 V DC 0 to 3.3 V DC input input input input input input input input input input - input input input Preliminary specification ipthdt5v bpts10tht5v vsse3v3 bpt4mthd bpt4mthd bpt4mthd SAA7724H This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 2003 Nov 18 12 Philips Semiconductors DIGITAL I/O LEVELS 0 to 3.3 V DC 0 to 3.3 V DC 0 to 3.3 V DC - - 0 to 3.3 V DC 0 to 3.3 V DC 0 to 3.3 V DC 0 to 3.3 V DC 0 to 3.3 V DC 0 to 3.3 V DC 0 to 3.3 V DC 0 to 3.3 V DC 0 to 3.3 V DC - - 0 to 3.3 V DC 0 to 3.3 V DC 0 to 5 V DC tolerant 0 to 5 V DC tolerant 0 to 5 V DC tolerant 0 to 5 V DC tolerant APPLICATION DIGITAL FUNCTION output output output - - output output output input bi-directional bi-directional output output output - - output output input bi-directional bi-directional output Car radio digital signal processor SYMBOL IIS_OUT1 IIS_OUT2 IIS_OUT3 VSS(I/O2) VDD(I/O2) IFP_IIS_OUT5 IIS_BCK IIS_WS IFP_IIS_IN1 IFP_IIS_I2O6 IFP_IIS_I3O4 IFP_IIS_OUT1 IFP_IIS_OUT2 IFP_IIS_OUT3 VDD(I/O3) VSS(I/O3) IFP_IIS_BCK IFP_IIS_WS SCL SDA RDS_CLK2 RDS_DATA2 PIN 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 PIN STATE AFTER RESET output and LOW level output and LOW level output and LOW level - - output and LOW level 3-state 3-state input input input output and LOW level output and LOW level output and LOW level - - 3-state 3-state input input input output mode (level depends on RDS data) input output mode (level depends on RDS data) input input input HYSTERESIS REQUIRED - - - - - - - - yes yes yes - - - - - - - yes - yes - INTERNAL PULL-DOWN - - - - - - - - pull-down pull-down pull-down - - - - - - - - - - - CELL NAME(1) ops10c ops10c ops10c vsse3v3 vdde3v3 ops10c ot4mc ots10c ipthd bpts10thd bpts10thd ops10c ops10c ops10c vdde3v3 vsse3v3 ot4mc ots10c iptht5v iic400kt5v bptons10tht5v bptons10tht5v RDS_CLK1_DAVN2 RDS_DATA1_DAVN1 52 53 0 to 5 V DC tolerant 0 to 5 V DC tolerant bi-directional output yes - - bptons10tht5v bptons10tht5v Preliminary specification SAA7724H DSP_IO0 DSP_IO1 DSP_IO2 54 55 56 0 to 5 V DC tolerant 0 to 5 V DC tolerant 0 to 5 V DC tolerant bi-directional bi-directional bi-directional yes yes yes - - - bptons10tht5v bptons10tht5v bptons10tht5v This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 2003 Nov 18 13 Philips Semiconductors DIGITAL I/O LEVELS 0 to 5 V DC tolerant - 0 to 5 V DC tolerant 0 to 5 V DC tolerant 0 to 5 V DC tolerant 0 to 5 V DC tolerant 0 to 5 V DC tolerant - - - - - - - - - - - - - - - - - - - - - - - APPLICATION DIGITAL FUNCTION bi-directional - bi-directional bi-directional bi-directional bi-directional bi-directional - - - - - - - - - - - - - - - - - - - - - - - - input input input input input - - - - - - - - - - - - - - - - - - - - - - - Car radio digital signal processor SYMBOL DSP_IO3 VSS(I/O4) DSP_IO4 DSP_IO5 DSP_IO6 DSP_IO7 DSP_IO8 VSSD6 VDDD1(MEM) VSSD1 VDDD2 VSSD2 VSSD5 VDDD3 VSSD3 CONREG FEBREG GAPREG VSS(OSC) OSC_IN OSC_OUT VDD(OSC) VSS(IF) VREFIF VDD(IF) IF_IN1 IF_VG IF_IN2 IFSS1 IFSS2 PIN 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 PIN STATE AFTER RESET input HYSTERESIS REQUIRED yes - yes yes yes yes yes - - - - - - - - - - - - - - - - - - - - - - - INTERNAL PULL-DOWN - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - CELL NAME(1) bptons10tht5v vsse3v3 bptons10tht5v bptons10tht5v bptons10tht5v bptons10tht5v bptons10tht5v vssis vddco vssis vddi vssis vssis vddi vssis apio apio apio vssco apio apio vddco vssco apio Preliminary specification vddco aprf apio aprf apio apio SAA7724H This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 2003 Nov 18 14 Philips Semiconductors DIGITAL I/O LEVELS - - - - - - - - - - - - - - APPLICATION DIGITAL FUNCTION - - - - - - - - - - - - - - - - - - - - - - - - - - - - Car radio digital signal processor SYMBOL AIN1_L AIN1_REF AIN1_R VDDA1 VADCP VADCN VREFAD AIN2_L AIN2_REF AIN2_R ADIFF_LP ADIFF_LN ADIFF_RP ADIFF_RN Note 1. See Table 3. PIN 87 88 89 90 91 92 93 94 95 96 97 98 99 100 PIN STATE AFTER RESET HYSTERESIS REQUIRED - - - - - - - - - - - - - - INTERNAL PULL-DOWN - - - - - - - - - - - - - - CELL NAME(1) apio apio apio vddco apio apio apio apio apio apio apio apio apio apio Preliminary specification SAA7724H Philips Semiconductors Preliminary specification Car radio digital signal processor Table 3 Used padcells and functional specification; notes 1 and 2 LIBRARY NAME FUNCTIONAL SPECIFICATION SAA7724H PADCELL NAME Inputs ipthd iptht5v ipthdt5v Outputs ot4mc ops10c ots10c I/Os iic400kt5v bpt4mthd bpts10thd bpts10tht5v bptons10tht5v Special apio aprf Supply vddco vssco vddi vssis vdde3v3 vsse3v3 Notes iolib_nlm iolib_nlm_danger iolib_nlm_danger input pad; hysteresis; pull-down; TTL levels input pad; hysteresis; TTL levels; 5 V tolerant input pad; hysteresis; pull-down; TTL levels; 5 V tolerant iolib_nlm iolib_nlm iolib_nlm output; 3-state; 4 mA output plain; 10 ns slew rate output; 3-state; 10 ns slew rate input/output; 400 kHz I2C-bus special cell; 5 V tolerant input/output; 4 mA; hysteresis; pull-down; TTL input levels input/output; 10 ns slew rate; hysteresis; pull-down; TTL input levels input/output; 10 ns slew rate; hysteresis; TTL input levels; 5 V tolerant input/output; open-drain N-channel; 10 ns slew rate; hysteresis; TTL input levels; 5 V tolerant iolib_nlm_danger iolib_nlm iolib_nlm iolib_nlm_danger iolib_nlm_danger iolib_nlm iolib_nlm analog pad input or output analog high frequency pad input or output iolib_nlm iolib_nlm iolib_nlm iolib_nlm iolib_nlm iolib_nlm VDD core only supply; not connected to internal supply ring VSS core only supply; not connected to internal supply ring VDD core supply; connected to internal supply ring VSS core supply; connected to internal supply ring and substrate VDD supply peripheral only VSS supply peripheral only 1. All pull-down inputs or disabled I/Os with pull-down, may be left open-circuit. Internally the logic level is guaranteed LOW, but the pull-down doesn't behave as a normal resistor seen at the pin itself. 2. 5 V tolerant means that the input or 3-stated/disabled output is functioning correctly and will not be damaged when applying externally 5 V, and can thus be used in a normal application. The tolerances of the 5 V are given in the limiting values; see Chapter 7. 2003 Nov 18 15 Philips Semiconductors Preliminary specification Car radio digital signal processor SAA7724H 100 ADIFF_RN 99 ADIFF_RP 95 AIN2_REF 93 VREFAD handbook, full pagewidth 88 AIN1_REF 98 ADIFF_LN 97 ADIFF_LP VDD(REG) MONO1_P MONO1_N MONO2_P MONO2_N RRV LRV VDACN VDDA2 1 2 3 4 5 6 7 8 9 81 VDD(IF) 96 AIN2_R 89 AIN1_R 92 VADCN 91 VADCP 94 AIN2_L 87 AIN1_L 90 VDDA1 84 IF_IN2 82 IF_IN1 83 IF_VG 86 IFSS2 85 IFSS1 80 VREFIF 79 VSS(IF) 78 VDD(OSC) 77 OSC_OUT 76 OSC_IN 75 VSS(OSC) 74 GAPREG 73 FEBREG 72 CONREG 71 VSSD3 70 VDDD3 69 VSSD5 68 VSSD2 67 VDDD2 66 VSSD1 65 VDDD1(MEM) 64 VSSD6 63 DSP_IO8 62 DSP_IO7 61 DSP_IO6 60 DSP_IO5 59 DSP_IO4 58 VSS(I/O4) 57 DSP_IO3 56 DSP_IO2 55 DSP_IO1 54 DSP_IO0 53 RDS_DATA1_DAVN1 52 RDS_CLK1_DAVN2 51 RDS_DATA2 IIS_OUT2 31 IIS_OUT3 32 VSS(I/O2) 33 VDD(I/O2) 34 IFP_IIS_OUT5 35 IIS_BCK 36 IIS_WS 37 IFP_IIS_IN1 38 IFP_IIS_I2O6 39 IFP_IIS_I3O4 40 IFP_IIS_OUT1 41 IFP_IIS_OUT2 42 IFP_IIS_OUT3 43 VDD(I/O3) 44 VSS(I/O3) 45 IFP_IIS_BCK 46 IFP_IIS_WS 47 SCL 48 SDA 49 RDS_CLK2 50 VDACP 10 RFV 11 LFV 12 A0 13 SPDIF1 14 SPDIF2 15 RESET 16 TSCAN 17 SHTCB 18 RTCB 19 EXT_IIS_WS1 20 EXT_IIS_BCK1 21 EXT_IIS_IO1 22 EXT_IIS_WS2 23 EXT_IIS_BCK2 24 EXT_IIS_IO2 25 VSS(I/O1) 26 IIS_IN1 27 IIS_IN2 28 IIS_IN3 29 IIS_OUT1 30 SAA7724H MGW193 Fig.4 Pin configuration. 2003 Nov 18 16 Philips Semiconductors Preliminary specification Car radio digital signal processor 6 6.1 FUNCTIONAL DESCRIPTION Voltage regulator SAA7724H A voltage regulator (see Fig.5) controls all 2.5 V supplies of the chip (see Fig.6). The input supply voltage is 3.3 V. An external PMOS power transistor (e.g. BSH207) is used to handle power. The regulated 2.5 V supply is derived from a band gap voltage, which is AC-decoupled by an external capacitor. handbook, full pagewidth on-chip off-chip VDD(REG) GAPREG BSH207 1 74 BAND GAP 72 73 R1 Vgap R2 CONREG FEBREG external PMOS 1 F external decoupling VSS MGW195 Fig.5 Voltage regulator schematic diagram. 2003 Nov 18 17 Philips Semiconductors Preliminary specification Car radio digital signal processor SAA7724H handbook, full pagewidth on-chip off-chip VDD(REG) VDD(I/O3) VDD(I/O2) GAPREG 100 nF BSH207 1 H 1 44 34 74 72 73 70 67 65 78 81 90 9 CONREG FEBREG VDDD3 VDDD2 VDDD1(MEM) VDD(OSC) VDD(IF) VDDA1 VDDA2 10 F 1 F 2.5 V 3.3 V 1 H 1 F 1 H VSS MGW196 Fig.6 Voltage regulator connection diagram. 2003 Nov 18 18 Philips Semiconductors Preliminary specification Car radio digital signal processor 6.2 Audio analog front-end SAA7724H The analog front-end consists of two identical 3rd-order sigma delta stereo ADCs (ADC1 and ADC2) with several input control blocks for handling common mode signals and acting as input selector (see Fig.7). handbook, full pagewidth SAA7724H AAD refc1 aic1[1:0] intref1 = 0 AIN1_L AIN2_L 87 94 00 01 10 11 0 0 1 1 89 96 00 01 10 11 ADIFF_R (P/N) ADIFF_L (P/N) VREFAD 99, 100 97, 98 93 INT REF AIN1_REF AIN2_REF 88 95 0 0 1 1 00 01 10 11 intref2 = 0 MONO2_P MONO2_N MONO1_P MONO1_N 4 5 2 3 CMRR 00 01 10 IFSS2 IFSS1 86 85 11 AUXAD_1 AUXAD_2 AUXO2 CLKAUX AUXO1 CMRR 1 0 mixc aic3[1:0] located in SDAC volmix[1:0] MIX aic2[1:0] refc2 volmix[5:2] 0 1 1 AUDIOAD_2 STEREO LEFT2 RIGHT2 ADF1_2 00 01 10 11 0 s2 2 2 0 1 1 AUDIOAD_1 STEREO LEFT1 RIGHT1 ADF1_1 0 s1 AIN1_R AIN2_R CLKADC1 CLKADC2 MGW197 Fig.7 Analog front-end switch diagram. 2003 Nov 18 19 Philips Semiconductors Preliminary specification Car radio digital signal processor The inputs ADIFF, AIN1, AIN2, MONO1 and MONO2 can be selected with the audio input controls (aic1 and aic2). The ground reference (REF1 and REF2) can be selected (refc1 and refc2) to enable the handling of common mode signals for AIN1 and AIN2. The switches s1 and s2 are needed for handling fully differential inputs at the ADIFF pins. The MONO1 and MONO2 inputs have their own CMRR input stage and can be redirected to ADC1 and/or ADC2 via the audio input control (aic1 and aic2). In this event, the ground reference should be switched to internal (intref = 1). It is also possible to pass MONO1/MONO2 to Table 4 SAA7724H the AUXAD (controlled by aic3) or directly mix the same MONO input with four DAC output channels, incorporating volume control. 6.2.1 SELECTOR DIAGRAM Three bits are available to make it possible to redirect the inputs with their corresponding reference to the required AUDIOAD (see Tables 4 and 5). The input control for the AUXAD_2 is given in Table 6. The input selection of the mixer is given in Table 7. Reference connection for AUDIOAD_1 and AUDIOAD_2 I2C-BUS BIT REFERENCE CONNECTION FOR AUDIOAD_1 and AUDIOAD_2 REF1 REF2 VREFAD differential refc1, refc2 0 1 - - Table 5 intref1, intref2 0 0 1 - s1, s2 0 0 0 1 Input connection for AUDIOAD_1 and AUDIOAD_2 I2C-BUS BIT PREFERRED REFERENCE INPUT CONNECTION FOR AUDIOAD_1 and AUDIOAD_2 AIN1 AIN2 ADIFF MONO1 and MONO2 aic1[1], aic2[1] 0 0 1 1 Table 6 aic1[0], aic2[0] 0 1 0 1 REF1 REF2 differential VREFAD Input connection for AUXAD_2 I2C-BUS BIT INPUT CONNECTION FOR AUXAD_2 aic3[1] 0 0 1 1 Table 7 aic3[0] 0 1 0 1 MONO1 MONO2 not connected IFSS2 Input connection for the MIXER INPUT CONNECTION FOR THE MIXER I2C-BUS BIT mixc 0 1 MONO1 MONO2 2003 Nov 18 20 Philips Semiconductors Preliminary specification Car radio digital signal processor 6.2.2 REALIZATION OF THE COMMON MODE INPUT WITH AIN SAA7724H The actual input can be selected with the audio input control (bits aic1[1:0] and aic2[1:0]). In Fig.8 the AIN1 input is selected. In this situation both signal lines going to the ADC will contain the common mode signal. The ADC itself will suppress this common mode signal with a high rejection ratio. The input pins AIN1_L and AIN1_R are connected directly to the source. The 1 M resistor provides the DC biasing of OA3 and OA4. The impedance level, in combination with the parasitic capacitance at input pin AIN_L or AIN_R, greatly determines the achievable common rejection ratio. A high CMRR can be created by the use of REF1 and REF2. These pins can be connected to the positive input of the second operational amplifier in the signal path with bits intref1, intref2, refc1 and refc2 (see Fig.8). The signal (of which a high CMRR is required) has a signal and a common signal as input. The common signal is connected to pin REF1 and/or REF2 and can be selected with bits refc1 and/or refc2. handbook, full pagewidth 10 k 10 k 11 10 01 CD player left AIN1_L 87 00 OA1 1 0 60 k ground CD player cable 1 M VREFAD 93 AIN1_REF 88 1 0 60 k MIDREF 0 1 1 0 s1 = 0 intref1 = 0 refc1 = 0 aic1[1:0] = 00 to AD 10 k OA3 CD player left AIN1_R 89 00 01 10 11 10 k 10 k to AD 10 k OA4 OA2 MGW198 off-chip on-chip Fig.8 Example of the use of common mode analog input AIN1. 2003 Nov 18 21 Philips Semiconductors Preliminary specification Car radio digital signal processor 6.2.3 REALIZATION OF THE DIFFERENTIAL ADIFF INPUT SAA7724H The ADIFF input is fully differential. The signal that is connected to this input should be a symmetrical signal. Besides bits aic1[1:0] and aic2[1:0], to select the ADIFF_L and ADIFF_R input, the switches s1 and s2 are needed to put the ADIFF_L and ADIFF_R inputs in true differential mode (see Fig.9). handbook, full pagewidth 10 k ADIFF_LN 98 11 ADIFF_LP 97 10 01 00 OA1 1 0 aic1[1:0] = 10 1 AIN1_REF 88 VREFAD 93 MIDREF 0 1 0 1 0 s1 = 1 intref1 = 0 refc1 = 0 10 k to AD 10 k OA3 00 01 ADIFF_RP 99 10 11 ADIFF_RN 100 10 k 10 k to AD 10 k OA4 OA2 MGW199 off-chip on-chip Fig.9 Example of the use of differential analog input ADIFF_L and ADIFF_R. 2003 Nov 18 22 Philips Semiconductors Preliminary specification Car radio digital signal processor 6.2.4 REALIZATION OF THE AUXILIARY INPUT WITH VOLUME CONTROL SAA7724H 0 to -22.5 dB in 1.5 dB steps. The attenuated signal can be added to the left and/or right front and/or left and/or right rear DAC channels. When the mix signal is added to the output, the gain of the output is automatically adjusted to prevent clipping at high input levels. The inverse output signal of both CMRR circuits can also be switched to the AUDIOAD_1 and/or AUDIOAD_2 and/or AUXAD_2. A common mode input with volume control for mixing with four DAC outputs is provided (see Fig.10). The inputs consist of pins MONO1_P and MONO2_P, both accompanied with their ground signals (pins MONO1_N and MONO2_N). After selection of MONO1 or MONO2, with bit mixc, the volume can be changed from handbook, full pagewidth off-chip on-chip AUDIOAD_1 or AUDIOAD_2 or AUXAD_2 AUDIOAD_1 or AUDIOAD_2 or AUXAD_2 volmix[5:2] R = 60 k R MONO1_P MONO1_N 2 3 R R R 0 R 1 MONO2_P MONO2_N 4 5 R R R mixc VREFAD 93 Midref volmix[1:0] rlm = 1 rrm = 1 flm = 1 frm = 1 volmix[5:2] volmix[5:2] volmix[5:2] MGW200 Fig.10 MONO input circuit. Table 8 Mix volume control I2C-BUS BIT OUTPUT MIX GAIN (dB) I2C-BUS BIT OUTPUT MIX GAIN (dB) volmix[5:0] (hex) 17 0 -1.5 -3.0 -4.5 -6.0 -7.5 -9.0 -10.5 -12.0 -13.5 23 The bits volmix[5:2] are binary weighted organized and used for setting the mixer gain from 0 to -18 dB. The selection bits are connected to the mixer in the QSDAC. 13 0F 0E 0D 0C 00 -15.0 -16.5 -18.0 -19.5 -21.0 -22.5 MUTE volmix[5:0] (hex) 3F 3B 37 33 2F 2B 27 23 1F 1B 2003 Nov 18 Philips Semiconductors Preliminary specification Car radio digital signal processor The bits volmix[1:0] are also binary weighted organized and connected to the analog front-end. The MIX signal can be added to all outputs independant of each other. Table 9 Mix output control; note 1 DAC OUTPUT FL off on X X X X X X FR X X off on X X X X RL X X X X off on X X RR X X X X X X off on handbook, halfpage SAA7724H 6.2.5.2 Reference pin VREFAD I2C-BUS BIT BIT flm frm rlm rrm VALUE 0 1 0 1 0 1 0 1 Note 1. X = not controlled by this bit. 6.2.5 The midref voltage of the ADCs is filtered via this pin. This midref voltage is used for half supply reference of the ADCs. External capacitors (connected to groundplane) prevent crosstalk between the switched capacitor DACs of the internal ADCs and buffers and improves the power supply rejection ratio of all components (see Fig.11). V VADCP - V VADCN V VREFAD = --------------------------------------------2 VADCP VREFAD VADCN MGW201 SUPPLIES AND REFERENCES 6.2.5.1 Reference pins VADCN and VADCP Fig.11 VREFAD reference circuit. These pins are used as a negative and positive reference for the AUDIOAD_1 and AUDIOAD_2 and the level ADC. These references needs to be "clean". 6.2.5.3 Analog supply inputs The analog input circuit has separate power supply (VDDA1) connections to allow maximum filtering. The input stage of every operational amplifier within the analog front-end is supplied by a 3.3 V supply voltage so as to enable a rail-to-rail input signal. 2003 Nov 18 24 Philips Semiconductors Preliminary specification Car radio digital signal processor 6.3 AD decimation paths (DAD) SAA7724H The DAD block consists of a Level Decimation Filter (LDF) which handles the AUX decimation and an Audio Decimation Filter (ADF) which handles the AUDIO decimation. The AD decimation paths for both the level and audio are achieved in the DAD block; (see Fig.12). There are two DAD blocks implemented for the SAA7724H. handbook, full pagewidth LDF aux(n)_sel_lev_voice 1-BIT CODE FILTER ADF 1-BIT CODE FILTER CEAD INTERFACE CEAD BLOCK CONTROLLER MGW202 ch(n)_dc_offset (n) is 1 or 2. Fig.12 DAD block diagram. 6.3.1 LDF AND AUX DECIMATION PATH The input signal has a sample frequency of 128 x fs and comes from a 1st-order ADC. The first part of the decimation is done using a CIC filter. For the AUX decimating filter a 2nd-order CIC filter is implemented. A branch is also available from this filter for a signal having a sample frequency of 8 x fs. This signal also passes a built-in high-pass filter section to make it adequate for level IAC detection purposes. With a sampling frequency of 8 x 42.1875 kHz the -3 dB point of this filter is at approximately 60 kHz. The CIC filter decimates the sample frequency by 64. The sin x new output sample rate is 2 x fs. The ---------- roll-off of the x CIC filter needs to be compensated for, therefore, a roll-off compensation filter is utilized. The last stage of the AUX decimation filter is the realization of the appropriate bandwidth characteristic. The bits aux1_sel_lev_voice and aux2_sel_lev_voice selects between the level characteristic and the audio characteristic for voice input. The transfer characteristics, level and audio, of the AUX decimation filter are illustrated in Fig.13. It should be noted that the figure corresponds with a 38 kHz sample rate. For the SAA7724H a 42.1875 kHz sample rate is used, the horizontal values need to be scaled with a factor of 42.1875 -------------------38 Remark: The absolute gain or attenuation of the graphs in Fig.13 has no meaning. The relative levels however have. When bit aux1_sel_lev_voice or aux2_sel_lev_voice is logic 1, the coefficient for audio processing is active. When bit aux1_sel_lev_voice or aux2_sel_lev_voice is logic 0, the coefficient for level processing is selected. 2003 Nov 18 25 Philips Semiconductors Preliminary specification Car radio digital signal processor SAA7724H handbook, full pagewidth G 80 40 MGW203 (dB) audio characteristic 0 -40 -80 80 40 0 -40 -80 0 10000 20000 30000 40000 50000 60000 70000 f (Hz) 80000 level characteristic Fig.13 AUX decimation path transfer characteristics. 6.3.2 ADF AND AUDIO DECIMATION PATH 6.4 Digital audio input/output The input signal has a sample frequency of 128 x fs and comes from a third order sigma delta ADC. The first step in the decimation process is done by the 1-bit code (CIC) filter. This CIC filter decimates the input sample rate by a factor of 16, which results in a sample rate of 8 x fs. After the 1-bit code filter, sample rehashing is necessary prior to entering the CEAD block. The CEAD block decimates the audio samples further by a factor of 8, resulting in a sample rate of 1 x fs. The overall gain in the pass-band of the decimation filter, including the CIC filter and CEAD block becomes 4.85 dB. A nominal input level of -7.36 dB coming from the ADC will result in a -2.5 dB level after decimation. The DC filter in the CEAD block is controlled by I2C-bus bit ch1_dc_offset or ch2_dc_offset; see Table 27. There is no power-on reset circuitry implemented. This means that after power-up, all filters will go through a fast transient phase before they reach their steady state behaviour. This section describes the external I2S-bus input/output ports, the EPICS host I2S-bus port and the SPDIF inputs. 6.4.1 GENERAL There are two external I2S-bus input/output ports available on the circuit, and three host I2S-bus ports. The I2S-bus inputs and host I2S-bus outputs are capable of handling Philips I2S-bus, and LSB-justified formats of 16, 18, 20 and 24-bit word sizes. The external I2S-bus output ports only support Philips I2S-bus. For the general waveforms of the five possible formats see Fig.14. More general information on the Philips I2S-bus format is given in Chapter 12. Note: When the applied word length is smaller than 24 bits, the LSB bits will get (internally) a zero value. When the applied word length exceeds 24 bits, the LSBs are skipped. 2003 Nov 18 26 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 2003 Nov 18 27 DATA MSB B2 B3 B4 B17 LSB LSB-JUSTIFIED FORMAT 18 BITS MSB B2 B3 B4 B17 LSB WS LEFT 20 BCK 19 18 17 16 15 2 1 RIGHT 20 19 18 17 16 15 2 1 DATA MSB B2 B3 B4 B5 B6 B19 LSB LSB-JUSTIFIED FORMAT 20 BITS MSB B2 B3 B4 B5 B6 B19 LSB WS 24 BCK 23 22 21 LEFT 20 19 18 17 16 15 2 1 24 23 22 21 RIGHT 20 19 18 17 16 15 2 1 Philips Semiconductors handbook, full pagewidth Car radio digital signal processor WS 1 BCK 2 3 LEFT >=8 1 2 3 RIGHT >=8 DATA MSB B2 MSB B2 MSB INPUT FORMAT I2S-BUS WS LEFT 16 15 2 1 RIGHT 16 15 2 1 BCK DATA MSB B2 B15 LSB LSB-JUSTIFIED FORMAT 16 BITS MSB B2 B15 LSB WS LEFT 18 17 16 15 2 1 RIGHT 18 17 16 15 2 1 BCK Preliminary specification SAA7724H DATA MSB B2 B3 B4 B5 B6 B7 B8 B9 B10 B23 LSB LSB-JUSTIFIED FORMAT 24 BITS MSB B2 B3 B4 B5 B6 B7 B8 B9 B10 B23 LSB MGW204 Fig.14 Waveforms of standardized digital input and output signals. Philips Semiconductors Preliminary specification Car radio digital signal processor 6.4.2 EXTERNAL I2S-BUS INPUT/OUTPUT PORTS SAA7724H 6.4.2.1 SRC audio signal flows An I2S-bus interface is provided for communication with external digital sources. It is a serial 3-line bus, having one line for data, one line for clock and one line for the word select. For external digital sources the circuit acts as a slave, so the external source is master and supplies the Bit Clock (BCK) and Word Select (WS). Figure 15 shows the external I2S-bus receiver and controls. Table 10 defines the possible modes that must be set for the I2S-bus inputs. An extra function that is provided is that the EXT_IIS ports can also be set, as an output, from the Sample Rate Converters (SRC). In this event only the Philips I2S-bus format is supported. Figure 16 shows the audio signal flow possibilities for the sample rate converters SRC1 and SRC2. The inputs to the SRCs can be either an external source, or an internal signal from the AUDIO_EPICS. The outputs from the SRCs can either work as a slave output from an externally connected bus to an external I2S-bus Port 1 or 2, or it can convert the internal SAA7724H sample rate directly to the AUDIO_EPICS and the switchboard in the IFP. If conversion to an external sample rate is selected, the audio signals to the IFPs switchboard and the AUDIO_EPICS are muted, while their sample rates are maintained at the internal SAA7724H sample rate. All I/O possibilities of the SRCs can be set by eight independent I2C-bus bits. Some selections are conflicting or make no sense. In order to keep as much flexibility as possible there is no detection of conflicting settings, however the circuitry is guaranteed not to cause a hang-up situation. All audio paths to and from the SRCs are 24 bits wide. Inside the switchboard from the IFP, the audio is always truncated to 16 bits. handbook, halfpage EXT_IIS_BCK(n) EXT_IIS_WS(n) EXT_IIS_DATA(n) I2S-BUS RECEIVER to SRC 3 ext_host_io_format(n)[2:0] (n) is 1 or 2. MGW205 Fig.15 External I2S-bus input and controls. Table 10 External I2S-bus input formats ext_host_io_format1 [2:0] ext_host_io_format2 [2:0] 0 1 1 1 1 Note 1. X = don't care. X(1) 0 0 1 1 X(1) 0 1 0 1 FORMAT Philips I2S-bus LSB -justified 16 bits LSB-justified 18 bits LSB-justified 20 bits LSB-justified 24 bits 2003 Nov 18 28 Philips Semiconductors Preliminary specification Car radio digital signal processor SAA7724H handbook, full pagewidth EXT_IIS_IO1 22 src1_ext_sel_out EXT_IIS_IO2 25 OUT1 SRC1 SPDIF1 EXT_IIS_IO1 14 22 sel_SPDIF1_IIS1 src1_int_ext_in src1_int_ext_out IFP_SWB sel_SPDIF2_IIS2 25 15 src2_int_ext_in SRC2 IN2 OUT2 src2_int_ext_out IN2 AUDIO_EPICS IN1 OUT1 IN1 EXT_IIS_IO2 SPDIF2 OUT2 src2_ext_sel_out 22 EXT_IIS_IO1 25 EXT_IIS_IO2 MGW206 Fig.16 SRC audio signal flows. 6.4.2.2 Sampling frequency range limitations 6.4.3 EXTERNAL SPDIF INPUT The external I2S-bus inputs are guaranteed for a continuous 8 kHz to 48 kHz sampling frequency range. A signal can be applied to one or both of the SPDIF inputs that conforms to the IEC 60958 specification. The SPDIF receivers support SPDIF audio data up to 24 bits. Some channel status bits are also decoded and made available to the system. There is no support for user data decoding, nor availability of the validity bit. Figure 17 shows the SPDIF receiver and its outputs. The exact meaning of the output bits is given in Table 30. The SPDIF inputs do not have any specific control signals. 6.4.2.3 BCK and WS limitations The rate at which the I2S-bus receivers decode data available to the system, depends on the WS frequency. For normal application only 1 x fs is used. The WS duty cycle does not need to be 50 % for any of the applied formats. The BCK is limited to a maximum frequency of 256 x fs. The lower limit is defined by the number of bits that are required to be sent. For LSB-justified formats the number of BCKs must be at least the number of bits that is selected per channel. 2003 Nov 18 29 Philips Semiconductors Preliminary specification Car radio digital signal processor SAA7724H handbook, full pagewidth off chip on chip Audio to SRC 14 or 15 LOCK SPDIF RECEIVER 2 2 SPDIF(n)_content SPDIF(n)_emphasis SPDIF(n)_fs SPDIF(n)_accuracy MGW207 SPDIF(n) channel status bits (n) is 1 or 2. Fig.17 SPDIF receiver and its outputs. 6.4.3.1 SPDIF input application diagram Figure 18 shows the general set-up for an SPDIF input for consumer applications. Figure 19 shows an example of how to prevent crosstalk from two adjacent SPDIF inputs, due to the parasitic capacitance from lead finger and bond wires. Therefore extra capacitors are added near the pins. handbook, halfpage 100 nF SPDIF input 100 pF 75 MGW208 Fig.18 General SPDIF input application. handbook, full pagewidth 100 nF 75 SPDIF1 14 100 pF 100 pF 100 nF 75 SPDIF2 15 100 pF leadfinger/bondwire capacitor 100 pF MGW209 Fig.19 Example of crosstalk prevention for SPDIF inputs. 2003 Nov 18 30 Philips Semiconductors Preliminary specification Car radio digital signal processor 6.4.3.2 Sampling frequency range limitations 6.4.3.4 Lock indicator SAA7724H The external SPDIF input sample rates are 32, 44.1 and 48 kHz. The accuracies of the supported standardized sampling frequencies at the SPDIF inputs meets the requirements of Level II accuracy as specified in IEC 60958, being 0.1 %. 6.4.3.3 Channel status bits The SPDIF receiver has a LOCK pin. The polarity is described in the I2C-bus map. When the system is not in lock, the audio data will be muted (being zero data values). In the event that the SPDIF signal is missing or very distorted, the timing information to the SRC from the SPDIF receiver will not be good or may even disappear. This will cause the SRC to get unlocked. Locking will occur within 5 ms after reset, or 5 ms after the availability of a proper SPDIF signal at the input. The lock indicator is available at one of the EPICS status flags, and thus also readable via the I2C-bus. The exact location is given in Table 25. 6.4.4 EPICS HOST I2S-BUS PORT The channel status bits given in Table 11 are available from the SPDIF receiver. The information is taken from the left audio channel. The channel status bits are available in the I2C-bus map, where the exact meaning of the bits can also be found; see Table 30. Table 11 SPDIF channel status bits CHANNEL STATUS BIT NUMBER 1 3 25 and 24 29 and 28 CONSUMER FORMAT MEANING data/audio mode pre-emphasis sampling frequency clock accuracy Because this is a master I/O port the EPICS host I2S-bus generates its own WS and BCK. There is one WS and BCK for all three output and input data paths. The definition of how the WS and BCK are generated can be found in Chapter 11. Figure 20 shows the EPICS host I2S-bus I/O and controls. The EPICS host I2S-bus has its own setting for selecting the formats; see Table 12. The setting of the EPICS rate should be taken into account, for setting the desired host I2S-bus format. The LSB-justified formats 18, 20 and 24 bits are not available when the EPICS is running at a rate other than 1 x fs. handbook, halfpage on chip off chip 27 28 to EPICS I2S-BUS TRANSCEIVER 29 37 36 30 from EPICS 31 32 IIS_IN1 IIS_IN2 IIS_IN3 IIS_WS IIS_BCK IIS_OUT1 IIS_OUT2 IIS_OUT3 3 MGW210 host_io_format[2:0] Fig.20 EPICS host I2S-bus with controls. 2003 Nov 18 31 Philips Semiconductors Preliminary specification Car radio digital signal processor Table 12 External EPICS host I2S-bus formats host_io_format2 0 1 1 1 1 Notes 1. X = don't care. 2. Not supported for EPICS rates other than 1 x fs. 6.5 Sample rate converter host_io_format1 X(1) 0 0 1 1 host_io_format0 X(1) 0 1 0 1 Philips I2S-bus LSB-justified 16 bits LSB-justified 18 bits; note 2 LSB-justified 20 bits; note 2 LSB-justified 24 bits; note 2 FORMAT SAA7724H There are two Sample Rate Converters (SRCs) available in the SAA7724H. The input of each SRC can be an external source or internal audio from the AUDIO_EPICS. The outputs are fed to the IFPs switchboard and the AUDIO_EPICS or to an external I2S-bus port; see Section 6.4.2.1. Both SRCs meet the requirements given in Table 13. Table 13 SRC specification SRC CHARACTERISTIC Input sample rate Output sample rate THD + N Overall gain Maximum ripple amplitude (0 to 0.45 fs) Stop band suppression (0.55 fs to 1 fs) Output word width Lock time Audio during unlocked state SPECIFICATION continuously 8 kHz to 48 kHz; absolute accuracy 0.1 % continuously 8 kHz to 48 kHz 96 dB at 1 kHz 0 dB 0.1 dB 98 dB 24 bits 45 ms muted (zero data) 2003 Nov 18 32 Philips Semiconductors Preliminary specification Car radio digital signal processor 6.6 IF_AD SAA7724H The IF_AD performs the analog-to-digital conversion of the FM/AM-IF signal. It generates 10-bit data. For dual radio two IF_AD convertors are incorporated (see Fig.21). handbook, full pagewidth off chip IF_IN1 on chip 82 IF_IN IF_VG VDD(IF) VREFIF VSS(IF) IF_AD_OUT DITHER_GAIN DIT_IN IF_AD1 IF_AD_CLK IF_AD_OUT1 dith_gain_1 DIT_IN1 IF_IN2 IF_VG VDD(IF) VREFIF VSS(IF) 84 83 81 80 79 IF_IN IF_VG VDD(IF) VREFIF VSS(IF) IF_AD_OUT DITHER_GAIN DIT_IN IF_AD2 IF_AD_CLK IF_AD_OUT2 dith_gain_2 DIT_IN2 IF_AD_CLK MGW211 Fig.21 IF_AD dual block diagram. 6.6.1 IF_AD SINGLE BLOCK DIAGRAM The IF_AD block diagram shows the analog part. It consists of a buffer and dither block and a two-step ADC. 2003 Nov 18 33 Philips Semiconductors Preliminary specification Car radio digital signal processor 6.6.2 IF_AD DETAILED FUNCTIONAL DESCRIPTION SAA7724H The IF_AD consists of several blocks. These blocks are the ADC itself preceded by a buffer and dither differential summing point. The dither is made with a dither DAC (DIT_DAC) combined with gain variation in G_DAC. The interface to the IFP is fed via the registers shown in Fig.22. handbook, full pagewidth off-chip on-chip IF_IN(n) 82, 84 BUFFER AND DITHER R1 234 10 k 10 k Rdit 10 k 10 k REGISTER DIT_DAC R1 234 234 234 Ig 4-BIT G_DAC R2 DIT_IN(n) bd0 VDD(IF) 81 bd7 dith_gain_(n) 0 3 IF_VG 83 VSS(IF) 79 IF_AD_CLK IF_AD_OUT(n) b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 TWO STEP ADC REGISTER MGW212 (n) is 1 or 2. Fig.22 IF_AD single block diagram; analog part. 2003 Nov 18 34 Philips Semiconductors Preliminary specification Car radio digital signal processor 6.6.2.1 ADC SAA7724H The I2C-bus registers, some of which are mapped onto XMEM address space, are shown in Chapter 11.5, Tables 21 to 23. 6.7.1 AUDIO_EPICS START-UP The ADC is based on the two-step principle. 6.6.2.2 Buffer The buffer is configured as a single-ended to differential convertor. 6.6.2.3 Dithering The AUDIO_EPICS will start running the code after the reset procedure has been completed. This code will start running from address 0 by default, if not reprogrammed by the user before releasing the pc_reset bit. 6.7.2 AUDIO_EPICS MEMORY OVERVIEW Dither can be applied via the dither DACs DIT_DAC and G_DAC. The input voltage range and the dither level are both proportional to the supply voltage. DIT_DAC is driven by the IFP. The source is an 8-bit word having 9 values representing -4 (00000000) to +4 (11111111). The total number of 1s in the 8-bit input word represent the code that the DIT_DAC is using. The maximum negative output voltage is represented by all 0s on the 8-bit word, and the maximum positive output voltage is represented by all 1s on the 8-bit word. A nominal value of 0 V, which is half way between the maximum positive output voltage and the maximum negative output voltage at the output of the DIT_DAC, is represented by setting any four of the eight bits to logic 1 and the other four bits to logic 0. To adjust the G_DAC dither to the required level, the multiplying current of the DIT_DAC can be changed with a binary weighted current DAC. The reference current is derived from an internal reference source which is proportional to VDD(IF). As a reference point for the equivalent input dither level, at nominal supply voltage, the following equation is used: Vditppeq = 3.7 x ditgain (mV). 6.7 AUDIO_EPICS specific information The memory sizes for the AUDIO_EPICS are given in Table 14. Table 14 AUDIO_EPICS memory list MEMORY TYPE DSP program memory DSP X memory DSP Y memory 6.8 SDAC output path PRODUCT VERSION ROM: 5120 words RAM: 3584 words RAM: 1024 words There are two SDACs implemented in the SAA7724H, one for the front channels (SDAC_F) and one for the rear channels (SDAC_R). The total digital-to-analog conversion path, consists of the following components (see Fig.23): 1. An upsample filter 2. A 3rd-order noise shaper 3. A compensation and dynamic element matching (CoDEM) scrambler 4. The multibit SDAC with current compensation. All circuitry including the analog part use a 128 x fs clock. This chapter contains specific additional information, over the EPICS7A programmers guide, specifically for the SAA7724H. handbook, full pagewidth UPSAMPLE FILTER NOISE SHAPER CODEM SA TIO N MULTIBIT DAC CO M N PE 1f s 128f s 128f s DA C 1 0 1 0 MGW213 Fig.23 SDAC path diagram. 2003 Nov 18 35 Philips Semiconductors Preliminary specification Car radio digital signal processor 6.8.1 DAC UPSAMPLING FILTER SAA7724H Element Matching (DEM) algorithm. Thirdly, by using this code, matching errors in the analog part of the SDAC have less influence on the performance. The CoDEM also generates a compensation vector for the compensation part of the DAC. 6.8.4 MULTI-BIT SDAC The upsampling filter interpolates a 24-bit stereo signal from 1 x fs to 8 x fs by cascading two half-band FIR filters. Interpolating to 128 x fs is done by a sample-and-hold filter. 6.8.2 DAC NOISE SHAPER A 3rd-order noise shaper is used to quantize the 24-bit input signal that is fed from the upsampling filter into a 5-bit output signal. The generated quantization noise is shaped outside the audio band. 6.8.3 DAC CODEM SCRAMBLER The SDAC is a multi-bit DAC based upon 31 switched resistors. The 31 resistors form a network which can create 32 DC output levels. The exact analog output level is the sum of the DC level and the superimposed bitstream signal. In the application a simple low-pass filter (one capacitor) must be used at the outputs of the SDAC. The overall DAC filters spectral plot is illustrated in Fig.24. As an example a left filtered output is selected, which also has a 3.3 nF output filtering capacitor connected. The CoDEM scrambler has three different functions. Firstly it converts the 5-bit signal from the noise shaper into a thermometer code. Secondly, after conversion, the thermometer code is scrambled by means of a Dynamic handbook, full pagewidth 0 MGW214 (dB) -25 -50 left_filtered -75 -100 -125 -150 -175 -200 20 filter 100 1k 10 k 100 k f (Hz) 1M 3M Fig.24 DAC filters spectral diagram. 6.8.5 ANALOG SUMMER FUNCTION The SDAC is featured with the analog summing of signals from the ADCs; for details of this function see Chapter 6.2. 2003 Nov 18 36 Philips Semiconductors Preliminary specification Car radio digital signal processor 6.8.6 SDAC APPLICATION DIAGRAM SAA7724H An example of the circuitry surrounding the DAC outputs is illustrated in Fig.25. handbook, full pagewidth LFV 12 47 F 3.3 nF RFV 11 47 F 3.3 nF SAA7724H LRV 7 3.3 nF 47 F RRV 6 8 VDACN 100 nF 9 VDDA2 100 F 100 nF 10 VDACP 47 F 47 F 3.3 nF MGW215 Fig.25 DAC outputs application diagram. 6.9 Reset block functional overview 6.10 6.10.1 Clock circuit and oscillator CIRCUIT DESCRIPTION The reset block uses the asynchronous reset signal from pin RESET to generate synchronous reset signals. The generated reset signals are described in the following sections. 6.9.1 ASYNCHRONOUS RESET The asynchronous reset signal from pin RESET asynchronously disables the SDA pin (set HIGH) whenever the reset signal is active. Furthermore, all 3-state and bidirectional outputs are kept 3-state asynchronously as long as pin RESET is kept LOW, and the internal reset sequence is still ongoing. It requires approximately 1100 OSCIN_CLK cycles to complete the reset sequence after the RESET pin has gone HIGH. After reset the state of the SAA7724H will be as specified in Table 2. The chip has an on-board crystal clock oscillator with amplitude control based on a Pierce oscillator; see Fig.26. The oscillator is implemented as an inverter with capacitive coupling at the input. When the transconductance of this inverter is sufficiently high, the feedback loop becomes unstable and the circuit starts to oscillate. This oscillation grows until its amplitude has reached a specific value which is detected by the AGC. In this way, clipping of the output voltage against the supply voltages is prevented. The AGC also ensures that the transconductance builds up very rapidly after power-on and stays sufficiently high during oscillation. The sinusoidal output is converted into a CMOS compatible clock by the comparator. 37 2003 Nov 18 Philips Semiconductors Preliminary specification Car radio digital signal processor SAA7724H handbook, full pagewidth AGC Gm CLKOUT on-chip Rbias XTAL1 76 OSC_IN 100 k XTAL2 77 OSC_OUT 78 VDD(OSC) 75 VSS(OSC) off-chip L1 2.2 H Cx1 15 pF Cx2 15 pF C3 10 nF MGW224 Fig.26 Schematic diagram of the crystal oscillator circuit. 6.10.2 EXTERNAL CLOCK INPUT MODE 6.10.4 APPLICATION GUIDELINES It is possible to use the oscillator as a clock input. In external clock input mode, an external clock signal is input on pin OSC_IN and this clock signal is transferred to the output via an extra output inverter stage. In this mode, the quartz crystal, L1, Cx2 and C3 may be removed, but this is not obligatory. 6.10.3 CRYSTAL OSCILLATOR SUPPLY For correct operation of the oscillator, two load capacitors (Cx1 and Cx2) need to be added externally to the chip. This configuration is adequate for the required crystal frequency of 43.2 MHz. The external components shown in Fig.26 are specified in Table 15. The use of other values may prevent the oscillator from start-up. A quartz crystal oscillator is used to generate the clock signal CLKOUT. In the case of an overtone oscillator, the ground harmonic is filtered out by L1 and Cx2. A quartz crystal should be used with a series resonance resistance of less than 80 and a capacitance of less than 7 pF. The crystal should be manufactured for a load capacitance of 10 pF. The value of C3 is not critical as long as it is not much lower than 10 nF (10 % is accurate enough). There is no theoretical upper limit. The power supply connections to the oscillator are separated from the other supply lines to minimize feedback from on-chip ground bounce to the oscillator circuit. Noise on the power supply affects the AGC operation therefore the power supply should be decoupled. The VSS(OSC) pin is used as ground supply and the VDD(OSC) as the positive supply. Table 15 External components specification for the crystal oscillator COMPONENT Cx1 Cx2 C3 L1 MIN. 13.5 13.5 9 1.98 TYP. 15.0 15.0 10 2.2 MAX. 16.5 16.5 - 2.42 UNIT pF pF nF H 2003 Nov 18 38 Philips Semiconductors Preliminary specification Car radio digital signal processor 6.11 PLL circuits SAA7724H The RDS demodulator regenerates the raw RDS bitstream (bit rate = 1187.5 Hz) from the modulated RDS signal in two steps. The first step is the demodulation of the double sideband suppressed carrier signal around 57 kHz into a baseband signal, by carrier extraction and down-mixing. The second step is the Binary Phase Shift Key (BPSK) demodulation of the biphase coded baseband signal, by clock extraction and correlation. The RDS/RBDS decoder provides block synchronization, error detection, error correction, complex flywheel function and programmable block data output. Newly processed RDS/RBDS block information is signalled to the main microcontroller as `new data available' using the DAVN output. The block data itself and the corresponding status information can be read out via an I2C-bus request. The RDS/RBDS decoder contains the following major functions needed for RDS/RBDS data processing: * RDS and RBDS block detection * Error detection and correction * Fast block synchronization * Synchronization control (flywheel) * Mode control for RDS/RBDS processing * Different RDS/RBDS block information output modes (e.g. A/C' block output mode). External decoding of the raw RDS bitstream, would require a microcontroller interrupt every 842 s. The double 16-bit RDS buffer allows the RDS data to be monitored at a 16 times lower rate, i.e. every 13.5 ms. In the SAA7724H two PLL circuits (PLL1 and PLL2) are available that deliver the clocks for the AUDIO_EPICS and the SRC_EPICS block. 6.12 RDS In the SAA7724H there are two RDS demodulation and decoder systems available. The description applies to each of the RDS blocks. 6.12.1 GENERAL DESCRIPTION The RDS function recovers the additional inaudible RDS information which is transmitted by FM radio broadcasting. The operational functions of the demodulator and decoder are in accordance with EBU specification EN 50067. The RDS function processes the RDS signal, that is frequency multiplexed in the stereo-multiplex signal, to recover the information transmitted over the RDS data channel. This processing consists of band-pass filtering, RDS demodulation and RDS/RBDS decoding. The stereo-multiplex signal is input from the IFP. Under control of I2C-bus bit rds_clkin, an internal buffer can be used to read out the raw RDS stream in bursts of 16 bits. With the I2C-bus bit rds_clkout the RDS clock can be enabled or switched off. The RDS band signal level can be read from a memory location in the SRC_EPICS, which needs to be defined. The RDS band-pass filter discards the audio content from the input signal and reduces the bandwidth. The RDS band signal level detector removes a possible Autofahrer Rundfunk Information (ARI) signal from the RDS band-pass filter output and measures the level of the remaining signal. 2003 Nov 18 39 Philips Semiconductors Preliminary specification Car radio digital signal processor SAA7724H handbook, full pagewidth RDS(n)_CLK rds(n)_clkout RDS(n)_DATA DECODER_BYPASS_MUX rds(n)_clkin 0 1 SRC_EPICS STEREOMPX RDS BAND-PASS FILTER OutMux MGW216 DEMODULATOR BSLP BSPA RDCL 0 1 RDDA RDS/RBDS DECODER (RBDS+) RDS_BUF_MUX BIT BUFFER (n) is 1 or 2. Fig.27 RDS/RBDS functional block diagram. 6.12.2 RDS I/O MODES data outputs via the I2C-bus, Apart from control inputs and the following inputs and outputs are related to the RDS function. Unbuffered raw RDS output mode (rds1_clkin = 0, rds2_clkin = 0, rds1_clkout = 1, rds2_clkout = 1 and DAVD mode: dac0 = 1 and dac1 = 1): * RDS_CLK: burst clock generated by the microcontroller. Bursts of 17 clock cycles are expected. The average time between bursts is 13.5 ms. * RDS_DATA: bursts of 16 raw RDS bits are output under control of the burst clock input. After a data burst, this output is HIGH. It is pulled LOW when 16 new bits are made available and a new clock burst is expected. The microcontroller has to monitor this line at least every 13.4 ms. DAVA, DAVB and DAVC modes (rds1_clkin = 0, rds2_clkin = 0, rds1_clkout = 0 and rds2_clkout = 0): * DAVN: data available signal for synchronization of data request between main controller and decoder; see Section 6.12.5.11. rds1_clkin = 1, rds2_clkin = 1, rds1_clkout = 1 and rds2_clkout = 1 is a not allowed mode. As shown in Fig.27, the same output is used for RDS_DATA and DAVN, depending on the selected mode. 6.12.3 RDS DEMODULATOR * RDS_CLK: clock of the raw RDS bitstream, extracted from the biphase coded baseband signal by the RDS demodulator. A clock period of 1.1875 kHz and 50 % duty cycle. The positive edge can be used to sample the RDS_DATA output. * RDS_DATA: raw RDS bitstream, generated by the demodulator detection of a positive going edge on the RDCL input signal. The data output changes every 100 s (this equals 18 of the RDS_BCK period) after the falling edge of RDS_BCK. This allows for external receivers of the RDS data to clock the data on the RDS_BCK signal as well as on its inverse. Buffered raw RDS output mode (rds1_clkin = 1, rds2_clkin = 1, rds1_clkout = 0, rds2_clkout = 0 and DAVD mode: dac0 = 1 and dac1 = 1): Phase jumps of the extracted RDS clock are detected and accumulated. If the accumulated phase shift exceeds a certain threshold, the RDS/RBDS decoder is informed by the bit slip (BSLP) signal. If the RDS/RBDS decoder 40 2003 Nov 18 DAVN Philips Semiconductors Preliminary specification Car radio digital signal processor detects a bit slip, the RDS demodulator is informed by the bit slip acknowledge (BSPA) signal. This causes the accumulation of RDS clock phase shifts to be cleared. 6.12.4 RDS BIT BUFFER * Bit slip correction * Data processing control * Restart of synchronization mode SAA7724H * Error correction control mode for synchronization * Data available control modes * Data output of RDS/RBDS information. The functions which are realized in the decoder are described in detail in the following Sections. The repetition frequency of RDS data is 1187.5 Hz. This results in an interrupt on the microcontroller every 842 s. The double 16-bit buffer enables this timing requirement to be relaxed. The two 16-bit buffers are alternately filled. If a buffer is not read out by the time the other buffer is filled, it will be overwritten and the old data will be lost. When a 16-bit buffer is being filled, the RDS bit buffer keeps the data line HIGH. If a 16-bit buffer is full, the data line is pulled down. The microcontroller has to monitor the data line at least every 13.5 ms. The data line remains LOW until the microcontroller pulls the clock line LOW. This initiates the reading of the buffer and the first bit is output on the data line. The RDS bit buffer outputs a bit on the data line after every falling clock edge. The data is valid when the clock is HIGH. After 16 falling and 16 rising edges, the whole buffer is read out and the bits are stored by the microcontroller. After a 17th falling clock edge, the data line is set HIGH until the other 16-bit buffer is full. The microcontroller stops communication by pulling the clock line HIGH again. 6.12.5 RDS/RBDS DECODER 6.12.5.1 RBDS processing mode The decoder is suitable for receivers intended for the European (RDS) and the USA (RBDS) standard. If the RBDS mode is selected (RBDS = 1) via the I2C-bus, the block detection and the error detection and correction are adjusted to RBDS data processing; i.e. E blocks are also treated as valid blocks. If RBDS is reset to zero then RDS mode is selected. 6.12.5.2 RDS/RBDS block detection The RDS/RBDS block detection is always active. For a received sequence of 26 data bits, a valid block and corresponding offset are identified using syndrome calculation. During a synchronization search, the syndrome is calculated with every newly received data bit (bit-by-bit) for a received 26-bit sequence. If the decoder is synchronized, syndrome calculation is activated only after 26 data bits for each new block are received. During RBDS reception, including the RDS block sequences with (A, B, C/C' and D) offset, block sequences of 4 blocks with offset E may also be received. If the decoder detects an `E-block', this block is marked in the block identification number (BlNr[2:0]) and is available via an I2C-bus request. In RBDS processing mode the block is signalled as valid `E-block' and in RDS processing mode, where only RDS blocks are expected, it is signalled as invalid `E-block'. This information can be used by the main controller to detect `E-block' sequences and identify RDS or RBDS transmitter stations. The RDS/RBDS decoder handles the complete data processing and decoding of the continuously received serial RDS/RBDS demodulator output data stream (RDDA and RDCL). Different data processing modes are software controllable by the external main controller via an I2C-bus request. All control signals are direct inputs to the decoder and are also available via the I2C-bus. Processed RDS/RBDS data blocks with corresponding decoder status information are available via the I2C-bus. The output signals of the decoder are direct outputs and available via the I2C-bus. The RDS/RBDS decoder contains the following functions: * RBDS processing mode * RDS/RBDS block detection * Error detection and correction * Synchronization * Flywheel for synchronization hold 2003 Nov 18 41 6.12.5.3 Error detection and correction The RDS/RBDS error detection and correction recognizes and corrects transmission errors within a received block via parity-check in consideration of the offset word of the expected block. Burst errors, with a maximum length of 5 bits, are corrected using this method; see Table 16. Philips Semiconductors Preliminary specification Car radio digital signal processor After synchronization has been detected the error correction is always active, depending on the pre-selected `error correction mode for synchronization' (mode SYNCA to SYNCD), but cannot be carried out in every reception situation. During a synchronization search, the error correction is disabled for detection of the first block and is enabled for processing of the second block, depending on the pre-selected error correction mode for synchronization. The processed block of data and the status of error correction are available for data request, via the I2C-bus, for the last two blocks. Table 16 RDS processed error correction EXB1 0 0 1 1 EXB0 0 1 0 1 DESCRIPTION no errors detected burst error of maximum 2 bits corrected burst error of maximum 5 bits corrected uncorrectable block SAA7724H reaches the pre-selected max_bad_blocks_gain, then the bit-by-bit search for the first block is restarted. If the RDS mode is selected then the next block is always calculated from the sequence A-B-C or C'-D, because E blocks are not allowed. If the RBDS mode is selected additional E blocks are allowed. However, while the synchronization search is active the block sequence E-E is always invalid (no synchronization will be found with E-E blocks in a row). If the first correctly detected block is block E, then the next expected block is block A; in this case no further expected blocks will be calculated. The decoder waits for an A block until the bad_blocks_counter value reaches the pre-selected max_bad_blocks_gain or a valid A block is received. If the first correct detected block is block D (in RBDS mode) then the next expected block will be block A. If the next expected block is block A (in RBDS mode) then a valid uncorrected block E is always allowed to be synchronized. If both blocks A and E fail, the next expected block calculated is block B and so on. For the second block, error correction may also be enabled, depending on the pre-selected correction mode SYNCA to SYNCD. Only valid and/or correctable second blocks are accepted for synchronization. If the pre-selected max_bad_blocks_gain value is set to zero, then (in this case only) the two-path synchronization search function is active independent of the selected RDS or RBDS mode. That is, if the first block was detected as a valid block, then Path 1 is open and the next expected block is calculated and stored. With each new received bit (bit-by-bit) syndrome calculation is started again until a second valid block is detected or 26 bits are received. If a second valid block was detected before 26 bits were received, then Path 2 is open, the block position (bit counter) is stored and the next expected block for Path 2 is calculated. If 26 bits have been received (after the first block Path 1) and the syndrome calculation gives the valid expected block for Path 1, then synchronization is detected and Path 2 is ignored. If 26 bits have been received (after the first block Path 1) and the syndrome calculation gives no validity or it is not the expected block for Path 1, then Path 1 is set to Path 2 values (if Path 2 is active): bit_count_path1 bit_count_path2 and expected_block_path1 expected_block_path2. Path 2 is 42 Processed blocks are characterized as uncorrectable under the following conditions: * During a synchronization search; if the burst error (for the second block) is higher than allowed by the pre-selected correction mode SYNCA to SYNCD * After synchronization has been detected; if the burst error exceeds the correctable maximum 5-bit burst error or if errors are detected but error correction is not possible. 6.12.5.4 Synchronization The decoder is synchronized if two valid blocks in a valid sequence are detected by the block detector; see Figs 8 and 9 for synchronization strategy overview. The search for the first block is done by a bit-by-bit syndrome calculation, starting after the first 26 bits have been received. This bit-by-bit syndrome calculation is carried out until the first valid, and error free, block has been received. The next block is then calculated and syndrome calculation is done after the next 26 bits have been received. The block-span in which the second valid and expected block can be received is selectable via the previous setting of the maximum bad blocks gain (RDS2_MBBG[4:0] or RDS1_MBBG[4:0]). If the second received block is an invalid block, then the bad_blocks_counter is incremented and the next new block is calculated. If the bad_blocks_counter value 2003 Nov 18 Philips Semiconductors Preliminary specification Car radio digital signal processor then cleared and ready for new input, but only after reception of the next few bits (until 26) may synchronization be detected. Thus using this Path 2 implementation a much faster synchronization is given in cases of wrong block interpretation of the first detected block. If synchronization is detected, the synchronization status flag (SYNC) is set and available via an I2C-bus request. The synchronization is held until the bad_blocks_counter value reaches the pre-selected max_bad_blocks_lose value (used for synchronization hold) or an external restart of synchronization is performed (NWSY = 1 or Power-on reset). SAA7724H 6.12.5.7 Data processing control The decoder provides different operating modes selectable by the NWSY, SYM0, SYM1, DAC0 and DAC1 inputs via the external I2C-bus. The data processing control performs the pre-selected operating modes and controls the requested output of the RDS/RBDS information. 6.12.5.8 Restart of synchronization mode 6.12.5.5 Flywheel for synchronization hold The `restart synchronization' (NWSY) control mode immediately terminates the actual synchronization and restarts a new synchronization search procedure (NWSY = 1). The NWSY flag is automatically reset after the restart of synchronization by the decoder [NeW SYnchronization Restart (NWSYRe pulse)]. This mode is required for a fast new synchronization on the RDS/RBDS data from a new transmitter station if the tuning frequency is changed by the radio set. Restart of a synchronization search is automatically carried out if the internal flywheel signals a loss of synchronization. An internal flywheel is implemented to enable a fast detection of loss of synchronization. Therefore one counter (bad_blocks_counter) checks the number of uncorrectable blocks and a second counter (good_blocks_counter) checks the number of error free or correctable blocks. Error blocks increment the bad_blocks_counter value and valid blocks increment the good_blocks_counter value. If the counter value of the good_blocks_counter reaches the pre-selected max_good_blocks_lose value (MGBL[5:0]) then the good_blocks_counter and bad_blocks_counters are reset to zero. However, if the bad_blocks_counter value reaches the pre-selected max_bad_blocks_lose value (MBBL[5:0]) then a new synchronization search (bit-by-bit) is started (SYNC = 0) and both counters are reset to zero. The flywheel function is only activated if the decoder is synchronized. The synchronization is held until the bad_blocks_counter value reaches the pre-selected max_bad_blocks_lose value (loss of synchronization) or an external forced start of a new synchronization search (NWSY = 1) is performed. The maximum values for the flywheel counters are both adjustable via the I2C-bus in a range of 0 to 63. 6.12.5.9 Error correction control mode for synchronization For error correction and identification of valid blocks during a synchronization search and synchronization hold, four different modes can be selected by control mode inputs SYM1 and SYM0: 1. Mode SYNCA (SYM1 = 0 and SYM0 = 0): no error correction; the blocks that are detected as correctable are treated as invalid blocks, the internal bad_blocks_counter value is still incremented even if correctable errors are detected. If synchronized, only error free blocks increment the good_blocks_counter value. All blocks except error free blocks increment the bad_blocks_counter value. 2. Mode SYNCB (SYM1 = 0 and SYM0 = 1): error correction of burst error maximum 2 bits; the blocks that are corrected are treated as valid blocks, all other errors detected are treated as invalid blocks. If synchronized, error free and correctable maximum 2-bit errors increment the good_blocks_counter value. 3. Mode SYNCC (SYM1 = 1 and SYM0 = 0): error correction of burst error maximum 5 bits; the blocks that are corrected are treated as valid blocks, all other errors detected are treated as invalid blocks. If synchronized, error free and correctable maximum 5-bit errors increment the good_blocks_counter value. 6.12.5.6 Bit slip correction During poor reception situations phase shifts of one bit to the left or right (1-bit slip) between the RDS/RBDS clock and data may occur, depending on the lock conditions of the demodulators clock regeneration. If the decoder is synchronized and detects a bit slip (BSLP = 1), the synchronization is corrected by +1, 0 or -1 bit via block detection on the respectively shifted expected new block. 2003 Nov 18 43 Philips Semiconductors Preliminary specification Car radio digital signal processor 4. Mode SYNCD (SYM1 = 1 and SYM0 = 1): no error correction; the blocks that are detected as correctable are treated as invalid blocks, if in synchronization search mode. The internal bad_blocks_counter value is always incremented even if correctable errors are detected. If synchronized, error free blocks and correctable maximum 5-bit errors increment the good_blocks_counter value. Only uncorrectable blocks increment the bad_blocks_counter value. SAA7724H received before the previously processed block was completely transmitted via the I2C-bus. After detection of data overflow the interface registers are not updated (no DecWrE) until reset of the data overflow flag (DOFL = 0) by reading via the I2C-bus or if NWSY = 1 which results in the start of a new synchronization search (SYNC = 0). 6.12.5.11 Data output of RDS/RBDS information The decoded RDS/RBDS block information and the current decoder status is available via the I2C-bus. For synchronization of data request between the main controller and decoder the additional data available output (DAVN) is used. For timing information see Section 10.1. If the decoder has processed new information for the main controller the data available signal (DAVN) is activated (LOW) under the following conditions: * During a synchronization search in DAVB mode if a valid A or C' block has been detected. This mode can be used for fast search tuning (detection and comparison of the PI code contained in the A and C' blocks). * During a synchronization search in any DAV mode (except DAVD mode), if two blocks in the correct sequence have been detected (synchronization criterion fulfilled) * If the decoder is synchronized and, in mode DAVA and DAVB, a new block has been processed; this mode is the standard data output mode * If the decoder is synchronized and, in DAVC mode, two new blocks have been processed * If the decoder is synchronized and, in any DAV mode (except DAVD mode), loss of synchronization is detected (flywheel loss of synchronization, resulting in a restart of the synchronization search) * In any DAV mode (except DAVD mode), if a reset caused by power-on or a voltage drop is detected (PresN = 0). Remark: If the decoder is synchronized, the DAVN signal is always activated after 21.9 ms in DAVA or DAVB mode and after 43.8 ms in DAVC mode independent of valid or invalid blocks being received. The processed RDS/RBDS data is available for an I2C-bus request for at least 20 ms after the DAVN signal was activated. The DAVN signal is always automatically deactivated (HIGH) after ~10 ms or almost after the main controller has read the RDS/RBDS status byte via the I2C-bus (see DAVN timing). 6.12.5.10 Data available control modes The decoder provides three different RDS/RBDS data output processing modes plus one decoder bypass mode which are selectable via the `data available' control mode inputs DAC1 and DAC0. * Mode DAVA (DAC1 = 0 and DAC0 = 0): standard output mode; if the decoder is synchronized and a new block is received (every 26 bits), the actual RDS/RBDS information of the last two blocks is available with every new received block (approximately every 21.9 ms). * Mode DAVB (DAC1 = 0 and DAC0 = 1): fast PI search mode; during synchronization search and if a new A or C' block is received, the actual RDS/RBDS information of this or the last two A or C' blocks respectively is available with every new received A or C' block. If the decoder is synchronized, the `standard output mode' is active. * Mode DAVC (DAC1 = 1 and DAC0 = 0): reduced data request output mode; if the decoder is synchronized and two new blocks are received (every 52 bits), the actual RDS/RBDS information of the last two blocks is available with every two new received blocks (approximately every 43.8 ms). * Mode DAVD (DAC1 = 1 and DAC0 = 1): decoder bypassed mode; if this mode is selected then the OutMux output of the decoder is reset to LOW (OutMux = 0). The MADRE internal row buffer output is then active and the decoder is bypassed. The decoder provides data output of the block identification of the last and previously processed blocks, the RDS/RBDS information words and error detection/correction status of the last two blocks together with general decoder status information. In addition the decoder output is controlled indirectly by the data request from the external main controller. The decoder receives a `data overflow' (DOFL) signal controlled by the I2C-bus register interface. This DOFL signal has to be set HIGH (DOFL = 1) if the decoder is synchronized and a new RDS/RBDS block is 2003 Nov 18 44 Philips Semiconductors Preliminary specification Car radio digital signal processor SAA7724H The decoder ignores new processed RDS/RBDS blocks if the DAVN signal is active or if data overflow occurs (DOFL = 1). Tables 17 and 18 show the block identification number and processed error status outputs of the decoder and how to interpret the output data. Table 17 RDS block identification number BLNR2 0 0 0 0 1 1 1 1 Table 18 RDS processed error correction EXB1 0 0 1 1 EXB0 0 1 0 1 no errors detected burst error of maximum 2 bits corrected burst error of maximum 5 bits corrected uncorrectable block DESCRIPTION BLNR1 0 0 1 1 0 0 1 1 BLNR0 0 1 0 1 0 1 0 1 BLOCK IDENTIFICATION block A block B block C block D block C' block E (RBDS mode) invalid block E (RDS mode) invalid block 6.12.5.12 Power-on reset Reset of the chip will cause a number of I2C-bus registers to be set to specific default values; see Chapter 11.5. If the decoder detects the reset, the status bit `reset detected' (RSTD) is set and available via an I2C-bus request. The RSTD flag is deactivated after the decoder status register is read by the I2C-bus. 2003 Nov 18 45 Philips Semiconductors Preliminary specification Car radio digital signal processor 7 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134); note 1 SYMBOL VDDD VDD(I/O) VDD(REG) VDDA IDDD ISSD IDD(I/O) ISS(I/O) IIK Vlim(5V) Tamb Tstg Vesd Ilu(prot) Notes PARAMETER supply voltage on pin VDDD supply voltage on pin VDD(I/O) supply voltage on pin VDD(REG) supply voltage on pin VDDA supply current pin VDDD supply current pin VSSD supply current pin VDD(I/O) supply current pin VSS(I/O) DC input clamp diode current 5 V tolerant pins voltage limits ambient temperature storage temperature electrostatic discharge voltage latch-up protection current HBM: 100 pF; 1500 MM: 200 pF; 2.5 H; 15 GQS (SNW-FQ-611 part E) fc = 43.2 MHz; VDDD = 2.5 V fc = 43.2 MHz; VDDD = 2.5 V fc = 43.2 MHz; VDDD = 3.3 V fc = 43.2 MHz; VDDD = 3.3 V VIL < -0.5 V or VIH > VDD(I/O) + 0.5 V; note 2 5 V tolerant outputs: disabled mode CONDITIONS MIN. -0.5 -0.5 -0.5 -0.5 - - - - - -0.5 -40 -55 2000 200 100 TYP. +2.5 +3.3 +3.3 +2.5 - - - - - - - - - - - SAA7724H MAX. +3.3 +4.2 +4.2 +3.3 750 750 750 750 10 +5.8 +85 +150 - - - UNIT V V V V mA mA mA mA mA V C C V V mA 1. Stresses greater than those listed above may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or at any other condition above those listed in the following recommended operating and characteristics section is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect device reliability. 2. Not applicable for 5 V tolerant pins. 8 THERMAL RESISTANCE PARAMETER thermal resistance from junction to ambient in free air CONDITION VALUE 45 UNIT K/W SYMBOL Rth(j-a) 2003 Nov 18 46 Philips Semiconductors Preliminary specification Car radio digital signal processor 9 DC CHARACTERISTICS Positive current flows into the device; 3.13 V VDD(I/O), VDD(REG) 3.47 V; 2.38 V VDDA, VDDD, VDD(OSC), VDD(IF) 2.62 V; Tamb = -40 C to +85 C. SYMBOL Digital parameters VDDD VDD(OSC) VDD(I/O) VDD(REG) IDD(tot) supply voltage on pin VDDD supply voltage on pin VDD(OSC) supply voltage on pin VDD(I/O) supply voltage on pin VDD(REG) total supply current fosc_in = 43.2 MHz pins VDDD pins VDD(I/O) pins VDDA1, VDDA2, VDD(IF), VDD(OSC) VIH HIGH-level input voltage VDD(I/O) = 3.3 V; inputs TTL; excluding 5 V tolerant pins VDD(I/O) = 3.3 V; 5 V tolerant inputs TTL; including SDA pin VIL LOW-level input voltage inputs TTL; excluding SDA pin 5 V tolerant inputs TTL; including SDA pin VOH HIGH-level output voltage IOH = -4 mA; VDD(I/O) = 3.3 V 10 ns slew rate outputs 4 mA outputs VOL LOW-level output voltage 10 ns slew rate outputs; IOL = 4 mA; VDD(I/O) = 3.3 V 4 mA outputs; IOL = 4 mA SDA output; IOL = 3 mA; VDD(I/O) = 3.3 V ILI input leakage current Schmitt trigger input without pull-down; excluding 5 V tolerant pins VI = VSS(I/O) VI = VDD(I/O) Schmitt trigger input without pull-down; 5 V tolerant pins only VI = 5 V VI = 0 V - - - - - - - - 2.9 2.9 - - - - - - - - - - - 1.7 2.0 0 0 2.38 2.38 3.13 3.13 2.5 2.5 3.3 3.3 PARAMETER CONDITIONS MIN. SAA7724H TYP. MAX. UNIT 2.62 2.62 3.47 3.47 260 10 216 3.3 5.5 0.7 0.8 V V V V mA mA mA V V V V 215 5 180 - - - - - - 0.4 0.4 0.4 V V V V V -1 1 A A 4.5 -4.5 A A 2003 Nov 18 47 Philips Semiconductors Preliminary specification Car radio digital signal processor SAA7724H SYMBOL IOL(Z) PARAMETER 3-state leakage current CONDITIONS VI = VSS(I/O); 3-state outputs without pull-down; excluding 5 V tolerant pins VI = VDD(I/O); 3-state outputs; excluding 5V tolerant pins MIN. - TYP. - MAX. UNIT -1 A - - - 1 64 A A VI = 5 V; 3-state outputs and - open-drain outputs without pull-down; 5 V tolerant pins only Vhys Schmitt trigger hysteresis Schmitt trigger inputs; excluding 0.4 SDA pin Schmitt trigger inputs; 5 V tolerant pins only pin SDA; VDD(I/O) = 3.3 V IDD(q) II(pd) digital quiescent current input pull-down current VDDD = 2.62 V; VDD(I/O) = 3.47 V; note 1 VDD < Vi < VDD(I/O); all pins with pull-down 0.3 0.15 - 15 - - - - 50 - - - 1 100 V V V mA A Analog parameters VDDA1 VVREFAD analog supply voltage common-mode reference voltage VVREFAD is determined by VVADCP and VVADCN [VVADCP - VVADCN] IO < 2 mA 2.38 45 2.5 50 2.62 55 V % ZO VDD(IF) VVREFIF VDAC VVDACP ZO(DAC) IADC(pos) VDD(OSC) Regulator VDD(REG) VDD(REG)(ctrl) Note output impedance pin VREFAD IF_AD supply voltage IF_AD reference voltage DAC supply voltage DAC positive reference voltage DAC output impedance ADC reference current oscillator supply voltage - 2.38 - 2.38 10 2.5 0.775 2.5 100 0.9 180 2.5 100 2.62 1 2.62 - 1.2 - 2.62 V V V % k A V VDDA2 - VVDACN pins LRV, RRV, LFV and RFV - 0.65 - 2.38 regulator supply voltage regulator control range PMOST BSH207 in application VDD(REG) = 3.3 V 2.5 1 2.58 - 2.66 3.3 V V 1. IDD(q) quiescent device current testing is a proven technique to increase device quality. The testing will be performed in several different logic states, but no guarantee can be given that the current will stay below the specified maximum value in every arbitrary static device state. 2003 Nov 18 48 Philips Semiconductors Preliminary specification Car radio digital signal processor 10 AC CHARACTERISTICS Positive current flows into the device; 3.13V VDD(I/O), VDD(REG) 3.47 V; 2.38V VDDA, VDDD, VDD(OSC), VDD(IF) 2.62 V; Tamb = -40 C to +85 C. SYMBOL Analog inputs DIFFERENTIAL MEASUREMENTS VIA AUDIOAD_1 AND AUDIOAD_2; B = 20 KHZ PSRR ct power supply rejection ratio Vi = 0.1 V (peak); fi = 1 kHz 35 - - - PARAMETER CONDITIONS MIN. TYP. SAA7724H MAX. UNIT - -70 dB dB cross-talk between pins AIN(x) VAIN(x) = 0.5 V (RMS); fi = 15 kHz; ADIFF(x) path measured Pins ADIFF_LP, ADIFF_LN, ADIFF_RP and ADIFF_RN Vi(dif)(rms) (THD + N)/S differential input voltage (RMS value) total harmonic distortion-plus-noise to signal ratio input resistance channel separation VAIN(x) = 0.5 V (RMS); fi = 15 kHz; ADIFF(x) path measured Vi = 1 V (RMS); fi = 1 kHz fi = 1 kHz; Vi = 0.1 V fi = 1 kHz; Vi = 0.5 V (RMS) fc at -3 dB Vi = 0.1 V (p); fi = 1 kHz Vi = 0.5 V (RMS); fi = 15 kHz; AIN(x) path measured Vi = 0.5 V (RMS); fi = 15 kHz; AIN(x) path measured nominal digital output level -2.5 dB fi = 1 kHz; Vi = 1 V (RMS) 0 dB input level -60 dB input level - - 45 - - - 57 - -75 -25 72 -70 dB dB k dB 0.85 1 1.15 V Ri cs Vo(ub) CMRR CMIR fres PSRR ct left and right unbalance common mode rejection ratio common mode input range frequency response -0.5 40 1.0 20 - - - - - - +0.5 - 1.5 - - -70 dB dB V kHz SINGLE-ENDED MEASUREMENTS VIA AUDIOAD_1 AND AUDIOAD_2; B = 20 KHZ 45 - dB power supply rejection ratio Pins ADIFF_LP, ADIFF_LN, ADIFF_RP, ADIFF_RN, AIN1_L, AIN1_R, AIN2_L and AIN2_R cross-talk dB cs channel separation - - -60 dB Pins AIN1_L, AIN1_R, AIN2_L and AIN2_R Vi(rms) (THD + N)/S input voltage (RMS value) total harmonic distortion-plus-noise to signal ratio input resistance left and right unbalance common mode rejection ratio common mode input range Vi = 0.5 V (RMS); fi = 1 kHz fi = 1 kHz; Vi = 0.1 V fi = 1 kHz; Vi = 0.5 V (RMS) 49 nominal digital output level -2.5 dB fi = 1 kHz; Vi = 0.5 V (RMS) 0 dB input level -60 dB input level - - 45 -0.5 40 1.0 - - 57 - - - -75 -25 72 +0.5 - 1.5 dB dB k dB dB V 0.4 0.5 0.6 V Ri Vo(ub) CMRR CMIR 2003 Nov 18 Philips Semiconductors Preliminary specification Car radio digital signal processor SAA7724H SYMBOL fres PARAMETER frequency response CONDITIONS fc at -3 dB 20 MIN. TYP. - MAX. - UNIT kHz MPX; PINS AIN1_L, AIN2_L ADIFF_LP AND ADIFF_LN; SINGLE-ENDED AND DIFFERENTIAL INPUTS MEASUREMENT VIA AUDIOAD_1 AND AUDIOAD_2 LEFT (THD + N)/S total harmonic distortion-plus-noise to signal ratio fi = 1 kHz; Vi = 0.5 V (RMS); single-ended; Vi = 1 V (RMS); differential; B = 40 kHz fi = 1 kHz; Vi = 0.5 mV (RMS); single-ended; Vi = 1 mV (RMS); differential; B = 40 kHz - -75 -70 dB - -15 -10 dB RDS; PINS AIN1_R, AIN2_R ADIFF_RP AND ADIFF_RN; SINGLE-ENDED AND DIFFERENTIAL INPUTS MEASUREMENT VIA AUDIOAD_1 AND AUDIOAD_2 RIGHT (THD + N)/S total harmonic distortion-plus-noise to signal ratio fi = 57 kHz; B = 4 kHz; Vi = 0.5 V (RMS); single-ended; Vi = 1 V (RMS); differential; 0 dB input level; reference level = Vi fi = 57 kHz; B = 4 kHz; Vi = 0.5 mV (RMS); single-ended; Vi = 1 mV (RMS); differential; -60 dB input level; reference level = Vi Vi(dif)(rms) (THD + N)/S differential input voltage (RMS value) total harmonic distortion-plus-noise to signal ratio fi = 1 kHz; nominal digital output level = -5 dB fi = 1 kHz; B = 4 kHz Vi = 0.5 V (RMS); 0 dB input level Vi = 50 mV (RMS) PSRR Ri CMRR CMIR fres power supply rejection ratio input resistance common mode rejection ratio common mode input range frequency response fi = 1 kHz; Vi = 0.1 V fi = 1 kHz fc at -3 dB amplitude = 0.1 V (p); fi = 1 kHz - - 15 90 40 1.0 32 - - - 120 - - - -45 -35 - 150 - 1.5 - dB dB dB k dB V kHz - - -65 dB - - -5 dB PINS MONO1_P, MONO1_N, MONO2_P AND MONO2_N; DIFFERENTIAL MEASUREMENTS VIA AUXAD_2 0.4 0.5 0.6 V 2003 Nov 18 50 Philips Semiconductors Preliminary specification Car radio digital signal processor SAA7724H SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT PINS MONO1_P, MONO1_N, MONO2_P AND MONO2_N; DIFFERENTIAL MEASUREMENTS VIA AUDIOAD_1 AND AUDIOAD_2 Vi(dif)(rms) (THD + N)/S differential input voltage (RMS value) total harmonic distortion-plus-noise to signal ratio fi = 1 kHz; nominal digital output level -2.5 dB fi = 1 kHz; B = 4 kHz Vi = 0.5 V (RMS); 0 dB input level Vi = 0.5 mV (RMS); -60 dB input level PSRR Ri CMRR CMIR fres Vi Voffset (THD + N)/S power supply rejection ratio input resistance common mode rejection ratio common mode input range frequency response fi = 1 kHz; Vi = 0.10 V fi = 1 kHz fc at -3 dB VVADCP - VVADCN = 2.5 V fi = 1 kHz Vi = 90 % x VR (p-p) Vi = 9 % x VR (p-p) fs = 5.4 MHz fc at -3 dB nominal digital output level 0 dB fi = 451 kHz fi = 10.701 MHz; includes influence of fc(LPF) Voffset Ri HDAM offset voltage input resistance AM harmonic distortion -34 dB (FS); measurement with respect to 0 dB (FS) fi = 225.500 kHz fi = 150.333 kHz IDAM AM intermodulation distortion f1 = 430 kHz; -12 dB (FS); f2 = 411 kHz; -22 dB (FS); measurement with respect to 0 dB (FS) - - - - - - -52 -52 -82 dB dB dB ADC + buffer + dither 0.82 0.815 -100 16 0.96 1.04 - 20 1.09 1.16 +100 24 V V mV k - - 500 32 - -34 - - -45 -28 - - dB dB k kHz Vi = 0.1 V (p-p); fi = 1 kHz - - 30 90 40 1.0 20 - - 120 - - - 2.5 +20 -70 -25 - 150 - 1.5 - 2.65 +150 dB dB dB k dB V kHz 0.4 0.5 0.6 V Analog inputs; pins IFSS1 and IFSS2 single-ended measurements via AUXAD_1 and AUXAD_2; B = 32 kHz input voltage offset voltage total harmonic distortion-plus-noise to signal ratio input resistance frequency response 2.35 -150 V mV Ri fres Vi(FS)(p-p) PINS IF_IN1, IF_IN2, IF_AD1 AND IF_AD2 full-scale input voltage (peak-to-peak value) 2003 Nov 18 51 Philips Semiconductors Preliminary specification Car radio digital signal processor SAA7724H SYMBOL HDFM PARAMETER FM harmonic distortion CONDITIONS measurement with respect to 0 dB (FS) fi = 10.7802 MHz; -6 dB (FS) fi = 5.3505 MHz; -10 dB (FS) fi = 3.567 MHz; -10 dB (FS) fi = 10.833 MHz; -9 dB (FS) - - - - - MIN. TYP. MAX. UNIT - - - - - -40 -44 -44 -66 -67 dB dB dB dB dB IDFM FM intermodulation distortion -12 dB (FS); measurement with respect to 0 dB (FS); f1 = 10.833 MHz; f2 = 10.967 MHz f1 = 451 kHz; f2 = 534.809 kHz; Vi = 85.3 mV (RMS); B = 6 kHz; measurement with respect to 0 dB (FS); DITGAIN = 8 f1 = 10.701 MHz; f2 = 10.89255 MHz; Vi = 171 mV (RMS); B = 180 kHz; measurement with respect to 0 dB (FS); DITGAIN = 8 Vi = 0.1 V (p); fi = 1 kHz fi = 10.701 MHz; amplitude = -12 dB (FS); measurement with respect to 0 dB (FS) fi = 451 kHz; amplitude = -12 dB (FS); measurement with respect to 0 dB (FS) S/NAM AM signal-to-noise ratio narrow-band 83 88 - dB S/NFM FM signal-to-noise ratio narrow-band 65 72 - dB PSRR ct(FM) power supply rejection ratio FM cross-talk 3 - 6 - - -39 dB dB ct(AM) AM cross-talk - - -47 dB Ri(IF_VG) Vdither(p-p) Gstep Gres input resistance pin IF_VG - DITGAIN = 15 56 - 3.5 400 - 84 - 5.3 mV Analog IF_AD dither DAC dither level (peak-to-peak) 70 Analog IF_AD dither gain DAC number of gain steps gain resolution 16 4.4 mV ------------steps 2003 Nov 18 52 Philips Semiconductors Preliminary specification Car radio digital signal processor SAA7724H SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT DAC measurements; 0 dB via I2S-bus; minimum AC impedance on DAC outputs = 100 k; filter capacitance on DAC outputs = 3.3 nF; B = 20 Hz to 20 kHz, Mixer muted PSRR power supply rejection ratio pin VDDA2 fripple = 1 kHz; Vripple = 0.1 V (p-p); CVDACP = 22 F 3 6 - dB VDAC deviation in output level of the amplitude = 0 dB (FS); front DAC voltage outputs with fi = 1 kHz respect to the average of the pins RRV and LRV front outputs pins RFV and LFV -0.38 -0.38 -0.5 - - - - -70 +0.38 +0.38 dB dB PINS RRV, LRV, RFV AND LFV m(f-r) ct matching of the front to rear averages crosstalk between the four DAC output voltages amplitude = 0 dB (FS); fi = 1 kHz amplitude = 0 dB; fi = 1 kHz; one output digital silence; three others 0 dB (FS); for all combinations fi = 1 kHz; all four DAC outputs driven 0 dB (FS); all mixers muted -60 dB (FS) 0 dB (FS); all mixers on and set to 0 dB DS Vo(DAC)(rms) digital silence DAC output voltage at maximum signal (RMS value) all zero digital input with respect to 0 dB (FS) AC impedance 100 k; fi = 1 kHz; VDDA2 = 2.5 V fi = 1 kHz; gain setting = 0 dB Vi = 0.50 V (RMS) Vi = 0.5 mV (RMS) SPDIF measurements; pins SPDIF1 and SPDIF2 Vi(p-p) Ri Vi(hys) input voltage level (peak-to-peak value) input resistance input hysteresis 0.2 - - 0.5 7 30 - - - 2.5 - - - - - V k mV mA/V mA - - - - -40 -20 dB dB - - - - 0.74 -80 -45 - -110 0.75 -75 -40 -60 -105 0.77 dB dB dB dB V +0.5 -60 dB dB (THD + N)/S total harmonic distortion-plus-noise to signal ratio Analog MIX output; pins RRV, LRV, RFV AND LFV THD total harmonic distortion summer input Quartz crystal oscillator measurements; pins OSC_IN and OSC_OUT; VDD(OSC) = 2.5 V; fi = 4 MHz Zo(xtal) Gxtal Ixtal crystal oscillator output impedance oscillator gain oscillator level dependent current difference Vi = 20 mV (RMS) Vi = 20 mV (RMS) Vi = 20 mV and 200 mV (RMS) 53 400 12 2 2003 Nov 18 Philips Semiconductors Preliminary specification Car radio digital signal processor SAA7724H SYMBOL PARAMETER CONDITIONS - - - - MIN. TYP. MAX. - - - - 250 UNIT Digital output rise and fall times; Tamb = 25 C; CL = 30 pF to(r) to(f) to(f)(SDA) output rise time LOW-to-HIGH 10 ns slew rate outputs transition 4 mA outputs output fall time HIGH-to-LOW transition output fall time HIGH-to-LOW transition pin SDA 10 ns slew rate outputs 4 mA outputs Cb = 10 pF to 400 pF 10 5 10 5 ns ns ns ns ns 20 + 0.1Cb I2S-bus inputs and outputs (see Fig.29) Tcy(BCK) I2S-bus bit clock cycle time fs = 48 kHz; pins EXT_IIS_BCK1 and EXT_IIS_BCK2 pins EXT_IIS_IO1 and EXT_IIS_IO2 pins IIS_IN1, IIS_IN2, IIS_IN3, IFP_IIS_IN1, IFP_IIS_I2O6 and IFP_IIS_I3O4 th;DAT data hold time pins EXT_IIS_IO1 and EXT_IIS_IO2 pins IIS_IN1, IIS_IN2, IIS_IN3, IFP_IIS_IN1, IFP_IIS_I2O6 and IFP_IIS_I3O4 td;DAT data delay time pins IIS_OUT1, IIS_OUT2, IIS_OUT3, EXT_IIS_WS1, EXT_IIS_BCK1, EXT_IIS_IO1, EXT_IIS_WS2, EXT_IIS_BCK2 and EXT_IIS_IO2 pins EXT_IIS_WS1 and EXT_IIS_WS2 pins EXT_IIS_WS1 and EXT_IIS_WS2 pins IIS_WS1 and IFP_IIS_WS 81.3 - - ns ts;DAT data set-up time 10 22.9 - - - - ns ns 5 0 - - - - ns ns - - 27 ns ts;WS th;WS td;WS word select set-up time word select hold time word select delay time 10 2 - - - - - - 27 ns ns ns RDS inputs and outputs; pins RDS_DATA and RDS_BCK; see Figs 30, 31, 32 and 33 TTDAV data valid period DAVA and DAVB mode DAVC mode tDAVNL tsr time data available signal is LOW clock set-up time DAVA, DAVB and DAVC mode 24.5 49.0 11.25 100 26.0 52.0 12.0 - 27.0 54.0 12.5 - RDS bit periods RDS bit periods RDS bit periods s 2003 Nov 18 54 Philips Semiconductors Preliminary specification Car radio digital signal processor SAA7724H SYMBOL Tpr thr tlr tdr twb Tpb thb tlb PARAMETER period time clock HIGH time clock LOW time data hold time wait time (burst mode) period time (burst mode) clock HIGH time (burst mode) clock LOW time (burst mode) CONDITIONS - MIN. 220 220 100 1 2 1 1 TYP. 842 - - - - - - - MAX. - 640 640 - - - - - UNIT s s s s s s s s I2C-bus inputs and outputs; pins SCL and SDA; value referenced to VIH minimum and VIL maximum levels; see Fig.28 fSCL tBUF tHD;STA tLOW tHIGH tSU;STA tHD;DAT tSU;DAT tr SCL clock frequency bus free time between a STOP and START condition hold time (repeated) START condition LOW period of the SCL clock HIGH period of the SCL clock set-up time for a repeated START condition data hold time data set-up time rise time of both SDA and SCL Cb = total capacitance of signals one bus line in pF fSCL = 400 kHz fSCL = 100 kHz tf tSU;STO Cb tSP fall time of both SDA and SCL signals set-up time for STOP condition capacitive load for each bus line pulse width of spikes which must be suppressed by the input filter Cb = total capacitance of one bus line in pF 20 + 0.1Cb 20 + 0.1Cb 20 + 0.1Cb 0.6 - 0 - - - - - - 300 1000 300 - 400 50 ns ns ns s pF ns 0 1.3 0.6 1.3 0.6 0.6 0 100 - - - - - - - - 400 - - - - - 0.9 - kHz s s s s s s ns 2003 Nov 18 55 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 2003 Nov 18 SDA t BUF t LOW tr tf t HD;STA t SP 10.1 Timing diagrams Philips Semiconductors Car radio digital signal processor Fig.28 Definition of timing on the I2C-bus. handbook, full pagewidth 56 SCL t HD;STA P S t HD;DAT t HIGH t SU;DAT t SU;STA t SU;STO Sr MBC611 P Preliminary specification SAA7724H Philips Semiconductors Preliminary specification Car radio digital signal processor SAA7724H handbook, full pagewidth t h;WS t s;WS WS (IN) LEFT WS (OUT) RIGHT t d;WS tr t BCK(H) tf t BCK(L) t d;DAT BCK t h;DAT Tcy t s;DAT DATA (IN) DATA (OUT) MGW231 Fig.29 I2S-bus timing diagram for digital audio inputs/outputs. handbook, full pagewidth RDS_DATA RDS_BCK t sr Tpr t hr t lr t dr MGW226 Fig.30 RDS timing diagram in direct output mode. 2003 Nov 18 57 Philips Semiconductors Preliminary specification Car radio digital signal processor SAA7724H handbook, full pagewidth RDS_DATA D0 D1 D2 D13 D14 D15 RDS_BCK t wb Tpb t hb t lb MGW227 Fig.31 Timing diagram of interface signals between RDS function and microcontroller in buffered output mode. handbook, full pagewidth t DAVNL DAVN T TDAV MGW228 Fig.32 RDS data available signal (DAVN); no I2C-bus request during DAVN LOW time (decoder is synchronized). 2003 Nov 18 58 Philips Semiconductors Preliminary specification Car radio digital signal processor SAA7724H handbook, full pagewidth I2C-bus R(B)DS status register read t DAVNL DAVN T TDAV MGW229 Fig.33 RDS data available signal (DAVN); DAVN LOW timing shorten by data request via I2C-bus (decoder is synchronized). 11 I2C-BUS CONTROL General description of the I2C-bus format in a booklet can be obtained at Philips Semiconductors, International Marketing and Sales. For the external control of the chip a fast I2C-bus is implemented. This is a 400 kHz bus which is downward compatible with the standard 100 kHz bus. There are two different types of control instructions: * Instructions to control the DSP programs, programming the coefficient RAM and reading the values of parameters * Instructions controlling the DATA I2S-bus flow, like source selection and clock speed. 11.1 I2C-bus protocol The bidirectional I2C-bus interface acts as a slave transceiver while an external microcontroller acts as a master transceiver. Communication between the MPI and the microcontroller is based on the I2C-bus protocol. The data transfer on the I2C-bus is shown in Fig.34. The I2C-bus has two lines: a Serial Clock line SCL and a Serial Data line SDA. Because the I2C-bus is a multi-master bus, arbitration between different master devices is achieved by using a START condition. The master device pulls the open-drain data line LOW while the clock line remains HIGH. After the bus has been `won' in this way, data is transmitted serially in packets of 8 bits plus an extra clock pulse for an acknowledgement flag from the receiving device. handbook, full pagewidth SDA 7 6 0 ACK SCL START 7 data MSB 6 data 2 0 data LSB acknowledge STOP MGW217 Fig.34 I2C-bus interface data transfer sequence. 2003 Nov 18 59 Philips Semiconductors Preliminary specification Car radio digital signal processor 11.1.1 PROTOCOL OF THE I2C-BUS COMMANDS SAA7724H address (2 bytes over the I2C-bus) which represents the starting memory address for the data transfer. In the event that a read command is received before the address register has been written, a negative acknowledgement will be generated. In the write mode, the transfer of data words continues until the master device stops the transfer with a STOP condition (P). In the read mode, the data transfer continues until a negative acknowledgement and STOP condition is generated by the master. In the read mode the last word will not be transmitted to the I2C-bus while the I2C-bus interface is stopped by the master. When reading from or writing to an invalid address a negative acknowledge will be generated after the first data byte, and the master must then send a STOP condition. An acknowledge is generated on all memory locations if selected. Also, within a given boundary, an acknowledge will be generated when selected, although the physical size of the memory may not be that large. These are the reserved locations in the I2C-bus memory map. A negative acknowledge will only be generated in unused spaces of the I2C-bus map. The SAA7724H acts as a slave receiver or slave transmitter; therefore the clock signal is only an input signal. The data signal is a bidirectional open-drain line at the IC pin level. The SAA7724H slave address has a subaddress bit A0 (bit 1) which allows the device to have 1 or 2 different addresses. The least significant bit (bit 0) represents the read/write mode. The read and write I2C-bus commands are illustrated in Figs 35 to 40, showing SDA. The I2C-bus interface will generate a negative acknowledge on the SDA line in the event that the data transfer was not completed successfully. After generating a START condition, the master device has to transmit a slave address. The slave I2C-bus interface responds to its own address (given in the first data byte) by sending an acknowledgement to the master device. The direction flag (bit 0) is always transmitted in this first byte so that the slave knows in which mode it has to operate. Initially, the I2C-bus interface receives a 16-bit handbook, full pagewidth S Device W A AddrH A AddrL A DataH A DataM A DataL A DataH A DataM A DataL A ...... P MHC653 0 0 1 1 1 0 A0 R/W Fig.35 Write cycle EPICS (XRAM). handbook, full pagewidth S Device W A AddrH A AddrL A Sr Device R A DataH A DataM A DataL A DataH A ...... NA P MHC654 0 0 1 1 1 0 A0 R/W Fig.36 Read cycle EPICS (XRAM). 2003 Nov 18 60 Philips Semiconductors Preliminary specification Car radio digital signal processor SAA7724H handbook, full pagewidth S Device W A AddrH A AddrL A DataM A DataL A DataM A DataL A ...... P MHC655 0 0 1 1 1 0 A0 R/W Fig.37 Write cycle EPICS (YRAM). handbook, full pagewidth S Device W A AddrH A AddrL A Sr Device R A DataM A DataL A DataM A ...... NA P MHC656 0 0 1 1 1 0 A0 R/W Fig.38 Read cycle EPICS (YRAM). handbook, full pagewidth S Device W A AddrH A AddrL A DataM A DataL A DataM A DataL A DataM A DataL A ...... P MHC657 0 0 1 1 1 0 A0 R/W Fig.39 Write cycle IFP. handbook, full pagewidth S Device W A AddrH A AddrL A Sr Device R A DataM A DataL A DataM A DataL A ...... NA P MHC658 0 0 1 1 1 0 A0 R/W Fig.40 Read cycle IFP. 2003 Nov 18 61 Philips Semiconductors Preliminary specification Car radio digital signal processor Table 19 I2C-bus symbol description SYMBOL S Sr P R W A A NA Device AddrH and AddrL DataH, DataM and DataL DataM and DataL 11.2 MPI data transfer formats START condition repeated START condition STOP condition read bit (1) write bit (0) acknowledge from slave (SAA7724H) acknowledge from master (microcontroller) negative acknowledge from master to stop the data transfer device address address memory map data of XRAM (3 bytes) data of YRAM or IFP (2 bytes) DESCRIPTION SAA7724H Table 20 Data transfer formats; note 1 TRANSFER Y transfer MPI YRAM Y transfer YRAM I2C-bus X transfer I2C-bus XRAM X transfer XRAM transfer IFP Note 1. M = MSB, L = LSB and X = don't care. I2C-bus transfer I2C-bus IFP I2C-bus I2C-bus: YRAM: I2C-bus: XRAM: I2C-bus: IFP_DATA_R: FROM XXXXM----------L YRAM: M----------L I2C-bus: M----------------------L XRAM: M----------------------L M--------------L I2C-bus: I2C-bus: M--------------L IFP: TO M----------L XXXXM----------L M----------------------L M----------------------L M--------------L M----------L 2003 Nov 18 62 Philips Semiconductors Preliminary specification Car radio digital signal processor 11.3 Reset initialization SAA7724H * If A0 = 1 the following addresses are available: - Write: 00111010 = 3Ah - Read: 00111011 = 3Bh. 11.5 I2C-bus memory map specification With a synchronous reset the SAA7724H will turn to their idle position (state 0), the address counter is set to zero and the SDA_OUT line remains high-impedance. For the SDA line an asynchronous reset is also implemented which is connected directly to the RESET pin. During the asynchronous reset period the internal SDA_OUT line remains HIGH which results in a high-impedance SDA line. These two resets should have an overlap to have a proper initialization. It is also possible to reset the internal I2C-bus registers separately, and these registers will be set to their default values. 11.4 Defined I2C-bus address The I2C-bus memory map contains all defined I2C-bus bits related to RDS, SRC and EPICS control and allocates EPICS, SRC and IFP RAM sizes. The memory spaces belonging to the AUDIO_EPICS are referred to as EPICS registers, and memory spaces belonging to the SRC/RDS EPICS are referred to as SRC registers. The RDS registers control the RDS1 and RDS2 blocks simultaneously while providing each RDS1 and RDS2 block with its own decoded data and status registers: the memory map is given in Table 21. Detailed memory map locations of the hardware registers related to the I2C-bus EPICS control are given in Table 23 and the I2C-bus RDS control are given in Table 24. The I2C-bus address is defined for location: 001110P; the least significant bit is a programmable bit with the external pin A0_pin. Two possible options are available with this pin: * If A0 = 0 the following addresses are available: - Write: 00111000 = 38h - Read: 00111001 = 39h. Table 21 I2C-bus memory map; notes 1 and 2 BLOCK - SRC SRC SRC SRC SRC SRC SRC - - Global - RDS EPICS EPICS - IFP 2003 Nov 18 START (HEX) END (HEX) NAME NUMBER OF WORDS x BIT WIDTH (DEBUG PART) - - 128 x 12 - 1 x 24 1 x 24 - 768 x 24 - - 1 x 24 - 12 x 16 1 x 32 - - all 16-bit width ACCESS - - R/W - R/W R/W - R/W - - R/W - see Table 24 read - - R/W E000 B880 B800 B000 AFFF AFFE A300 A000 9000 6030 602F 6010 6000 5FFF 4000 3000 2C64 FFFF DFFF B87F B7FF AFFF AFFE AFFD A2FF 9FFF 8FFF 602F 602E 600F 5FFF 5FFE 3FFF 2FFF not used reserved SRC_YRAM reserved IIC_SRC_PC IIC_SRC_STAT reserved SRC_XRAM reserved not used IIC_DSP_CTR not used RDS 1 and 2 registers IIC_SILICON_ID reserved not used IFP registers 63 Philips Semiconductors Preliminary specification Car radio digital signal processor SAA7724H BLOCK - IFP IFP IFP IFP IFP IFP IFP IFP IFP IFP IFP EPICS EPICS EPICS EPICS EPICS EPICS EPICS Notes START (HEX) END (HEX) NAME NUMBER OF WORDS x BIT WIDTH (DEBUG PART) - 100 x 16 - 256 x 16 256 x 16 256 x 16 256 x 16 256 x 16 256 x 16 - 128 x 16 - 1024 x 12 1 x 24 1 x 24 14 x 24 - 3584 x 24 ACCESS - R/W - R/W R/W R/W R/W R/W R/W - R/W R/W - R/W R/W R/W R/W - R/W 1400 2C00 2700 2600 2500 2400 2300 2200 2100 2081 2080 2000 1400 1000 0FFF 0FFE 0FF0 0E00 0000 2C63 2C63 2BFF 26FF 25FF 24FF 23FF 22FF 21FF 20FF 2080 207F 1FFF 13FF 0FFF 0FFE 0FFD 0FEF 0DFF reserved FP_RAM reserved VY3_RAM VX3_RAM VY2_RAM VX2_RAM VY1_RAM VX1_RAM reserved SWB_RAM reserved EPICS_YRAM IIC_EPICS_PC IIC_EPICS_STAT EPICS registers reserved EPICS_XRAM IIC_SWB_ERR_STAT 1 x 16 1. At all `reserved' spaces an acknowledge (ACK) will be generated. 2. At all `not used' spaces a negative acknowledge (NACK) will be generated. Table 22 I2C-bus memory map SRC_EPICS hardware register overview LOCATION (HEX) AFFF AFFE REGISTER NAME IIC_SRC_PC IIC_SRC_STAT # USED BITS 24 24 READ/WRITE R/W R/W Table 23 I2C-bus memory map AUDIO_EPICS hardware register overview LOCATION (HEX) 0FFF 0FFE 0FFD 0FFC 0FFB 0FFA REGISTER NAME IIC_EPICS_PC IIC_EPICS_STAT IIC_DSPIO_CONF IIC_SEL IIC_IFAD_SEL IIC_HOST # USED BITS 24 24 9 20 10 12 READ/WRITE R/W R/W R/W R/W R/W R/W 2003 Nov 18 64 Philips Semiconductors Preliminary specification Car radio digital signal processor SAA7724H LOCATION (HEX) 0FF9 0FF8 0FF7 REGISTER NAME IIC_SPDIF_STAT IIC_SUM IIC_EPICS_START_ADDR # USED BITS 13 13 16 READ/WRITE read R/W R/W Table 24 I2C-bus memory map RDS hardware register overview LOCATION (HEX) 600F and 600E 600D 600C 600B 600A 6009 6008 6007 and 6006 6005 6004 6003 6002 6001 6000 REGISTER NAME not used IIC_RDS2_CTR IIC_RDS2_SET IIC_RDS2_CNT IIC_RDS2_PDAT IIC_RDS2_LDAT IIC_RDS2_STAT not used IIC_RDS1_CTR IIC_RDS1_SET IIC_RDS1_CNT IIC_RDS1_PDAT IIC_RDS1_LDAT IIC_RDS1_STAT # USED BITS - 11 15 16 16 16 8 - 11 15 16 16 16 8 READ/WRITE - write write read read read read - write write read read read read Table 25 I2C_EPICS_STAT status register (0FFEh) BIT 23 to 13 12 and 11 10 - F12 and F11 F10 SYMBOL DEFAULT 0h - 0 internal flags not used SPDIF2 lock status 0: not locked 1: locked 9 F9 0 SPDIF1 lock status 0: not locked 1: locked 8 F8 0 DSPIO8 status 0: input 1: output 7 F7 0 DSPIO7 status 0: input 1: output 6 F6 0 DSPIO6 status 0: input 1: output DESCRIPTION 2003 Nov 18 65 Philips Semiconductors Preliminary specification Car radio digital signal processor SAA7724H BIT 5 F5 SYMBOL DEFAULT 0 DSPIO5 status 0: input 1: output DESCRIPTION 4 F4 0 DSPIO4 status 0: input 1: output 3 F3 0 DSPIO3 status 0: input 1: output 2 F2 0 DSPIO2 status 0: input 1: output 1 F1 0 DSPIO1 status 0: input 1: output 0 F0 0 DSPIO0 status 0: input 1: output Table 26 IIC_DSPIO_CONF configuration register (0FFDh) BIT 23 to 9 8 - config_DSPIO8 SYMBOL DEFAULT - 0 not used port configuration for DSPIO8 0: input 1: output 7 config_DSPIO7 0 port configuration for DSPIO7 0: input 1: output 6 config_DSPIO6 0 port configuration for DSPIO6 0: input 1: output 5 config_DSPIO5 0 port configuration for DSPIO5 0: input 1: output 4 config_DSPIO4 0 port configuration for DSPIO4 0: input 1: output 3 config_DSPIO3 0 port configuration for DSPIO3 0: input 1: output DESCRIPTION 2003 Nov 18 66 Philips Semiconductors Preliminary specification Car radio digital signal processor SAA7724H BIT 2 SYMBOL config_DSPIO2 DEFAULT 0 0: input 1: output DESCRIPTION port configuration for DSPIO2 1 config_DSPIO1 0 port configuration for DSPIO1 0: input 1: output 0 config_DSPIO0 0 port configuration for DSPIO0 0: input 1: output Table 27 IIC_SEL selection register (0FFCh) BIT 23 to 20 19 - ch2_dc_offset SYMBOL DEFAULT - 1 not used DC offset filter for audio channel 2 0: disable 1: enable 18 ch1_dc_offset 1 DC offset filter for audio channel 1 0: disable 1: enable 17 aux2_sel_lev_ voice 0 select behavioural of the compensation filter for AUX channel 2 0: level inputs 1: voice inputs 16 aux1_sel_lev_ voice 0 select behavioural of the compensation filter for AUX channel 1 0: level inputs 1: voice inputs 15 ch2_wide_narrow 0 select bandwidth for audio channel 2 0: audio + RDS information 1: only audio data 14 ch1_wide_narrow 0 select bandwidth for audio channel 1 0: audio + RDS information 1: only audio data 13 sel_SPDIF2_IIS2 0 select input for SRC2 0: SPDIF 2 1: EXT_IIS2 12 sel_SPDIF1_IIS1 0 select input for SRC1 0: SPDIF 1 1: EXT_IIS1 11 and 10 9 8 7 and 6 2003 Nov 18 aic3[1:0] s2 intref2 aic2[1:0] 11 1 0 01 analog input control 3; see Table 6 AD normal/differential selection 2; see Table 4 AD internal reference 2; see Table 4 analog input control 2; see Table 5 67 DESCRIPTION Philips Semiconductors Preliminary specification Car radio digital signal processor SAA7724H BIT 5 4 3 2 and 1 0 s1 SYMBOL refc2 intref1 aic1[1:0] refc1 DEFAULT 1 0 0 00 0 DESCRIPTION AD reference control 2; see Table 4 AD normal/differential selection 1; see Table 4 AD internal reference 1; see Table 4 analog input control 1; see Table 5 AD reference control 1; see Table 4 Table 28 IIC_IFAD_SEL selection register (0FFBh) BIT 23 to 10 9 - ifad2_power SYMBOL DEFAULT - 1 not used controls activity of IFAD2 0: power low 1: power on 8 ifad1_power 1 controls activity of IFAD1 0: power low 1: power on 7 to 4 3 to 0 dith_gain_2[3:0] dith_gain_1[3:0] 0000 0000 control gain of IF-AD dither source 2 control gain of IF-AD dither source 1 DESCRIPTION Table 29 IIC_HOST register (0FFAh) BIT 23 to 20 19 - src2_ext_sel_out SYMBOL DEFAULT - 0 not used selects the external output port for SRC2 0: EXT_IIS1 1: EXT_IIS2 18 src1_ext_sel_out 1 selects the external output port for SRC1 0: EXT_IIS1 1: EXT_IIS2 17 src2_int_ext_out 0 selects the output destination for SRC2 0: internal (audio epics) 1: external (Ext_iis) 16 src1_int_ext_out 0 selects the output destination for SRC1 0: internal (audio epics) 1: external (Ext_iis) 15 src2_int_ext_in 1 selects the input source for SRC2 0: internal (audio epics) 1: external (Ext_iis/Spdif) 14 src1_int_ext_in 1 selects the input source for SRC1 0: internal (audio epics) 1: external (Ext_iis/Spdif) DESCRIPTION 2003 Nov 18 68 Philips Semiconductors Preliminary specification Car radio digital signal processor SAA7724H BIT 13 SYMBOL en_ifp_iis_bck DEFAULT 0 enable ifp_iis_bck 0: disable 1: enable DESCRIPTION 12 iboc_mode 0 selects outputs of IF decimation paths to come out at IFP_IIS ports 0: disable 1: enable 11 to 9 8 to 6 5 ext_host_io_ format2[2:0] ext_host_io_ format1[2:0] en_host_io 000 000 0 input data format for EXT_IIS2 port; see Table 10 input data format for EXT_IIS1 port; see Table 10 port output enable for IIS_OUT port 0: disable. IIS_OUT1, IIS_OUT2 and IIS_OUT3 set to zero; IIS_WS and IIS_BCK 3-stated 1: all pins enabled 4 to 2 1 0 host_io_format[2:0] - en_256FS 000 - 0 host input/output data format for I2S-bus port; see Table 12 not used 256 x fs clock output 0: disable 1: enable Table 30 IIC_SPDIF_STAT status register (0FF9h) BIT 23 to 17 16 - IFP_Status SYMBOL DEFAULT - - not used IFP_Status 0: disabled 1: enabled 15 and 14 13 and 12 - SPDIF2_ accuracy[1:0] - - not used accuracy of sampling frequency of SPDIF2 channel 00: level II 10: level III 01: level I 11: reserved 11 and 10 SPDIF2_fs[1:0] audio sampling frequency of SPDIF2 channel 00: 44.1 kHz 10: 48 kHz 01: reserved 11: 32 kHz 9 SPDIF2_emphasis - equalization of SPDIF2 channel 0: no pre-emphasis present 1: 50/15 s pre-emphasis present DESCRIPTION 2003 Nov 18 69 Philips Semiconductors Preliminary specification Car radio digital signal processor SAA7724H BIT 8 SYMBOL SPDIF2_content DEFAULT - 0: normal audio mode 1: data mode DESCRIPTION contents of SPDIF2 channel 7 and 6 5 and 4 - SPDIF1_ accuracy[1:0] - - not used accuracy of sampling frequency of SPDIF1 channel 00: level II 10: level III 01: level I 11: reserved 3 and 2 SPDIF1_fs[1:0] - audio sampling frequency of SPDIF1 channel 00: 44.1 kHz 10: 48 kHz 01: reserved 11: 32 kHz 1 SPDIF1_emphasis - equalization of SPDIF1 channel 0: no pre-emphasis present 1: 50/15 s pre-emphasis present 0 SPDIF1_content - contents of SPDIF1 channel 0: normal audio mode 1: data mode Table 31 IIC_SUM summer register (0FF8h) BIT 23 to 13 12 11 10 9 8 - rrm rlm frm flm mixc SYMBOL DEFAULT - 0 0 0 0 0 not used DAC summer RR enable; see Table 9 DAC summer RL enable; see Table 9 DAC summer FR enable; see Table 9 DAC summer FL enable; see Table 9 DAC summer input selection 0: MONO1 1: MONO2 7 ifin2_inpsel 0 select IFAD for IFIN2 input from IFP 0: for IF_AD2 1: for IF_AD1 6 ifin1_inpsel 0 select IFAD for IFIN1 input from IFP 0: for IF_AD1 1: for IF_AD2 5 to 0 volmix[5:0] 000000 DAC summer volume setting; see Table 8 DESCRIPTION 2003 Nov 18 70 Philips Semiconductors Preliminary specification Car radio digital signal processor Table 32 IIC_EPICS_START_ADDR address register (0FF7h) BIT 23 to 16 15 to 0 - start_addr[15:0] SYMBOL DEFAULT - 0000h not used DESCRIPTION SAA7724H start address for the AUDIO_EPICS; can be programmed before releasing `epics_pc_reset' bit; see Table 33 Table 33 IIC_DSP_CTR control register (602Fh) BIT 23 to 19 18 and 17 - pll2_clksel[1:0] SYMBOL DEFAULT - 01 not used choose PLL2 clock selection switch 00: low range 01: mid range 16 and 15 pll1_clksel[1:0] 00 choose PLL1 clock selection switch 00: low range 01: mid range 14 to 10 9 to 5 4 pll2_div[4:0] pll1_div[4:0] pll2_bypass 01101 10000 0 choose PLL2 division factor choose PLL1 division factor bypass option for SRC_EPICS; this is an evaluation mode only 0: PLL2 1: OSCIN_CLK 3 pll1_bypass 0 bypass option for AUDIO_EPICS clock; warning: the OSCIN_CLK is only used for evaluation; it is functionally not a valid setting 0: PLL2 1: OSCIN_CLK 2 1 - src_pc_reset - 1 not used program counter for SRC_EPICS reset 0: no reset 1: reset; program counter will always be set to 0000h 0 epics_pc_reset 1 program counter for AUDIO_EPICS reset 0: no reset 1: reset; program counter will be set to the `start_addr' value; see Table 32 Table 34 IIC_SILICON_ID register (5FFFh); BIT 31 to 16 15 to 12 11 to 7 6 to 0 SYMBOL dev_number[15:0] dev_version[3:0] mask_version[4:0] romcode_ version[6:0] DEFAULT - - - - DESCRIPTION development number; decimal number development version number; binary code mask version number; binary code ROM code version number; binary code DESCRIPTION 2003 Nov 18 71 Philips Semiconductors Preliminary specification Car radio digital signal processor Table 35 IIC_RDS2_CTR control register (600Dh) BIT 15 to 11 10 - sel_DAVN2_RDS_ Flag SYMBOL DEFAULT - 0 not used select DAVN2 control indicator 0: use RDS2 block 1: use FLAG from IFP 9 8 7 and 6 5 rds2_clkout rds2_clkin RDS2_DAC[1:0] RDS2_NWSY 0 1 00 0 see Table 37 start new synchronization 0: no start 1: start 4 to 0 RDS2_MBBG[4:0] 00000 maximum bad blocks gain see Table 36 DESCRIPTION SAA7724H Table 36 Description of bits rds2_clkout and rds2_clkin rds2_clkout 0 0 1 1 rds2_clkin 0 1 0 1 rds decoder burst mode with external clock as input rds demodulator not allowed DESCRIPTION Table 37 Description of bits RDS2_DAC1 and RDS0_DAC0 RDS2_DAC1 0 0 1 1 RDS2_DAC0 0 1 0 1 standard mode fast PI search mode reduced data request decoder bypass DESCRIPTION Table 38 IIC_RDS2_SET settings register (600Ch) BIT 15 14 and 13 12 to 7 6 - RDS2_SYM[1:0] RDS2_MGBL[5:0] RDS2_RBDS SYMBOL DEFAULT - 00 100000 0 not used see Table 39 maximum good blocks lose allow RBDS `E' blocks 0: not allow 1: allow 5 to 0 RDS2_MBBL[5:0] 100000 maximum bad blocks lose DESCRIPTION 2003 Nov 18 72 Philips Semiconductors Preliminary specification Car radio digital signal processor Table 39 Description of bits RDS2_SYM1 and RDS2_SYM0 RDS2_SYM1 0 0 1 1 RDS2_SYMO 0 1 0 1 no error correction maximum 2 bits burst error maximum 5 bits burst error no error correction DESCRIPTION SAA7724H Table 40 IIC_RDS2_CNT counter register (600Bh) BIT 15 to 10 9 to 5 4 to 2 1 and 0 SYMBOL RDS2_BBC[5:0] RDS2_GBC[4:0] RDS2_PBIN[2:0] RDS2_EPB[1:0] DEFAULT 000000 00000 111 00 bad blocks counter good blocks counter (only 5 MSBs are available) previous block identifier error status previously received block; see Table 41 DESCRIPTION Table 41 Description of bits RDS2_EPB1 and RDS2_EPB0 RDS2_EPB1 0 0 1 1 RDS2_EPB0 0 1 0 1 no errors detected maximum 2 bits maximum 5 bits uncorrectable DESCRIPTION Table 42 IIC_RDS2_PDAT register (600Ah) BIT 15 to 0 SYMBOL RDS2_PDAT[15:0] DEFAULT 0000h DESCRIPTION previously processed block data Table 43 IIC_RDS2_LDAT register (6009h) BIT 15 to 0 SYMBOL RDS2_LDAT[15:0] DEFAULT 0000h last processed block data DESCRIPTION Table 44 IIC_RDS2_STAT status register (6008h) BIT 15 to 8 7 - RDS2_SYNC SYMBOL DEFAULT - 0 not used synchronization found 0: no synchronization 1: synchronization 6 RDS2_DOFL 0 data overflow flag 0: no overflow 1: overflow DESCRIPTION 2003 Nov 18 73 Philips Semiconductors Preliminary specification Car radio digital signal processor SAA7724H BIT 5 SYMBOL RDS2_RSTD DEFAULT 0 reset detected 0: no reset 1: reset DESCRIPTION 4 to 2 1 and 0 RDS2_LBIN[2:0] RDS2_ELB[1:0] 111 00 last block identification error status last block; see Table 45 Table 45 Description of bits RDS2_ELB1 and RDS2_ELB0 RDS2_ELB1 0 0 1 1 RDS2_ELB0 0 1 0 1 no errors detected maximum 2 bits maximum 5 bits uncorrectable DESCRIPTION Table 46 IIC_RDS1_CTR control register (6005h) BIT 15 to 11 10 - sel_RDS_CLK1_ DAVN2 SYMBOL DEFAULT - 0 not used select usage for pin RDS_CLK1_DAVN2; pin is used for DAVN2 and IFP flag usage (depending on state of sel_DAVN2_RDS_Flag); otherwise pin is used as RDS_CLK1 for RDS1 block 1: DAVN2 and IFP flag usage 0: RDS_CLK1 9 8 7 and 6 5 rds1_clkout rds1_clkin RDS1_DAC[1:0] RDS1_NWSY 0 1 00 0 see Table 48 start new synchronization 0: no start 1: start 4 to 0 RDS1_MBBG[4:0] 00000 max bad blocks gain see Table 47 DESCRIPTION Table 47 Description of bits rds1_clkout and rds1_clkin rds1_clkout 0 0 1 1 rds1_clkin 0 1 0 1 decoder burst mode with external clock as input demodulator not allowed DESCRIPTION 2003 Nov 18 74 Philips Semiconductors Preliminary specification Car radio digital signal processor Table 48 Description of bits RDS1_DAC1 and RDS1_DAC0 RDS1_DAC1 0 0 1 1 RDS1_DAC0 0 1 0 1 standard mode fast PI search mode reduced data request decoder bypass DESCRIPTION SAA7724H Table 49 IIC_RDS1_SET settings register (6004h) BIT 15 14 and 13 12 to 7 6 - RDS1_SYM[1:0] RDS1_MGBL[5:0] RDS1_RBDS SYMBOL DEFAULT - 00 100000 0 not used see Table 50 maximum good blocks lose allow RBDS `E' blocks 0: not allowed 1: allowed 5 to 0 RDS1_MBBL[5:0] 100000 maximum bad blocks lose DESCRIPTION Table 50 Description of bits RDS1_SYM1 and RDS1_SYM0 RDS1_SYM1 0 0 1 1 RDS1_SYM0 0 1 0 1 no error correction maximum 2 bits burst error maximum 5 bits burst error no error correction DESCRIPTION Table 51 IIC_RDS1_CNT counter register (6003h) BIT 15 to 10 9 to 5 4 to 2 1 and 0 SYMBOL RDS1_BBC[5:0] RDS1_GBC[4:0] RDS1_PBIN[2:0] RDS1_EPB[1:0] DEFAULT 000000 00000 111 00 bad blocks counter good blocks counter (only 5 MSBs are available) previous block identifier error status previously received block; see Table 52 DESCRIPTION Table 52 Description of bits RDS1_EPB1 and RDS1_EPB0 RDS1_EPB1 0 0 1 1 RDS1_EPB0 0 1 0 1 no errors detected maximum 2 bits maximum 5 bits uncorrectable DESCRIPTION 2003 Nov 18 75 Philips Semiconductors Preliminary specification Car radio digital signal processor Table 53 IIC_RDS1_PDAT register (6002h) BIT 15 to 0 SYMBOL RDS1_PDAT[15:0] DEFAULT 0000h DESCRIPTION previously processed block data SAA7724H Table 54 IIC_RDS1_LDAT register (6001h) BIT 15 to 0 SYMBOL RDS1_LDAT[15:0] DEFAULT 0000h last processed block data DESCRIPTION Table 55 IIC_RDS1_STAT status register (6000h) BIT 15 to 8 7 - RDS1_SYNC SYMBOL DEFAULT 0 not used synchronization found 0: no synchronization 1: synchronization 6 RDS1_DOFL 0 data overflow flag 0: no overflow 1: overflow 5 RDS1_RSTD 0 reset detected 0: no reset 1: reset 4 to 2 1 and 0 RDS1_LBIN[2:0] RDS1_ELB[1:0] 111 00 last block identification error status last block; see Table 56 DESCRIPTION Table 56 Description of bits RDS1_ELB1 and RDS1_ELB0 RDS1_ELB1 0 0 1 1 RDS1_ELB0 0 1 0 1 no errors detected maximum 2 bits maximum 5 bits uncorrectable DESCRIPTION 2003 Nov 18 76 Philips Semiconductors Preliminary specification Car radio digital signal processor 12 I2S-BUS CONTROL 12.1 Basic system requirements SAA7724H transmitters and receivers which makes it difficult to define the master. In such systems there is usually a system master controlling digital audio data-flow between the various ICs. Transmitters then have to generate data under the control of an external clock, and so act as a slave. Figure 41 illustrates some simple system configurations and the basic interface timing. Note that the system master can be combined with a transmitter or receiver, and it may be enabled or disabled under software control or by pin programming. As shown in Fig.41, the bus has three lines: * Continuous serial clock (SCK) * Word Select (WS) * Serial Data (SD). The device generating SCK and WS is the master. The inter-IC sound (I2S-bus) was developed by Philips to facilitate communications between the ever increasing number of digital audio processing ICs in a typical audio system. The bus only has to handle audio data, while the other signals such as sub-coding and control are transferred separately. To minimize the number of pins required and to keep wiring simple, a 3-line serial bus is used consisting of a line for two time-multiplexed data channels, a word select line and a clock line. Since the transmitter and receiver have the same clock signal for data transmission, the transmitter as the master, has to generate the bit clock, word select signal and data. In complex systems however, there may be several handbook, full pagewidth Clock SCK TRANSMITTER Word Select WS Data SD RECEIVER TRANSMITTER SCK WS SD RECEIVER TRANSMITTER = MASTER RECEIVER = MASTER CONTROLLER SCK TRANSMITTER WS SD RECEIVER CONTROLLER = MASTER SCK WS SD word n - 1 right channel MSB word n left channel LSB MSB word n + 1 right channel MGW230 Fig.41 Simple system configurations and basic interface timing. 2003 Nov 18 77 Philips Semiconductors Preliminary specification Car radio digital signal processor 12.2 Serial data 12.3 Word select SAA7724H Serial data is transmitted in twos complement with the MSB first. The MSB is transmitted first because the transmitter and receiver may have different word lengths. It is not necessary for the transmitter to know how many bits the receiver can handle, nor does the receiver need to know how many bits are being transmitted. When the system word length is greater than the transmitter word length, the word is truncated (least significant bits are set to 0) for data transmission. If the receiver is sent more bits than it's word length, the bits after the LSB are ignored. However, if the receiver is sent fewer bits than it's word length the missing bits are set to zero internally. Therefore, the MSB has a fixed position whereas the position of the LSB depends on the word length. The transmitter always sends the MSB of the next word one clock period after the WS changes. Serial data sent by the transmitter may be synchronized with either the trailing (HIGH-to-LOW) or the leading (LOW-to-HIGH) edge of the clock signal. However, the serial data must be latched into the receiver on the leading edge of the serial clock signal so there are some restrictions when transmitting data that is synchronized with the leading edge. The word select line indicates the channel being transmitted: * WS = 0: channel 1 (left) * WS = 1: channel 2 (right). WS may change either on a trailing or leading edge of the serial clock, but it doesn't need to be symmetrical. In the slave, this signal is latched on the leading edge of the clock signal. The WS line changes one clock period before the MSB is transmitted. This allows the slave transmitter to derive synchronous timing of the serial data that will be set up for transmission. Furthermore, it enables the receiver to store the previous word and clear the input for the next word (see Fig.41). 2003 Nov 18 78 Philips Semiconductors Preliminary specification Car radio digital signal processor 13 PACKAGE OUTLINE QFP100: plastic quad flat package; 100 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm SAA7724H SOT317-3 c y X 80 81 51 50 ZE A e E HE A A2 A1 (A 3) Lp bp 100 1 wM D HD ZD B vM B 30 vMA 31 detail X L wM pin 1 index e bp 0 5 scale 10 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 3.4 A1 0.45 0.25 A2 2.90 2.65 A3 0.25 bp 0.40 0.25 c 0.25 0.14 D (1) 20.1 19.9 E (1) 14.1 13.9 e 0.65 HD 24.2 23.6 HE 18.2 17.6 L 1.95 Lp 1.0 0.73 v 0.2 w 0.15 y 0.1 Z D (1) Z E(1) 0.8 0.4 1.0 0.6 7 0o o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT317-3 REFERENCES IEC JEDEC MO-112 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-15 03-02-25 2003 Nov 18 79 Philips Semiconductors Preliminary specification Car radio digital signal processor 14 SOLDERING 14.1 Introduction to soldering surface mount packages SAA7724H To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results: * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250 C or 265 C, depending on solder material applied, SnPb or Pb-free respectively. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 14.4 Manual soldering This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. 14.2 Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 270 C depending on solder paste material. The top-surface temperature of the packages should preferably be kept: * below 225 C (SnPb process) or below 245 C (Pb-free process) - for all BGA, HTSSON-T and SSOP-T packages - for packages with a thickness 2.5 mm - for packages with a thickness < 2.5 mm and a volume 350 mm3 so called thick/large packages. * below 240 C (SnPb process) or below 260 C (Pb-free process) for packages with a thickness < 2.5 mm and a volume < 350 mm3 so called small/thin packages. Moisture sensitivity precautions, as indicated on packing, must be respected at all times. 14.3 Wave soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C. Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. 2003 Nov 18 80 Philips Semiconductors Preliminary specification Car radio digital signal processor 14.5 Suitability of surface mount IC packages for wave and reflow soldering methods PACKAGE(1) BGA, HTSSON..T(3), LBGA, LFBGA, SQFP, SSOP..T(3), TFBGA, USON, VFBGA DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP, HSQFP, HSSON, HTQFP, HTSSOP, HVQFN, HVSON, SMS PLCC(5), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO, VSSOP CWQCCN..L(8), PMFP(9), WQCCN..L(8) Notes not suitable not suitable(4) suitable not not recommended(5)(6) recommended(7) SAA7724H SOLDERING METHOD WAVE REFLOW(2) suitable suitable suitable suitable suitable not suitable not suitable 1. For more detailed information on the BGA packages refer to the "(LF)BGA Application Note" (AN01026); order a copy from your Philips Semiconductors sales office. 2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 3. These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature exceeding 217 C 10 C measured in the atmosphere of the reflow oven. The package body peak temperature must be kept as low as possible. 4. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. 5. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 6. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 7. Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 8. Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered pre-mounted on flex foil. However, the image sensor package can be mounted by the client on a flex foil by using a hot bar soldering process. The appropriate soldering profile can be provided on request. 9. Hot bar or manual soldering is suitable for PMFP packages. 2003 Nov 18 81 Philips Semiconductors Preliminary specification Car radio digital signal processor 15 DATA SHEET STATUS LEVEL I DATA SHEET STATUS(1) Objective data PRODUCT STATUS(2)(3) Development DEFINITION SAA7724H This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). II Preliminary data Qualification III Product data Production Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 16 DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 17 DISCLAIMERS Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. 2003 Nov 18 82 Philips Semiconductors Preliminary specification Car radio digital signal processor 18 PURCHASE OF PHILIPS I2C COMPONENTS SAA7724H Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011. 2003 Nov 18 83 Philips Semiconductors - a worldwide company Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com. (c) Koninklijke Philips Electronics N.V. 2003 SCA75 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 753503/02/pp84 Date of release: 2003 Nov 18 Document order number: 9397 750 11426 |
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