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PI6C2310
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PCI-X Clock Buffers
Product Features
* * * * * * * * * * Four synchronous outputs Selectable divider/multiplier Output Enable control Low phase error < 150 ps Allows clock input to have spread spectrum modulation for EMI reduction Low output skew < 200 ps Low cycle jitter < 200 ps Industrial temperature (-40 C to 85 C) 3.3V V supply Packages: 24-pin QSOP (Q) and 24-pin TSSOP (L)
Product Description
PI6C2310 is a low skew, low jitter, PLL clock buffer with divider or multiplier designed for PCI-X application in servers and workstations. There are two selectable input ranges using HF# input: 10-40 MHz and 40-80 MHz. All outputs are synchronized to the input and to the other outputs. Each output can be independently turned off to reduce EMI and power consumption.
Block Diagram
Pin Configuration
AGND 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 CLKIN AVCC VCC OUT0 OUT1 GND GND OUT2 OUT3 VCC OE3 OE2
OUT0 OUT1 OUT2 OUT3 PLL DIV FBOUT
VCC HF# DIV0 DIV1 GND GND FBIN FBOUT VCC OE0 OE1
OE[0:3] HF# CLKIN FBIN DIV[0:1]
24-Pin Q, L 19
18 17 16 15 14 13
20
Clock Select Table
HF# 1 1 1 1 0 0 0 0 DIV1 1 1 0 0 1 1 0 0 DIV0 1 0 1 0 1 0 1 0 OUTx CLKIN 2xCLKIN 33MHz 3xCLKIN 4xCLKIN CLKIN/2 CLKIN 66MHz 1.5xCLKIN 2xCLKIN 100MHz 133MHz 100MHz 133MHz 33MHz 66MHz CLKIN OUTx 33MHz 66MHz
1
PS8502
10/10/00
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6C2310 PCI-X Clock Buffers
Pin Description
Pin 16,17,20,21 11- 14 9 8 24 3 4,5 2,10,15,22 6 , 7 , 18 , 19 23 1 Type O I O I I I I P P P P Qty 4 4 1 1 1 1 2 4 4 1 1 Symbol OUT[0:3] OE[0:3] FBOUT FBIN CLKIN HF# DIV[0,1] VCC GND AVCC AGND De s cription Clock outputs. To achieve zero input to output delay, all outputs must have the same loading. Active high Output Enable, pulled up. When OE is low, OUT [0:3] outputs are disabled at low state. Feedback output. To achieve zero input to output delay, FBOUT must have the same loading as OUT[0:3]. Feedback input. 7pF must be added to the output driving this pin (FBOUT) in addition to the other load. Input Clock. High Frequency range, pulled up. "1" = Low, "0" = High. Divider/Multiplier Select, pulled up. 3.3V power Ground 3.3V analog power Analog ground
Absolute Maximum Ratings
Supply Voltage (VCC, AVCC) ................................................ 0.5V to +7.0V Input Voltage ................................................................ -0.5V to Vcc+0.5V Industrial Operating Temperature ....................................... -40C to +85C Storage Temperature ........................................................ -65C to +150C Junction Temperature ....................................................................... 150C Input ESD MIL-883, Method 3015, human body model ....................... 2kV
Operating Condition
Symbol VCC, AVCC Ta De s cription I/O Supply, Analog Core Supply Industrial Ambient Temperature M in. 3.0 -40 M ax. 3.6 +85 Units V C
2
PS8502
10/10/00
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6C2310 PCI-X Clock Buffers
DC Electrical Characteristics Over Operating Conditions
Symbol Vil Vih Iil Iih Vol Voh Idd_33 Idd_66 Idd_100 Idd_133 Co Ci Cl Lpin Parame te r Low Input Voltage High Input Voltage Low Input Current High Input Current Low Output Voltage High Output Voltage Supply Current Supply Current Supply Current Supply Current Output Capacitance Input Capacitance Load Capacitance Pin Inductance VIN = 0V VIN = VCC VCC = 3.0V, Iol = 12mA VCC = 3.0V, Ioh = -12mA Cl = 15pF, FOUT = 33MHz Cl = 15pF, FOUT = 66MHz Cl = 15pF, FOUT = 100MHz Cl = 15pF, FOUT = 133MHz 2.4 25 35 tbd 45 60 6 5 15 7 nH pF mA 2.0 50 uA 200 0.4 V Conditions M in. Typ. M ax. 0.8 V Units
Switching Characteristics (TA = 25C, VCC = 3.3V 0.3V, Cl = 15pF, FOUT = 66.67 MHz)
Symbol Fin Tpd Tsk Tskpp Tjc Tdc Tr/Tf Parame te r Input frequency High Freq., HF# = "0" Propagation delay Output skew Pkg to pkg skew Cycle jitter Duty cycle Rise/Fall time @1.4V 0.8V~2.0V 45 50 CLKIN to FBIN rising edges @VDD/2 @1.4V, rising edges @VDD/2, rising edges, same CLKIN 40 -150 66 80 15 0 200 400 200 55 1.5 % ns ps Te s t Conditions Low Freq., HF# = "1" M in. 10 Typ. 33 M ax. 40 MHz Units
Note: Tjc = Tp(n+1) -Tp(n) Tdc = Th/Tp Tp(n) = Period of the nth cycle Tp = Period cycle time Tp(n+1) = Period of nth+1 cycle Th = High time @1.4V
3
PS8502
10/10/00
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
2.0V 0.8V Tr Tf 2.0V 0.8V 1.4V Tp Figure 1. Rise/Fall time Figure 2. Duty cycle T1 1.4V OUTx Tsk 1.4V 1.65V Tp(n+1) Figure 4. Cycle jitter Tp(n) 1.65V OUTy Figure 3. Output skew Device1 OUTx 1.65V Tskp2p Device2 OUTy 1.65V FBIN CLKIN 1.65V Tpd 1.65V Figure 5. Pkg.-to-Pkg. skew Figure 6. Propagation Delay DUT OUTx 15pF Figure 7. Test load
PI6C2310 PCI-X Clock Buffers
4
PS8502
10/10/00
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6C2310 PCI-X Clock Buffers
Packaging Mechanical: 24-pin QSOP (Q)
24
.150 .157
3.81 3.99 .015 x 45 0.38
1 .337 .344 8.56 8.74 .016 .050 .053 .069 1.35 1.75 0.406 1.27 .228 .244 5.79 6.20 .007 .010 0.178 0.254
.033 0.84
SEATING PLANE .004 0.101 .010 0.254
.025 typical 0.635
.008 0.203 .012 0.305
X.XX DENOTES DIMENSIONS X.XX IN MILLIMETERS
Packaging Mechanical: 24-Pin TSSOP (L)
24
.169 .177
4.3 4.5
1
.303 .311 7.7 7.9 .047 1.20 Max
.004 .008 0.45 0.75 SEATING PLANE .018 .030
0.09 0.20
.252 BSC 6.4
.0256 BSC 0.65
.007 .012 0.19 0.30
.002 .006
0.05 0.15
X.XX DENOTES CONTROLLING X.XX DIMENSIONS IN MILLIMETERS
Ordering Information
Orde ring Code PI6C2310Q PI6C2310L Package Name Q 24 L24 Package Type 24- pin, 150- mil QSOP Industrial 24- pin, 4.4- mil TSSOP Ope rating Te mp
Pericom Semiconductor Corporation 2380 Bering Drive * San Jose, CA 95131 * 1-800-435-2336 * Fax (408) 435-1100 * http://www.pericom.com
5
PS8502 10/10/00

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