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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843003I-01
FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
FEATURES
* Three 3.3V LVPECL outputs on two banks, A Bank with one LVPECL pair and B Bank with 2 LVPECL output pairs * Using a 19.53125MHz or 25MHz crystal, the two output banks can be independently set for 625MHz, 312.5MHz, 156.25MHz or 125MHz * Selectable crystal oscillator interface or LVCMOS/LVTTL single-ended input * VCO range: 490MHz to 680MHz * RMS phase jitter @ 156.25MHz (1.875MHz - 20MHz): 0.53ps (typical) * 3.3V output supply mode * -40C to 85C ambient operating temperature
GENERAL DESCRIPTION
The ICS843003I-01 is a 3 differential output LVPECL Synthesizer designed to generate HiPerClockSTM Ethernet reference clock frequencies and is a member of the HiPerClocksTM family of high performance clock solutions from ICS. Using a 19.53125MHz or 25MHz, 18pF parallel resonant crystal, the following frequencies can be generated based on the settings of 4 frequency select pins (DIV_SEL[A1:A0], DIV_SEL[B1:B0]): 625MHz, 312.5MHz, 156.25MHz, and 125MHz. The 843003I-01 has 2 output banks, Bank A with 1 differential LVPECL output pair and Bank B with 2 differential LVPECL output pairs.
ICS
The two banks have their own dedicated frequency select pins and can be independently set for the frequencies mentioned above. The ICS843003I-01 uses ICS' 3rd generation low phase noise VCO technology and can achieve 1ps or lower typical r ms phase jitter, easily meeting Ethernet jitter requirements. The ICS843003I-01 is packaged in a small 24-pin TSSOP package.
PIN ASSIGNMENT
DIV_SELB0 VCO_SEL MR VCCO_A QA0 nQA0 CLK_ENB CLK_ENA FB_DIV VCCA VCC DIV_SELA0 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 DIV_SELB1 VCCO_B QB0 nQB0 QB1 nQB1 XTAL_SEL TEST_CLK XTAL_IN XTAL_OUT VEE DIV_SELA1
BLOCK DIAGRAM
CLK_ENA Pullup DIV_SELA[1:0] VCO_SEL
Pullup Pullup
ICS843003I-01
24-Lead TSSOP 4.40mm x 7.8mm x 0.92mm package body G Package Top View
QA0
TEST_CLK Pulldown
0
0
00 01 10 11
/1 /2 /3 /4 (default)
nQA0
XTAL_IN
OSC
XTAL_OUT XTAL_SEL Pullup
1
Phase Detector
VCO
1
QB0
FB_DIV 0 = /25 (default) 1 = /32
00 01 10 11
/2 /4 /5 /8 (default)
nQB0 QB1 nQB1
FB_DIV Pulldown DIV_SELB[1:0] MR
Pullup Pulldown
CLK_ENB Pullup
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. 843003AGI-01 www.icst.com/products/hiperclocks.html REV. A MAY 26, 2005
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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843003I-01
FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
Type Description Division select pin for Bank B. Default = HIGH. Pullup LVCMOS/LVTTL interface levels. VCO select pin. When Low, the PLL is bypassed and the crystal reference or TEST_CLK (depending on XTAL_SEL setting) are passed directly to the Pullup output dividers. Has an internal pullup resistor so the PLL is not bypassed by default. LVCMOS/LVTTL interface levels. Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs Qx to go low and the inver ted outputs nQx Pulldown to go high. When logic LOW, the internal dividers and the outputs are enabled. Has an internal pulldown resistor so the power-up default state of outputs and dividers are enabled. LVCMOS/LVTTL interface levels. Output supply pin for Bank A outputs. Differential output pair. LVPECL interface levels. Synchronizing clock enable for Bank B outputs. Active High output enable. When logic HIGH, the output pair in Bank B is enabled. When logic LOW, the QB outputs are LOW and nQB outputs are HIGH. Has an internal pullup resistor so the default power-up state of output is enabled. LVCMOS/LVTTL interface levels. See Figure 1. Synchronizing clock enable for Bank A outputs. Active High output enable. When logic HIGH, the output pair in Bank A is enabled. When logic LOW, the QA output is LOW and nQA output is HIGH. Has an internal pullup resistor so the default power-up state of output is enabled. LVCMOS/LVTTL interface levels. See Figure 1. Feedback divide select. When Low (default), the feedback divider is set for /25. When HIGH, the feedback divider is set for /32. LVCMOS/LVTTL interface levels. Analog supply pin.
TABLE 1. PIN DESCRIPTIONS
Number 1 24 2 Name DIV_SELB0 DIV_SELB1 VCO_SEL Input
Input
3
MR
Input
4 5, 6
VCCO_A QA0, nQA0
Power Ouput
7
CLK_ENB
Input
Pullup
8
CLK_ENA
Input
Pullup
9 10 11 12 13 14 15, 16
FB_DIV VCCA VCC DIV_SELA0 DIV_SELA1 VEE XTAL_OUT, XTAL_IN TEST_CLK
Input Power Power Input Power Input
Pulldown
17
Input
18 19, 20 21, 22
XTAL_SEL nQB1, QB1 nQB0, QB0
Input Output Output
Core supply pin. Division select pin for Bank A. Default = HIGH. Pullup LVCMOS/LVTTL interface levels. Negative supply pin. Parallel resonant crystal interface. XTAL_OUT is the output, XTAL_IN is the input. XTAL_IN is also the overdrive pin if you want to overdrive the crystal circuit with a single-ended reference clock. Single-ended reference clock input. Has an internal pulldown resistor to pull Pulldown to low state by default. Can leave floating if using the crystal interface. LVCMOS/LVTTL interface levels. Crystal select pin. Selects between the single-ended TEST_CLK or crystal Pullup interface. Has an internal pullup resistor so the crystal interface is selected by default. LVCMOS/LVTTL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels.
Power Output supply pin for Bank B outputs. 23 VCCO_B NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLDOWN RPULLUP
843003AGI-01
Parameter Input Capacitance Input Pulldown Resistor Input Pullup Resistor
Test Conditions
Minimum
Typical 4 51 51
Maximum
Units pF k k
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REV. A MAY 26, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843003I-01
FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
M/N Multiplication Factor 25 12.5 12.500 8.333 6.25 6.25 6.25 32 16 16 10.667 8 8 8 QA0/nQA0 Output Frequency (MHz) 625 312.5 250 187.5 156.25 150 125 622.08 311.04 250 200 155.52 150 125
TABLE 3A. BANK A FREQUENCY TABLE
Inputs Crystal Frequency (MHz) 25 25 20 22.5 25 24 20 19.44 19.44 15.625 18.75 19.44 18.75 15.625 FB_DIV 0 0 0 0 0 0 0 1 1 1 1 1 1 1 DIV_SELA1 DIV_SELA0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 1 1 0 1 1 1 0 1 1 0 1 1 1 Feedback Divider 25 25 25 25 25 25 25 32 32 32 32 32 32 32 Bank A Output Divider 1 2 2 3 4 4 4 1 2 2 3 4 4 4
TABLE 3B. BANK B FREQUENCY TABLE
Inputs Crystal Frequency (MHz) 25 20 25 24 20 25 25 24 20 19.44 15.625 19.44 18.75 15.625 15.625 19.44 18.75 15.625
843003AGI-01
FB_DIV 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1
DIV_SELB1 0 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 1 1
DIV_SELB0 0 0 1 1 1 0 1 1 1 0 0 1 1 1 0 1 1 1
Feedback Divider 25 25 25 25 25 25 25 25 25 32 32 32 32 32 32 32 32 32
Bank B Output Divider 2 2 4 4 4 5 8 8 8 2 2 4 4 4 5 8 8 8
M/N Multiplication Factor 12.5 12.5 6.25 6.25 6.25 5 3.125 3.125 3.125 16 16 8 8 8 6.4 4 4 4
QB0/nQB0 Output Frequency (MHz) 312.5 250 156.25 150 12 5 125 78.125 75 62.5 311.04 250 155.52 150 12 5 10 0 77.76 75 62.5
REV. A MAY 26, 2005
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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843003I-01
FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
Outputs QA /1 /2 /3 /4 Inputs DIV_SELB1 0 0 1 1 DIV_SELB0 0 1 0 1 Outputs QB /2 /4 /5 /8
TABLE 3C. OUTPUT BANK CONFIGURATION SELECT FUNCTION TABLE
Inputs DIV_SELA1 0 0 1 1 DIV_SELA0 0 1 0 1
TABLE 3D. FEEDBACK DIVIDER CONFIGURATION SELECT FUNCTION TABLE
Inputs FB_DIV 0 1 Feedback Divide /2 5 /32
Disabled
TEST_CLK
Enabled
CLK_ENx
nQA0, nQB0:nQB1 QA0, QB0:QB1
FIGURE 1. CLK_EN TIMING DIAGRAM
TABLE 3E. CLK_ENA SELECT FUNCTION TABLE
Inputs CLK_ENA 0 1 QA0 LOW Active Outputs nQA0 HIGH Active
TABLE 3F. CLK_ENB SELECT FUNCTION TABLE
Inputs CLK_ENB 0 1 LOW Active Outputs QB0:QB1 nQB0:nQB1 HIGH Active
843003AGI-01
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REV. A MAY 26, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843003I-01
FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
4.6V -0.5V to VCC + 0.5V 50mA 100mA 70C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC Inputs, VI Outputs, IO Continuous Current Surge Current Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO_A = VCCO_B = 3.3V5%, TA = -40C TO 85C
Symbol VCC VCCA VCCO_A, B IEE ICCA Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Test Conditions Minimum 3.135 3.135 3.135 Typical 3.3 3.3 3.3 121 15 Maximum 3.465 3.465 3.465 Units V V V mA mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA = VCCO_A = VCCO_B = 3.3V5%, TA = -40C TO 85C
Symbol VIH VIL Parameter Input High Voltage Input Low Voltage Input High Current TEST_CLK, MR, FB_DIV DIV_SELA0, DIV_SELA1, DIV_SELB0, DIV_SELB1, VCO_SEL, XTAL_SEL, CLK_ENA, CLK_ENB TEST_CLK, MR, FB_DIV DIV_SELA0, DIV_SELA1, DIV_SELB0, DIV_SELB1, VCO_SEL, XTAL_SEL, CLK_ENA, CLK_ENB VCC = VIN = 3.465V VCC = VIN = 3.465V VCC = 3.465V, VIN = 0V VCC = 3.465V, VIN = 0V -5 -150 Test Conditions Minimum 2 -0.3 Typical Maximum VCC + 0.3 0.8 150 5 Units V V A A A A
IIH
IIL
Input Low Current
TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = VCCA = VCCO_A = VCCO_B = 3.3V5%, TA = -40C TO 85C
Symbol VOH VOL VSWING Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Peak-to-Peak Output Voltage Swing Test Conditions Minimum VCCO - 1.4 VCCO - 2.0 0.6 Typical Maximum VCCO - 0.9 VCCO - 1.7 1. 0 Units V V V
NOTE 1: Outputs terminated with 50 to VCCO - 2V.
843003AGI-01
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REV. A MAY 26, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843003I-01
FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
Test Conditions Minimum 19.6 15.313 Typical Fundamental 27.2 21.25 50 7 1 MHz MHz pF mW Maximum Units
TABLE 5. CRYSTAL CHARACTERISTICS
Parameter Mode of Oscillation Frequency FB_DIV = /25 FB_DIV = /32
Equivalent Series Resistance (ESR) Shunt Capacitance Drive Level NOTE: Characterized using an 18pF parallel resonant cr ystal.
TABLE 6. AC CHARACTERISTICS, VCC = VCCA = VCCO_A = VCCO_B = 3.3V5%, TA = -40C TO 85C
Symbol Parameter Test Conditions Output Divider = /1 Output Divider = /2 fOUT Output Frequency Range Output Divider = /3 Output Divider = /4 Output Divider = /5 Output Divider = /8 Minimum 490 245 163.33 122.5 98 61.25 TBD Outputs @ Same Frequency Outputs @ Different Frequencies 625MHz (1.875MHz - 20MHz) 312.5MHz (1.875MHz - 20MHz) 156.25MHz (1.875MHz - 20MHz) 125MHz (1.875MHz - 20MHz) t R / tF Output Rise/Fall Time 20% to 80% TBD TBD 0.43 0.51 0.53 0.48 400 Typical Maximum 680 340 226.67 170 136 85 Units MHz MHz MHz MHz MHz MHz ps ps ps ps ps ps ps ps %
tsk(b) tsk(o)
Bank Skew, NOTE 1 Output Skew; NOTE 2, 4
tjit(O)
RMS Phase Jitter (Random); NOTE 3
odc Output Duty Cycle 50 NOTE 1: Defined as skew winthin a bank of outputs at the same voltages and with equal load conditions. NOTE 2: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at the output differential cross points. NOTE 3: Please refer to the Phase Noise Plots. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
843003AGI-01
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REV. A MAY 26, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843003I-01
FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
TYPICAL PHASE NOISE AT 156.25MHZ
NOISE POWER dBc Hz
-10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 1k 10k
10Gb Ethernet Filter 156.25MHz
RMS Phase Jitter (Random) 1.875Mhz to 20MHz = 0.53ps (typical)
0
Raw Phase Noise Data
Phase Noise Result by adding 10Gb Ethernet Filter to raw data
100k 1M 10M 100M
OFFSET FREQUENCY (HZ)
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843003AGI-01
REV. A MAY 26, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843003I-01
FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
PARAMETER MEASUREMENT INFORMATION
2V
Phase Noise Plot
Noise Power
V CC , VCCA, VCCO_A. _B
Qx
SCOPE
LVPECL
nQx
Phase Noise Mask
VEE
f1 Offset Frequency f2
-1.3V0.165V
RMS Jitter = Area Under the Masked Phase Noise Plot
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
RMS PHASE JITTER
nQx Qx nQy Qy
tsk(o)
nQA0, nQB0, nQB1 QA0, QB0, QB1
t PW
t
PERIOD
odc =
t PW t PERIOD
x 100%
OUTPUT SKEW
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
nQB0
80%
QB0 nQB1 QB1
80% VSW I N G
Clock Outputs
20% tR tF
20%
tsk(b)
BANK SKEW
843003AGI-01
OUTPUT RISE/FALL TIME
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REV. A MAY 26, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843003I-01
FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS843003I-01 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC, VCCA, and VCCOx should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 2 illustrates how a 10 resistor along with a 10F and a .01F bypass capacitor should be connected to each VCCA pin.
3.3V VCC .01F VCCA .01F 10F 10
FIGURE 2. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
The ICS843003I-01 has been characterized with 18pF parallel resonant crystals. The capacitor values shown in Figure 3 below were determined using a 19.53125MHz or 25MHz 18pF parallel resonant crystal and were chosen to minimize the ppm error.
XTAL_OUT C1 22p X1 18pF Parallel Crystal XTAL_IN C2 22p
ICS843003I-01
Figure 3. CRYSTAL INPUt INTERFACE
843003AGI-01
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REV. A MAY 26, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843003I-01
FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
designed to drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 4A and 4B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
TERMINATION
FOR
3.3V LVPECL OUTPUT
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are
3.3V
Zo = 50 FOUT FIN
125 Zo = 50 FOUT
50 50 VCC - 2V RTT
125
Zo = 50
FIN
RTT =
1 Z ((VOH + VOL) / (VCC - 2)) - 2 o
Zo = 50 84 84
FIGURE 4A. LVPECL OUTPUT TERMINATION
FIGURE 4B. LVPECL OUTPUT TERMINATION
843003AGI-01
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REV. A MAY 26, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843003I-01
FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER RELIABILITY INFORMATION
TABLE 7. JAVS. AIR FLOW TABLE
FOR
24 LEAD TSSOP
JA by Velocity (Meters per Second)
0
Multi-Layer PCB, JEDEC Standard Test Boards 70C/W
1
65C/W
2.5
62C/W
TRANSISTOR COUNT
The transistor count for ICS843003I-01 is: 3822
843003AGI-01
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REV. A MAY 26, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843003I-01
FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
24 LEAD TSSOP
PACKAGE OUTLINE - G SUFFIX
FOR
TABLE 8. PACKAGE DIMENSIONS
SYMBOL N A A1 A2 b c D E E1 e L aaa 0.45 0 -4.30 0.65 BASIC 0.75 8 0.10 -0.05 0.80 0.19 0.09 7.70 6.40 BASIC 4.50 Millimeters Minimum 24 1.20 0.15 1.05 0.30 0.20 7.90 Maximum
Reference Document: JEDEC Publication 95, MO-153
843003AGI-01
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REV. A MAY 26, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843003I-01
FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
Marking ICS843003AI01 ICS843003AI01 Package 24 Lead TSSOP 24 Lead Shipping Packaging tube 2500 tape & reel Temperature -40C to 85C -40C to 85C
TABLE 9. ORDERING INFORMATION
Part/Order Number ICS843003AGI-01 ICS843003AGI-01T
The aforementioned trademarks, HiPerClockSTM and FemtoClocksTM are a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 843003AGI-01
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