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TECHNICAL DATA SL74LV14 Hex Schmitt-Trigger Inverter The 74LV14 is a low-voltage Si-gate CMOS device and is pin and function compatible with 74HC/HCT14. The 74LV14 provides six inverting buffers with Schmitt-trigger action. * * * * Wide Operating Voltage: 1.0 to 5.5 V Optimized for Low Voltage applications: 1.0 to 3.6 V Accepts TTL input levels between VCC =2.7 V and VCC =3.6 V Low input current ORDERING INFORMATION SL74LV14N Plastic SL74LV14D SOIC SL74LV14 Chip TA = -40 / 125 C for all packages LOGIC DIAGRAM PIN ASSIGNMENT FUNCTION TABLE Input A L H Output Y= A H L PIN 14 =VCC PIN 7 = GND SLS System Logic Semiconductor 1 SL74LV14 MAXIMUM RATINGS * Symbol VCC IIK* 1 IOK* Io* 2 3 Parameter DC supply voltage (Referenced to GND) DC input diode current DC output diode current DC output source or sink current -bus driver outputs DC GND current for types with - bus driver outputs DC VCC current for types with - bus driver outputs Power dissipation per paskade, plastic DIP+ SOIC package+ Storage temperature Lead temperature, 1.5 mm from Case for 10 seconds (Plastic DIP ), 0.3 mm (SOIC Package) Value -0.5 ~ +7.0 20 50 25 50 50 750 500 -65 ~ +150 260 Unit V mA mA mA mA mA mW C C IGND ICC PD Tstg TL * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 12 mW/C from 70 to 125C SOIC Package: : - 8 mW/C from 70 to 125C * 1: VI < -0.5V or VI > VCC+0.5V * 2: Vo < -0.5V or Vo > VCC+0.5V * 3: -0.5V < Vo < VCC+0.5V RECOMMENDED OPERATING CONDITIONS Symbol VCC VIN, VOUT TA tr, t f Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time 1.0 VVCC <2.0 V 2.0 VVCC <2.7 V 2.7 VVCC <3.6 V 3.6 VVCC 5.5 V Min 1.0 0 -40 0 0 0 0 Max 5.5 VCC +125 500 200 100 50 Unit V V C ns This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND(VIN or VOUT)VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V ). CC Unused outputs must be left open. SLS System Logic Semiconductor 2 SL74LV14 DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Symbol VIT+ Parameter Positive-Going Input Threshold Voltage Test Conditions VO VOH VCC V 1.2 2.0 2.7 3.0 3.6 4.5 5.5 1.2 2.0 2.7 3.0 3.6 4.5 5.5 1.2 2.0 2.7 3.0 3.6 4.5 5.5 1.2 2.0 2.7 3.0 3.6 4.5 5.5 3.0 25C min 0.45 0.85 1.05 1.25 1.55 1.75 2.15 0.2 0.35 0.45 0.65 0.85 0.95 1.15 0.2 0.25 0.35 0.45 0.45 0.45 0.65 1.05 1.85 2.55 2.85 3.45 4.35 5.35 2.48 max 0.95 1.35 1.95 2.15 2.35 3.10 3.80 0.65 0.85 1.35 1.45 1.75 1.95 1.15 0.65 0.75 1.05 1.15 1.15 1.35 1.45 Guaranteed Limit -40C / 85C min max 0.4 0.8 1.0 1.2 1.5 1.7 2.1 0.15 0.3 0.4 0.6 0.8 0.9 1.1 0.15 0.3 0.4 0.6 0.8 0.9 1.1 1.0 1.8 2.5 2.8 3.4 4.3 5.3 2.40 1.0 1.4 2.0 2.2 2.4 3.15 3.85 0.7 0.9 1.4 1.5 1.8 2.0 2.26 0.7 0.9 1.4 1.5 1.8 2.0 2.6 -40C / 125C min max 0.4 0.8 1.0 1.2 1.5 1.7 2.1 0.15 0.3 0.4 0.6 0.8 0.9 1.1 0.15 0.3 0.4 0.6 0.8 0.9 1.1 1.0 1.8 2.5 2.8 3.4 4.3 5.3 2.20 1.0 1.4 2.0 2.2 2.4 3.15 3.85 0.7 0.9 1.4 1.5 1.8 2.0 2.26 0.7 0.9 1.4 1.5 1.8 2.0 2.6 Unit V VIT- Negative-Going Input Threshold Voltage VO VOL V VH Hysteresis Voltage VO VOH VO VOL V VOH High-Level Output Voltage VI = VIH -or VIL IO = -100 A V VOH High-Level Output Voltage VI = VIH -or VIL IO = -6.0 mA VI = VIH -or VIL IO = -12.0 mA V 4.5 3.70 - 3.60 - 3.50 - VOL Low-Level Output Voltage VI = VIH -or VIL IO = 100 A 1.2 2.0 2.7 3.0 3.6 4.5 5.5 - 0.15 0.15 0.15 0.15 0.15 0.15 0.15 - 0.2 0.2 0.2 0.2 0.2 0.2 0.2 - 0.2 0.2 0.2 0.2 0.2 0.2 0.2 V SLS System Logic Semiconductor 3 SL74LV14 DC ELECTRICAL CHARACTERISTICS (continuation) Symbol VOL Parameter Low-Level Output Voltage Test Conditions VI = VIH -or IO = 6.0 mA VI = VIH -or VIL IO = 12.0 mA IIL IIH Low-Level Input Leakage Current High-Level Input Leakage Current Quiescent Supply Current (per Package) Additional Quiescent Supply Current on input VI=0 V VI= VNN 5.5 5.5 -0.1 0.1 -1.0 1.0 -1.0 1.0 A VCC V 3.0 4.5 25C min max 0.33 0.40 Guaranteed Limit -40C / 85C min max 0.40 0.55 -40C / 125C min max 0.50 0.65 Unit V ICC VI=0 A or VNN IO = 0 A VI = VNN 0.6V IO = 0 A 5.5 - 4.0 - 20 - 40 A ICC1 2.7 3.6 - 0.2 - 0.5 - 0.85 mA . SLS System Logic Semiconductor 4 SL74LV14 AC ELECTRICAL CHARACTERISTICS (CL=50 pF, t LH =t HL = 2.5 ns, RL=1 kU) Symbol tPLH, t PHL Parameter Propagation Delay, Input A to Output Y (Figure 1 ) Test Conditions VI=0 V or V1 tLH = tHL =2.5 ns N L = 50 pF RL = 1 kU VCC V 1.2 2.0 2.7 3.0 4.5 5.5 VI=0 V or VNN 5.5 25C min max 150 28 22 17 14 7.0 30 Guaranteed Limit -40C / 85C min max 170 37 28 22 18 7.0 30 -40C / 125C min max 200 48 35 28 23 7.0 30 Unit ns CI CPD Input Capacitance pF pF tH L 0.9 VX tL H 0.9 VX V1 0.1 Input A 0.1 tP H L tP L H GND V OH Output Y VY VY VO L VX=0.5 VCC Figure 1. Switching Waveforms VC C VI PULSE GENERATOR RT DEVICE UNDER TEST VO Termination resistance RT - should be equal to ZOUT of pulse generators CL RL Figure 2. Test Circuit SLS System Logic Semiconductor 5 SL74LV14 CHIP PAD DIAGRAM SL74LV14 1.33 0.03 13 12 11 10 09 1.42 0.03 14 08 07 01 02 03 04 05 06 Chip marking IN74LV14 (x=0.130; y=0.130) Pad size 0.108 x 0.108 mm (Pad size is given as per metallization layer) Thickness of chip 0.46 0,02 mm PAD LOCATION Pad No 01 02 03 04 05 06 07 08 09 10 11 12 13 14 Symbol A1 Y1 A2 Y2 A3 Y3 GND Y4 A4 Y5 A5 Y6 A6 VCC X 0.130 0.130 0.381 0.616 0.881 1.116 1.115 1.115 1.115 0.804 0.569 0.378 0.143 0.130 Y 0.463 0.230 0.126 0.126 0.126 0.126 0.631 0.846 1.181 1.194 1.194 1.194 1.194 0.813 SLS System Logic Semiconductor 6 |
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