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| For:char Printed on:Mon, Feb 6, 1995 09:32:08 From book:DL121CH4 (5) VIEW Document:MC74F283 (5) VIEW Last saved on:Fri, Feb 3, 1995 16:03:54 MC54/74F283 4-BIT BINARY FULL ADDER (With Fast Carry) The MC54/74F283 high-speed 4-bit binary full adder with internal carry lookahead, accepts two 4-bit binary words (A0-A3, B0-B3) and a Carry input (C0). It generates the binary Sum outputs (S0-S3) and the Carry output (C4) from the most significant bit. The F283 will operate with either active-HIGH or active-LOW operands (positive or negative logic). 4-BIT BINARY FULL ADDER (With Fast Carry) FASTTM SCHOTTKY TTL FUNCTIONAL DESCRIPTION The F283 adds two 4-bit binary words (A plus B) plus the incoming carry C0. The binary sum appears on the Sum (S0-S3) and outgoing carry (C4) outputs. The binary weight of the various inputs and outputs is indicated by the subscript numbers, representing powers of two. 20 (A0 + B0 + C0) + 21 (A1 + B1) + 22 (A2 + B2) + 23 (A3 + B3) = S0 + 2S1 + 4S2 + 8S3 + 16C4 Where (+) = plus Interchanging inputs of equal weight does not affect the operation.Thus C0, A0, B0 can be arbitrarily assigned to pins 5, 6 and 7. Due to the symmetry of the binary add function, the F283 can be used either with all inputs and outputs active HIGH (positive logic) or with all inputs and outputs active LOW (negative logic). See Figure A. Note that if C0 is not used it must be tied LOW for active-HIGH logic or tied HIGH for active-LOW logic. Due to pin limitations, the intermediate carries of the F283 are not brought out for use as inputs or outputs. However, other means can be used to effectively insert a carry into, or bring a carry out from, an intermediate stage. Figure B shows how to make a 3-bit adder. Tying the operand inputs of the fourth adder (A3, B3) LOW makes S3 dependent only on, and equal to, the carry from the third adder. Using somewhat the same principle, Figure C shows a way of dividing the F283 into a 2-bit and a 1-bit adder. The third stage adder (A2, B2, S2) is used merely as a means of getting a carry (C10) signal into the fourth stage (via A2 and B2) and bringing out the carry from the second stage on S2. Note that as long as A2 and B2 are the same, whether HIGH or LOW, they do not influence S2. Similarly, when A2 and B2 are the same the carry into the third stage does not influence the carry out of the third stage. Figure D shows a method of implementing a 5-input encoder, where the inputs are equally weighted. The outputs S0, S1 and S2 present a binary number equal to the number of inputs I1-I5 that are true. Figure E shows one method of implementing a 5-input majority gate. When three or more of the inputs I1-I5 are true, the output M5 is true. CONNECTION DIAGRAM VCC 16 B2 15 A2 14 S2 13 A3 12 B3 11 S3 10 C4 9 13 10 S2 S3 C4 9 J SUFFIX CERAMIC CASE 620-09 16 1 16 1 N SUFFIX PLASTIC CASE 648-08 16 1 D SUFFIX SOIC CASE 751B-03 ORDERING INFORMATION MC54FXXXJ MC74FXXXN MC74FXXXD Ceramic Plastic SOIC LOGIC SYMBOL 7 C0 4 1 S0 S1 A0 B0 A1 B1 A2 B2 A3 B3 5 6 3 2 14 15 12 11 VCC = PIN 16 GND = PIN 8 1 S1 2 B1 3 A1 4 S0 5 A0 6 B0 7 C0 8 GND FAST AND LS TTL DATA 4-146 MC54/74F283 LOGIC DIAGRAM C0 A0 B0 A1 B1 A2 B2 A3 B3 S0 S1 S2 S3 C4 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range 74 Output Current -- High Output Current -- Low 54, 74 54, 74 0 -- -- 25 -- -- 70 -1.0 20 Parameter 54, 74 54 Min 4.5 - 55 Typ 5.0 25 Max 5.5 125 Unit V C mA mA Figure A. Active-HIGH versus Active-LOW Interpretation C0 Logic Levels Active HIGH Active LOW L 0 1 A0 L 0 1 A1 H 1 0 A2 L 0 1 A3 H 1 0 B0 H 1 0 B1 L 0 1 B2 L 0 1 B3 H 1 0 S0 H 1 0 S1 H 1 0 S2 L 0 1 S3 L 0 1 C4 H 1 0 Active HIGH: 0 + 10 + 9 = 3 + 16 Active LOW: 1 + 5 + 6 = 12 + 0 FAST AND LS TTL DATA 4-147 MC54/74F283 C10 L A0 B0 A1 B1 A2 B2 A3 B3 C0 S0 S1 S2 S3 C3 C4 C0 A0 B0 A1 B1 A0 B0 A1 B1 C0 S0 S0 S1 S1 S2 C2 S3 S10 A10 B10 A2 B2 A3 B3 C4 C11 Figure B. 3-Bit Adder Figure C. 2-Bit and 1-Bit Adders I3 I3 I1 I2 L I4 I5 A0 B0 A1 B1 A2 B2 A3 B3 A0 B0 A1 B1 A2 B2 A3 B3 C0 S0 20 S1 21 S2 22 S3 C4 C0 S0 S1 S2 S3 C4 I1 I2 I4 I5 M5 Figure D. 5-Input Encoder Figure E. 5-Input Majority Gate DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH VOL IIH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage 54, 74 Output HIGH Voltage 74 Output LOW Voltage Input HIGH Current 100 Input LOW Current C0 Input A and B Inputs IOS ICC Output Short Circuit Current (Note 2) Power Supply Current - 60 36 - 0.6 -1.2 -150 55 2.7 3.4 0.35 0.5 20 V V A A mA mA mA mA VOUT = 0 V Inputs = 4.5 V VCC = MAX VCC = MAX 2.5 3.4 Min 2.0 0.8 -1.2 Typ Max Unit V V V V Test Conditions Guaranteed Input HIGH Voltage Guaranteed Input LOW Voltage IIN = -18 mA IOH = -1.0 mA IOH = -1.0 mA IOL = 20 mA VIN = 2.7 V VIN = 7.0 V VIN = 0.5 V VCC = MIN VCC = 4.5 V VCC = 4.75 V VCC = MIN VCC = MAX IIL VCC = MAX NOTES: 1. For conditions such as MIN or MAX, use the appropriate value specified under guaranteed operating ranges. 2. Not more than one output should be shorted at a time, nor for more than 1 second. FAST AND LS TTL DATA 4-148 MC54/74F283 AC CHARACTERISTICS 54/74F TA = +25C VCC = +5.0 V CL = 50 pF Symbol tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL Parameter Propagation Delay C0 to Sn Propagation Delay An or Bn to Sn Propagation Delay C0 to C4 Propagation An or Bn to C4 Min 3.5 4.0 3.0 3.5 3.5 3.0 3.0 3.0 Typ 7.0 7.0 7.0 7.0 5.7 5.4 5.7 5.3 Max 9.5 9.5 9.5 9.5 7.5 7.0 7.5 7.0 54F TA = -55 to +125C VCC = 5.0 V 10% CL = 50 pF Min 3.5 4.0 3.0 3.5 3.5 3.0 3.0 3.0 Max 14 14 14 14 10.5 10 10.5 10 74F TA = 0 to +70C VCC = 5.0 V 10% CL = 50 pF Min 3.5 4.0 3.0 3.5 3.5 3.0 3.0 3.0 Max 10.5 10.5 10.5 10.5 8.5 8.0 8.5 8.0 Unit ns ns ns ns FAST AND LS TTL DATA 4-149 |
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