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| Using Terminator Technology in Stratix & Stratix GX Devices November 2002, ver. 2.0 Application Note 209 Introduction Signal integrity is crucial in high-speed digital designs because of increased system speeds and clock edge rates. Designers must properly terminate single-ended and differential signals to achieve signal integrity. Traditionally, designers use on-board termination resistors to achieve proper signal termination. However, these resistors take up significant board space and can cause signal reflections (stub effects). These reflections normally occur when a termination resistor is too far away from the transmission line it terminates. TerminatorTM technology in StratixTM and Stratix GX devices helps prevent reflections, improving signal integrity. To address these issues, Stratix and Stratix GX devices have driver impedance matching and onchip termination circuitry. Terminator technology includes series termination, impedance matching, parallel termination for single-ended I/O standards (e.g., HSTL and SSTL-2), and differential termination. Termination resistors are adjacent to the buffers on the device, thereby eliminating stub effects. Terminator technology minimizes the need for a cumbersome external resistor network, thereby easing board routing and saving board space. Figure 1 shows a footprint comparison of a device with external termination and with Terminator technology. This application note covers various Terminator technology types supported by Stratix and Stratix GX devices as well as power management. Figure 1. Device Footprint Comparison with & without Terminator Technology Termination Resistors With External Termination With Terminator Technology Reference Resistors Altera Corporation AN-209-2.0 1 AN 209: Using Terminator Technology in Stratix & Stratix GX Devices How Terminator Technology Works Two external precision resistors (RUP and RDN ) per VCCIO bank are used as reference resistors. RUP is a pull-up resistor connected to VCCIO; RDN is a pull-down resistor connected to GND. Terminator technology monitors the value of the two reference resistors and uses the value to adjust internal termination circuitry to the same impedance. In addition, Terminator technology circuitry compensates for voltage, temperature, and process variation. This circuitry continuously calibrates the internal termination resistors during normal device operation. Terminator technology supports one type of I/O standard per I/O bank. You can enable or disable on-chip termination within an I/O bank on a pin-by-pin basis. To use different on-chip termination I/O standards on a device, select separate I/O banks. For example, if you want to use on-chip termination for GTL+ (3.3-V VCCIO ) and SSTL-3 class II (3.3-V VCCIO ), use two separate I/O banks. Different I/O standards need different VCCIO and VREF voltages. You can simultaneously use some I/O standards with the same VCCIO in an I/O bank. For more information, refer to AN 201: Using Selectable I/O Standards in Stratix Devices. Series Termination Resistor (RS) Terminator technology provides an on-chip series termination resistor (RS) for single-ended voltage-referenced I/O standard such as SSTL-2 and SSTL-3. The series termination value for these I/O standards is 25 ; the impedance matching value for these I/O standards is either 25 or 50 . All I/O pins in Stratix and Stratix GX devices support this termination method. Table 1 shows the I/O standards supported for series termination and impedance matching. Table 1. Supported I/O Standards for Series Termination & Impedance Matching Feature Series Termination Supported I/O Standards SSTL-3 class I SSTL-3 class II SSTL-2 class I SSTL-2 class II VCCIO (V) 3.3 3.3 2.5 2.5 3.3 2.5 1.8 Impedance Matching LVTTL/LVCMOS LVTTL/LVCMOS LVTTL/LVCMOS 2 Altera Corporation AN 209: Using Terminator Technology in Stratix & Stratix GX Devices Impedance Matching The impedance of the output driver is matched with the transmission line impedance. Stratix and Stratix GX output buffers can match output impedance to either 25 or 50 . This impedance matching results in properly terminated signals, improving signal integrity. This feature is supported by all Stratix device I/O pins. 1 When using impedance matching for an output buffer, variable drive current strength and slow-slew rate features are not available. Figure 2 shows the on-chip impedance matching resistor for an output driver. Figure 2. Driver Impedance Matching Impedance Matched Driver (LVTTL, LVCMOS) VCCIO = 1.8, 2.5, or 3.3 V Rs Z0 Receiving Buffer (LVTTL, LVCMOS) Parallel Termination (RT) Terminator technology supports on-chip parallel termination for several voltage-referenced I/O standards. To maintain signal integrity and save board space, use Terminator technology resistors instead of external pullup termination resistors. Parallel termination is supported for SSTL-2, SSTL-3, HSTL (class I and II), GTL, GTL+, and CTT I/O standards. All the I/O pins in the top and bottom I/O banks support parallel termination. Figure 3 shows the parallel termination connections for a Stratix device. Altera Corporation 3 AN 209: Using Terminator Technology in Stratix & Stratix GX Devices Figure 3. Terminator Technology Parallel Termination Driver with Parallel Termination VTT Receiver with Terminator Technology Parallel Termination VTT R T1 Z0 R T2 VREF Table 2 shows the supported I/O standards for parallel termination in Stratix and Stratix GX devices. Table 2. Supported I/O Standards for Parallel Termination Supported I/O Standards SSTL-3 class I SSTL-3 class II (1) SSTL-2 class I SSTL-2 class II (1) HSTL class I HSTL class II GTL GTL+ CTT Note to Table 2: (1) In addition to parallel termination, SSTL-3 and SSTL-2 class II I/O standards require a series termination next to the output buffer. If you are using these I/O standards for the output pins, Altera recommends using the on-chip series termination and an external pull-up resistor to VTT for parallel termination. Figure 4 shows the connection scheme for these particular I/O standards. Parallel Termination (RT1) N/A 50 N/A 50 N/A 50 50 50 N/A Parallel Termination (RT2) 50 50 50 50 50 50 50 50 50 VCCIO (V) 3.3 3.3 2.5 2.5 1.5 1.5 3.3 3.3 3.3 4 Altera Corporation AN 209: Using Terminator Technology in Stratix & Stratix GX Devices Figure 4. Terminator Technology Series-Parallel Termination Driver with Series Termination External Resistor Provided by User VTT Receiver with Terminator Technology Parallel Termination VTT R R S T1 Z0 R T2 VREF Differential Termination (RD) Terminator technology supports on-chip differential termination for source-synchronous LVDS signalling. The differential termination resistors are adjacent to the differential input buffers on the device. This placement eliminates stub effects, improving the signal integrity of the serial link. Using on-chip differential termination resistors also saves board space. Figure 5 shows the differential termination connections for Stratix and Stratix GX devices. Figure 5. Terminator Technology Differential Termination Differential Transmitter Differential Receiver with Terminator Technology LVDS Termination Z0 RD Z0 Differential termination for Stratix devices is supported for the left and right I/O banks. Differential termination for Stratix GX devices is supported for the left, source-synchronous I/O bank. Some of the clock input pins are in the top and bottom I/O banks, which do not support differential termination. External reference resistors are not required for I/O banks that support differential termination. The value of on-chip differential termination resistors is 100 . Altera Corporation 5 AN 209: Using Terminator Technology in Stratix & Stratix GX Devices Transceiver Termination f Reference Resistors Stratix GX devices feature built-in on-chip termination within the transceiver at both the transmit and receive buffers. This termination improves signal integrity and provides support for the 1.5-V PCML I/O standard. See AN 237: Using High-Speed Transceiver Blocks in Stratix GX Devices for more information on transceiver termination. Connect the two reference resistors (RUP and RDN ) to the two dualpurpose reference pins per I/O bank. RUP is a pull-up resistor and is connected to the VCCIO of that I/O bank. RDN is a pull-down resistor and is connected to GND of that I/O bank. Figure 6 below shows the reference resistor connections. Figure 6. Terminator Reference Resistor Connections VCCIO R UP Device R DN GND Table 3 shows the external reference resistor values for different types of terminations. Table 3. External Reference Resistance Values Termination Type Impedance Matching Series Termination Parallel Termination Differential Termination Note to Table 3: (1) Z0 is the target on-chip impedance. Note (1) RUP/RDN 10 x Z0 10 x Z0 10 x Z0 20 x Z0 Not needed Impedance () 25 50 25 50 100 6 Altera Corporation AN 209: Using Terminator Technology in Stratix & Stratix GX Devices Power Analysis Terminator technology on-chip termination resistors increase the total current draw of the device. This increase in current draw occurs because the termination circuitry, which is normally external to the device, is now a part of the device. Make sure the device's current consumption in a design does not exceed any device limits. You must ensure that no more than 200 mA (Flip Chip packages) is consumed for any ten consecutive I/O pins (excluding VCC and GND pins). The Altera(R) Quartus(R) II software automatically performs these calculations during compilation. If the pin assignments do not comply with these conditions, the Quartus II software generates an error message during design compilation. Table 4 lists the DC current draw when using on-chip series termination for single-ended I/O standards. Table 4. DC Current Draw for On-Chip Series Termination Bank I/O Standard Selected by Terminator Technology DC Current Draw per Pin for Series Termination (Ipin in mA) (1) 0 0 10 23 11 24 VCCIO (V) LVTTL LVCMOS SSTL-2 class I SSTL-2 class II SSTL-3 class I SSTL-3 class II Note to Table 4: (1) Ipin is the DC current drawn per pin. 1.8, 2.5, 3.3 1.8, 2.5, 3.3 2.5 2.5 3.3 3.3 Altera Corporation 7 AN 209: Using Terminator Technology in Stratix & Stratix GX Devices Table 5 lists the DC current draw when using Terminator technology onchip parallel termination resistors for single-ended inputs or outputs. Table 5. DC Current Draw for On-Chip Series-Parallel Termination (Input & Output Pins) Bank I/O Standard Selected by Terminator Technology DC Current Draw per Pin for Series & Parallel Termination (Ipin in mA) (2) Output Mode RS GTL GTL+ SSTL-2 class I SSTL-2 class II SSTL-3 class I SSTL-3 class II CTT HSTL class I HSTL class II Notes to Table 5: (1) (2) (3) There are no current limitations for 1.8-V I/O standards (thermally-enhanced ball-grid array (BGA) cavity-up packages). Ipin is the DC current drawn per pin. RT1 and RT2 are the parallel termination resistors for the voltage-referenced I/O standards. RT1is the parallel termination resistor next to the output buffer and RT2 is the parallel termination resistor next to the input buffer. See Figure 3. The CTT output buffer and HSTL Class I output buffer do not draw any current due to the on-chip termination resistor for single-ended I/O pins, but they will still draw 8 mA as specified in the corresponding JEDEC specifications. Note (1) VCCIO (V) Input Mode RT1 (3) 40 34 N/A N/A N/A N/A RT2 (3) 15 14 12 12 15 17 18 9 10 3.3 3.3 2.5 2.5 3.3 3.3 3.3 1.5 1.5 N/A N/A 10 23 11 24 N/A N/A N/A N/A (4) N/A (4) 20 (4) 8 Altera Corporation AN 209: Using Terminator Technology in Stratix & Stratix GX Devices When using bidirectional pins, the total DC current draw by Terminator technology on-chip termination resistors is different than the values listed in Table 5. Table 6 lists the DC current draw values for bidirectional pins. Table 6. DC Current Draw for On-Chip Series-Parallel Termination (Bidirectional Pins) Bank I/O Standard Selected by Terminator Technology GTL GTL+ SSTL-3 class I SSTL-3 class II SSTL-2 class I SSTL-2 class II CTT HSTL class I HSTL class II Notes to Table 6: (1) (2) (3) (4) There are no current limitations for 1.5- and 1.8-V VCCIO I/O standards. Ipin is the DC current drawn per pin. RT1 and RT2 are the parallel termination resistors for the voltage referenced I/O standards. RT1 is the parallel termination resistor next to output buffer and RT2 is the parallel termination resistor next to input buffer. The CTT output buffer and HSTL class I output buffer do not draw any current due to the on-chip termination resistor for single-ended I/O pins, but they will still draw 8 mA as specified in the corresponding JEDEC specifications. Note (1) VCCIO (V) DC Current Draw per Pin for Series & Parallel Termination (Ipin in mA) (2) RS N/A N/A 11 24 10 23 N/A N/A N/A RT1 (3) 40 34 N/A N/A N/A N/A N/A (4) N/A (4) 20 RT2 (3) 40 34 25 37 19 25 27 16 20 3.3 3.3 3.3 3.3 2.5 2.5 3.3 1.5 1.5 Altera Corporation 9 AN 209: Using Terminator Technology in Stratix & Stratix GX Devices When you enable Terminator technology for an I/O bank, the external reference resistors for that bank are activated. When enabled, these reference resistors also draw a finite amount of current. The current consumption of these resistors for different I/O standards is shown in the Table 7. Table 7. RUP & RDN Current Consumption Bank I/O Standard Selected by Terminator Technology Note (1) VCCIO (V) RUP & RDN Current Consumption per I/O Bank (Iref in mA) (2) Series Termination 16 10 9 12 15 19 N/A N/A N/A N/A N/A Parallel Termination N/A N/A 13 14 22 26 5 5 17 17 24 3.3 2.5 2.5 2.5 3.3 3.3 1.5 1.5 3.3 3.3 3.3 LVTTL/LVCMOS (3) LVTTL/LVCMOS (3) SSTL-2 class I SSTL-2 class II SSTL-3 class I SSTL-3 class II HSTL class I HSTL class II GTL GTL+ CTT Notes to Table 7: (1) (2) (3) There are no current restrictions for the HSTL class I and class II I/O standards (thermally-enhanced BGA cavity-up packages). Iref is the current drawn by the Terminator technology control circuitry, including the external reference resistors RUP and RDN, per I/O bank. These values are the same whether you are using 250- or 500- reference resistors. Dual-purpose pins for connecting external reference resistors are also included while counting ten consecutive I/O pins. When using Terminator technology, Figure 7 shows a Stratix or Stratix GX device's current draw limitation guidelines. f For complete details on the current draw limits or any other limitations for different I/O standards, refer to AN 201: Using Selectable I/O Standards in Stratix Devices. 10 Altera Corporation AN 209: Using Terminator Technology in Stratix & Stratix GX Devices Figure 7. Current Draw Limitation Guidelines Using Terminator Technology I/O Pin Sequence of an I/O Bank VCC Any 10 Consecutive I/O Pins, Excluding either RUP or RDN or Both GND VCC R UP R DN Any 10 Consecutive I/O Pins, Including either RUP or RDN or Both GND VCC If the ten consecutive I/O pins exclude either RUP or RDN or both pins, the current draw limitations in thermally enhanced BGA packages cannot exceed 200 mA. Consult Altera Applications for current draw limit for all other packages. Altera Corporation 11 AN 209: Using Terminator Technology in Stratix & Stratix GX Devices For example, consider a case where the ten consecutive pins are configured as follows (only seven of the ten pins are used in this example): Number of SSTL-3 Class I output pins with Terminator technology = 3 Number of GTL+ output pins without Terminator technology = 4 In this case, the total current draw for these ten consecutive I/O pins would be (see Tables 5 and 6 for values): (# of SSTL-3 Class I pins with Terminator technology x 11 mA) + (# of GTL+ output pins x 34 mA) = (3 x 11 mA) + (4 x 34 mA) = 169 mA In the above example, the total current draw for all ten consecutive I/O pins is less than 200 mA. If the ten consecutive I/O pins also include either RUP or RDN or both pins, the current draw limitation for Stratix devices should be less than (200 mA - Iref), where Iref is the current drawn by either RUP or RDN or both. For example, consider another case where the ten consecutive pins are configured as follows (nine of the ten pins are used in this example): Number of SSTL-3 Class II output pins with Terminator technology = 8 Number of external reference resistor pins (RUP and RDN) = 1 In this case, the sum total of current draw for these ten consecutive I/O pins would be (see Tables 4 and 7 for values): (# of SSTL-3 Class II output pins with Terminator technology x 25 mA) + (total current due to the Terminator technology, including external reference resistor pins RUP and RDN) = (8 x 24 mA) + (26 mA) = 218 mA In the above example, the total current draw for all ten consecutive I/O pins is more than 200 mA. Therefore, this case is not allowed and the Quartus II software generates an error message during design compilation. 12 Altera Corporation AN 209: Using Terminator Technology in Stratix & Stratix GX Devices Design Tips The following is a list of design tips: Parallel termination is supported only on the top and bottom I/O banks. Series termination and impedance matching is supported on all the I/O banks. Differential termination is supported only on the left and right I/O banks in Stratix devices and on the left I/O bank in Stratix GX devices. Transceiver termination is supported in the Stratix GX transceiver. Terminator technology supports one type of on-chip termination I/O standard for a given I/O bank. Some features, such as LVTTL variable drive strength and slow slew rate control, cannot be used when impedance matching is enabled. Each I/O bank has two dual-purpose reference pins to which two external reference resistors need to be connected when using Terminator technology. Each I/O pin can either support series or parallel termination. In the case of SSTL-2 class II and SSTL-3 class II output pins, Altera recommends using on-chip series termination and parallel external pull-up resistors. There are no current draw limitations for 1.8-V VCCIO levels (thermally-enhanced BGA cavity up packages). Total current draw of ten consecutive I/O pins, including two dualpurpose pins for external reference resistors within these ten I/O pins, should not exceed 200 mA (thermally-enhanced BGA cavity up packages). Conclusion Increasing clock speeds and faster edge rates have made board design challenging. Designers must ensure that signal traces on the board are properly terminated to maintain signal integrity. Altera's Stratix and Stratix GX device families with Terminator technology offers impedance matching and on-chip termination resistors for single-ended and differential I/O standards. Terminator technology enables designers to meet signal integrity requirements while simplifying board design, saving time and resources. The information contained in AN 209: Using Terminator Technology in Stratix & Stratix GX Devices version 2.0 supersedes information published in previous versions. The following changes were made in AN 209: Using Terminator Technology in Stratix & Stratix GX Devices version 2.0 Revision History Added Stratix GX devices throughout the document. Added Note (1) to Table 3. Added Note (3) to Table 7. Altera Corporation 13 AN 209: Using Terminator Technology in Stratix & Stratix GX Devices 101 Innovation Drive San Jose, CA 95134 (408) 544-7000 http://www.altera.com Applications Hotline: (800) 800-EPLD Literature Services: lit_req@altera.com 14 Copyright (c) 2002 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. Altera Corporation |
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