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12-Channel Gamma Buffers with VCOM and Regulator ADD8707
FEATURES
12 precision gamma reference outputs Mask-programmable gamma resistors: 0.2% resolution and 0.1% accuracy Mask programmable voltage regulator: 0.4% accuracy Upper 6 buffers swing to VDD Lower 6 buffers swing to GND Single-supply operation: 7.5 V to 16 V Gamma current drive: 15 mA per channel VCOM peak output current: 250 mA Outputs stable under load conditions 48-lead, Pb-free LFCSP package
FUNCTIONAL BLOCK DIAGRAM
VREG OUT
MASK-PROGRAMMABLE REGULATOR RESISTORS
FB
700* VCOM GND + - GAMMA BUFFERS VOUT12 700* VIN11 VCOM OUT
1.2V
VCOM IN+
VCOM IN-
VOUT11 VOUT10 MASKPROGRAMMABLE GAMMA RESISTORS VOUT9 VOUT8 VOUT7 VOUT6 VOUT5 VOUT4
APPLICATIONS
LCD TV panels LCD monitor panels
VIN10
700*
VIN8
700*
PRODUCT OVERVIEW
The ADD8707 is a 12-channel integrated gamma reference with VCOM for use in LCD TV and monitor panels. The output buffers feature high current drive and low offset voltage to provide an accurate and stable gamma curve. The top six channels swing to VDD and the lower six channels swing to GND. Integrating the gamma setup resistors drastically reduces the external component count while increasing the gamma curve accuracy. To accommodate multiple column drivers and panel architectures, the ADD8707 is mask-programmable to a 0.2% resolution using the on-chip 500 resistor string. An on-board voltage regulator provides a fixed input for the resistor string, isolating the gamma curve from supply ripple. The ADD8707 is specified over the temperature range of -40C to +105C and comes in a 48-lead, Pb-free, lead frame chip-scale package.
VIN7 VIN6 VIN5
700*
700*
700*
700* VIN3 VIN2 VIN1 700*
VOUT3 VOUT2 VOUT1
04712-001
700*
*ESD PROTECTION RESISTORS
Figure 1. 48-Lead LFCSP
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 (c) 2004 Analog Devices, Inc. All rights reserved.
ADD8707
TABLE OF CONTENTS
Electrical Characteristics ................................................................. 3 Absolute Maximum Ratings............................................................ 5 Pin Configuration and Function Description .............................. 6 Typical Performance Characteristics ............................................. 8 Application Notes ........................................................................... 12 Tap Point Selection..................................................................... 12 Voltage Regulator ....................................................................... 13 Maximum Power Dissipation ................................................... 13 Land Pattern................................................................................ 13 Operating Temperature Range ................................................. 14 Typical Applications Circuit.......................................................... 16 Development Circuit...................................................................... 17 Tap Point and Regulator Voltage Request Form......................... 19 Regulator Section--VREG OUT...................................................... 19 Tap Point Section........................................................................ 19 Outline Dimensions ....................................................................... 20 Ordering Guide........................................................................... 20
REVISION HISTORY
10/04--Data Sheet Changed from Rev. 0 to Rev. A Changes to Product Overview Section .......................................... 1 Changes to Figure 1.......................................................................... 1 Changes to Electrical Characteristics Section .............................. 3 Changes to Absolute Maximum Ratings Section......................... 5 Changes to Pin Configuration and Function Description.......... 6 Changes to Typical Performance Characteristics Section........... 8 Changes to Applications Notes Section ....................................... 12 Changes to Figure 28, Typical Applications Circuit................... 16 Added Development Circuit Section ........................................... 17 Added Tap Point and Regulator Voltage Request Form............ 19 Changes to Ordering Guide .......................................................... 20 7/04--Revision 0: Initial Version
Rev. A | Page 2 of 20
ADD8707 ELECTRICAL CHARACTERISTICS
VDD = 16 V, TA @ +25oC, unless otherwise noted. Table 1.
Parameter GAMMA CURVE CHARACTERISTICS Accuracy Programming Resolution Total Resistor String Value BUFFER CHARACTERISTICS OUTPUTS Output Voltage Range (Ch12 to Ch7) Output Voltage Range (Ch6 to Ch1) Output vs. Load (Ch12, Ch11, Ch2, Ch1) Output vs. Load (Ch10 to Ch3) INPUTS Offset Voltage Offset Voltage Drift Input Bias Current Input Voltage Range (Ch12 to Ch7) Input Voltage Range (Ch6 to Ch1) VCOM CHARACTERISTICS Offset Voltage Input Range Peak Output Current Continuous Output Current Output vs. Load BUFFER AND VCOM DYNAMIC PERFORMANCE Slew Rate Bandwidth Settling Time to 0.1% Phase Margin Power Supply Rejection Ratio VOLTAGE REGULATOR Programmable Range Initial Regulator Accuracy Dropout Voltage Line Regulation Load Regulation Maximum Load Current Feedback Reference Voltage Feedback Input Bias Current Symbol RACC1 RRES RTOTAL Condition Min Typ 0.1 0.2 15 Max 0.4 Unit % % k
500 segments
VOUT VOUT VOUT2 VOUT2 VOS VOS/T IB VIN VIN VOS VIN IPK IOUT VCOM2 SR BW
IL = 100 A IL = 100 A IL = 20 mA IL = 5 mA
1.4 0 15 5 5 20 0.5 1.4 0 5 1.4 250 50 10 4 6 4.5 1.1 55 90
VDD VDD - 1.4
V V mV mV mV V/C A V V mV V mA mA mV V/s MHz s Degrees dB
15 1.5 VDD VDD - 1.4 15 VDD - 1.4
-40C TA +105C -40C TA +105C
IL = 30 mA RL = 10 k, CL = 200 pF -3dB, RL = 10 k, CL = 200 pF 1V step, RL = 10 k, CL = 200 pF RL = 10 k, CL = 200 pF VDD = 7 V to 17 V, -40C TA +105C
tS
o PSRR VREG OUT VACC VDO REGLINE REGLOAD IO VREF IB FB
68 5
No Load. VREG OUT = 14.4V IL = 100 A IL = 5 mA VIN = 8.5 V to 16.5 V, VOUT = 8V IO = 100 A to 5 mA -40C TA +105C -40C TA +105C
0.4 100 310 0.01 0.02 5 -150 1.2 10
VDD - 0.6 1.5 150 350 0.20 0.10
150
V % mV mV %/V %/mA mA V nA
Rev. A | Page 3 of 20
ADD8707
Parameter SYSTEM ACCURACY Total Error3, 4 POWER SUPPLY Supply Voltage Supply Current Symbol VTOTAL ERROR VDD ISY Condition -40C TA +105C 7.5 No load, -40C TA +105C 8.3 Min Typ 10 0.5 Max 3 16 15 Unit % V mA
1 2
Gamma curve accuracy includes resistor matching and buffer errors, but excludes the regulator error. VCOM is the shift from the desired output voltage under the specified current load. 3 Total error is defined as the difference between the designed and actual output voltage divided by the actual regulator output voltage or full-scale voltage. 4 Total error includes regulator error, resistor string error, bias current effects, and buffer offset voltage.
Rev. A | Page 4 of 20
ADD8707 ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Supply Voltage (VDD) Input Voltage Storage Temperature Range Operating Temperature Range1 Lead Temperature Range (Soldering 10 sec) Junction Temperature ESD Tolerance (HBM) ESD Tolerance (MM) Rating 18 V -0.5 V to VDD -65C to +150C -40C to +105C 300C 150C 3000 V 100 V
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Table 3. Thermal Resistance
Package Type 48-Lead LFCSP (CP) JA2 28.3 JA3 47.7 Unit C/W
1 2
See the Applications Information section. JA for exposed pad soldered to JEDEC 4-layer board. 3 JA for exposed pad not soldered down.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. A | Page 5 of 20
ADD8707 PIN CONFIGURATION AND FUNCTION DESCRIPTION
VOUT12 VOUT11 VOUT10 VOUT9 VOUT8 VOUT7 VOUT6 VOUT5
38
VDD
GND
48
NC
47
46
45
44
43
42
41
40
39
37 36 NC 35 NC 34 NC 33 VOUT4 32 VOUT3
NC GND VDD VREG OUT FB NC NC VIN11 VIN10
1 2 3 4 5 6 7 8 9
ADD8707
TOP VIEW (Not to Scale)
NC
31 VOUT2 30 VOUT1 29 VDD 28 GND 27 VCOM OUT 26 NC 25 NC
04712-0-002
NC 10 VIN8 11 NC 12
13 14 15 16 17 18 19 20 21 22 23 24
VIN7
VIN6
VIN5
VIN3
VIN2
VIN1
VCOM IN-
VCOM IN+
NC
NC
NC
Figure 2. 48-Lead LFCSP
Table 4. Pin Function Descriptions
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Name NC GND VDD VREG OUT FB NC NC VIN11 VIN10 NC VIN8 NC NC VIN7 VIN6 VIN5 NC VIN3 VIN2 VIN1 VCOM INVCOM IN+ NC NC Description Ground. Normally 0 V. Supply voltage. Normally 16 V. Regulator output voltage. Provides reference voltage to resistor string and is internally connected to the top of the resistor string. Regulator feedback pin. Compares a percentage of the regulator output to the internal 1.2V voltage reference. Internal resistors are used to program the desired regulator output voltage.
Buffer inputs. Normally floating.1
Buffer inputs. Normally floating.1
Buffer inputs. Normally floating.1
Buffer inputs. Normally floating.1 VCOM amplifier inverting input. VCOM amplifier non-inverting input.
1
External resistors can be added to modify the internal resistor string to change the gamma voltage. An external resistor calculator is available upon request.
Rev. A | Page 6 of 20
NC
ADD8707
Pin No. 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Name NC NC VCOM OUT GND VDD VOUT1 VOUT2 VOUT3 VOUT4 NC NC NC NC VOUT5 VOUT6 GND VDD VOUT7 VOUT8 VOUT9 VOUT10 VOUT11 VOUT12 NC Description
VCOM amplifier output. Ground. Normally 0 V. Supply voltage. Normally 16 V.
Buffer outputs. These buffers can swing to ground.
Buffer outputs. These buffers can swing to ground. Ground. Normally 0 V. Supply voltage. Normally 16 V.
Buffer outputs. These buffers can swing to VDD.
Rev. A | Page 7 of 20
ADD8707 TYPICAL PERFORMANCE CHARACTERISTICS
20 15
OUTPUT VOLTAGE ERROR (mV)
ISINK = 25mA
ISINK = 15mA ISINK = 5mA
30
5 0 ILOAD = 0mA -5 -10 -15 -20 -25 -30 -35 -20 -10 0 10 ISOURCE = 25mA ISOURCE = 15mA ISOURCE = 5mA 20 30 40 50 60 70 TEMPERATURE (C) 80
OUTPUT VOLTAGE ERROR (mV)
10
25
20 CH6 SOURCE 15 CH3 SOURCE CH6 SINK 5 CH3 SINK 0 0.1 1 10 LOAD CURRENT (mA)
04712-006
10
90 100 110 120
04712-003
100
Figure 3. Output Voltage Error vs. Temperature
35 30
Figure 6. Output Voltage Error vs. Load Current (Channels 3 and 6)
30
OUTPUT VOLTAGE ERROR (mV)
CH11 SOURCE 25 20 15 10 CH12 SINK
04712-004
OUTPUT VOLTAGE ERROR (mV)
25
20 CH2 SOURCE 15
CH12 SOURCE
CH11 SINK
10 CH1 SOURCE CH1 SINK 5 CH2 SINK 0 0.1 1 10 LOAD CURRENT (mA)
04712-007
5 0 0.1
1 10 LOAD CURRENT (mA)
100
100
Figure 4. Output Voltage Error vs. Load Current (Channels 11 and 12)
30
Figure 7. Output Voltage Error vs. Load Current (Channels 1 and 2)
15 14 13
OUTPUT VOLTAGE ERROR (mV)
CH7 SOURCE 20 CH10 SOURCE 15
OUTPUT VOLTAGE ERROR (mV)
25
12 11 10 9 8 8 7 6 5 4 3 2 1 0 0.1 VCOM SINK
10 CH10 SINK 5
04712-005
CH7 SINK 0 0.1 1 10 LOAD CURRENT (mA)
100
1 10 LOAD CURRENT (mA)
100
Figure 5. Output Voltage Error vs. Load Current (Channels 7 and 10)
Figure 8. Output Voltage Error vs. Load Current (VCOM)
Rev. A | Page 8 of 20
04712-008
VCOM SOURCE
ADD8707
1000 900 800
0.3 MAX ERROR EACH STEP 0.2 TYPICAL UNIT B 0.1 TYPICAL UNIT C
NUMBER OF AMPLIFIERS
700
ERROR (%)
600 500 400 300 200 100 0 -0.30 -0.18 -0.10 -0.02 0.06 0.14 0.22 0.30 GAMMA OUTPUT ERROR DUE TO OFFSET AND RESISTOR MATCHING (% OF FS)
04712-009
0 TYPICAL UNIT A -0.1
-0.2 MIN ERROR EACH STEP -0.3 0 1 2 3 4 5 6 7 8 OUTPUT CHANNEL 9 10 11 12
04712-012
Figure 9. Gamma Output Voltage Error
35 30
Figure 12. Gamma Output Error per Channel (920 Parts)
15 14 13 12 11 10 9 8 7 6 5 4 3
04712-010
NUMBER OF AMPLIFIERS
OUTPUT VOLTAGE (V)
25 20 15 10
ILOAD = 0mA ILOAD = 5mA
ILOAD = 10mA
1 0 17 16 15 14 13 12 11 10 9 8 7 6 INPUT VOLTAGE (V) 5 4 3 2 1 0
0 -10.0 -7.5 -5.0 -2.5 0 2.5 5.0 7.5 OUTPUT VOLTAGE ERROR (mV)
10.0
Figure 10. VCOM Offset Voltage
35 30 200 25 20 15 10 5 0 100
Figure 13. Dropout Characteristics
DROPOUT VOLTAGE (mV)
NUMBER OF AMPLIFIERS
300 400 500 600 700 800
04712-0-011
900 1000 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 OUTPUT CURRENT (mA)
0 -500
-470
-440 -410 -380 -350 INPUT BIAS CURRENT (nA)
-320
Figure 11. VCOM Input Bias Current Distribution
Figure 14. Dropout Voltage vs. Output Current
Rev. A | Page 9 of 20
04712-014
04712-013
5
2
ADD8707
800 750 700 650 600
18
10mA
CLOAD = 1F
DROPOUT VOLTAGE (mV)
17
400 200
500 450 400 350 300 250 200 150 100 50 0 -25 -15 -5 5 15 25 35 45 55 65 TEMPERATURE (C) 75 85
5mA
INPUT VOLTAGE (V)
550
16
0 -200
15
04712-015
-400
OUTPUT VOLTAGE CHANGE (mV) OUTPUT VOLTAGE CHANGE (mV)
04712-020
0mA
95 105 115
14 TIME (100s/DIV)
Figure 15. Dropout Voltage vs. Temperature
14.5 14.4 -20C 14.3
Figure 18. Regulator Line Transient Response
CLOAD = 1F 40 20
REGULATOR OUTPUT (V)
14.2 14.1 14.0 +85C 13.9 +95C 13.8 +105C 13.7 13.6 0 2 4 6 8 10 12 14 LOAD CURRENT (mA) 16 +25C +55C
0C
LOAD CURRENT (mA)
0 -20 -40 0.1
04712-016
5
18
20
TIME (100s/DIV)
Figure 16. Regulator Output vs. ILOAD over Temperature
14.45 0mA 14.40 11 10 9 SUPPLY CURRENT (mA) 5mA 8 7 6 5 4 3 2
04712-017
Figure 19. Regulator Load Transient Response
REGULATOR OUTPUT (V)
14.35
14.30 10mA 14.25
1 0 0 2 4 6 8 10 12 SUPPLY VOLTAGE (V) 14 16 18
14.20 -20 -10
0
10
20
30 40 50 60 70 TEMPERATURE (C)
80
90 100 110
Figure 17. Regulator Output vs. Temperature
Figure 20. Supply Current vs. Supply Voltage
Rev. A | Page 10 of 20
04712-0-019
04712-0-018
ADD8707
11 10 9 8 10V PULSE 120pF 320pF 520pF 1nF 10nF
8.8 8.7
SUPPLY CURRENT (mA)
8.6 8.5 8.4 8.3
AMPLITUDE (V)
7 6 5 4 3 2 1 0 -200 0 200 400
04712-021
600 800 1000 1200 1400 1600 1800 TIME (ns)
8.1 -20
0
20
40 60 TEMPERATURE (C)
80
100
120
Figure 21. Gamma Buffers Transient Load Response vs. Capacitive Loading
Figure 22. Supply Current vs. Temperature
Rev. A | Page 11 of 20
04712-022
8.2
ADD8707 APPLICATION NOTES
The ADD8707 is a mask-programmable gamma reference generator that allows source drivers to be optimized for the different combinations of liquid crystals, glass sizes, etc. in large LCD panels. It generates 12 gamma reference outputs that can be mask-programmed in 0.2% increments using the 500 matched internal resistors (Figure 23), so that every point on the curve can be targeted within 0.1% of the desired value.
TAP POINT 4 TAP POINT 3 TAP POINT 2 TAP POINT 1 TAP POINT 500 TAP POINT 499 TAP POINT 498 TAP POINT 497
The matching and tracking accuracy of the internal resistors is typically 0.1% with worst-case deviation from the desired curve within 0.4% of the ideal gamma curve, over temperature. The ADD8707 also includes a low dropout linear regulator to provide a stable reference level for the gamma curve for optimum panel performance.
TAP POINT SELECTION
The ADD8707 uses a single resistor string consisting of 500 individual elements. The tap points are mask programmable and completely independent of each other. Refer to the Tap Point and Regulator Voltage Request Form in this data sheet.
VREG OUT 500-TPX VINX TPX VOUTX
04712-025
EACH R = 30 TYPICALLY
Figure 23. 500 Mask-Programmable Resistor String
04712-023
In a typical panel application, the selected source drivers have an internal gamma curve that is not ideal for the specific panel (Figure 24). The ADD8707 allows the gamma curve in the source drivers to be adjusted appropriately, and also insures that all the source drivers have the same gamma curve.
16 14 12
Figure 25. Gamma Buffers Tap Point Circuit.
Tap point voltages can be derived from the following equation:
VOUT X =
TPX x VREG OUT 500
where TPX is the desired tap point for the Xth channel. Table 5. Typical Mask Implementation VDD = 16 V, VREG OUT = 14.4 V, 0 X 500
VOUT12 VOUT11 VOUT10 VOUT9 VOUT8 VOUT7 VOUT6 VOUT5 VOUT4 VOUT3 VOUT2 VOUT1 Tap Point (X) 500 419 365 349 343 297 213 173 163 146 95 7 Voltage 14.400 12.067 10.512 10.051 9.878 8.554 6.134 4.982 4.694 4.205 2.736 0.202 Units V V V V V V V V V V V V
GAMMA VOLTAGE (V)
10 8 ORIGINAL GAMMA CURVE IN SOURCE DRIVERS 6 PANEL GAMMA CURVE CORRECTED BY ADD8707 4
04712-024
2 0 GAMMA REFERENCE INPUT POINTS
Figure 24. Original and Corrected Gamma Curves
Rev. A | Page 12 of 20
ADD8707
VOLTAGE REGULATOR
The on-board voltage regulator provides a regulated voltage to the resistor chain to provide stable gamma voltages. The output of the regulator is set by the two mask programmable internal resistors R1 and R2, and a reference voltage. In the ADD8707, the typical values of these parts are shown in Figure 26. To request a different regulator voltage, please refer to the Tap Point and Regulator Voltage Request Form in this data sheet.
LAND PATTERN
The LFCSP package comes with a thermal pad. Soldering down this thermal pad dramatically improves the heat dissipation of the package. It is necessary to attach vias that connect the soldered thermal pad to another layer on the board. This provides an avenue to dissipate the heat away from the part. Without vias, the heat is isolated directly under the part. Subdivide the solder paste, or stencil layer, for the thermal pad. This reduces solder balling and splatter. It is not critical how the subdivisions are arranged, as long as the total coverage of the solder paste for the thermal pad is greater than 50%. The land pattern is critical to heat dissipation. A suggested land pattern is shown in Figure 27. The thermal pad is attached to the substrate. In the ADD8707, the substrate is connected to VDD. To be electrically safe, the thermal pad should be soldered to an area on the board that is electrically isolated or connected to VDD. Attaching the thermal pad to ground adversely affects the performance of the part.
R1 5k
R2 55k
VREG OUT VREF 1.2V + -
04712-026
Figure 26. Voltage Regulator
The internal resistors have a typical accuracy of 0.1%. External resistors can be used to adjust the regulator voltage, though it is not recommended. Contact a sales office for further details.
MAXIMUM POWER DISSIPATION
The maximum safe power dissipation in the ADD8707 package is limited by the associated rise in junction temperature (TJ) on the die. At approximately 150C, the glass transition temperature, the properties of the plastic change. Even temporarily exceeding this temperature limit may change the stresses that the package exerts on the die, permanently shifting the parametric performance of the ADD8707. Exceeding a junction temperature of 175C for an extended period can result in changes in the silicon devices, potentially causing failure.
Rev. A | Page 13 of 20
ADD8707
OPERATING TEMPERATURE RANGE
The junction temperature is as follows: TJ = TAMB + JA x PDIS where: TAMB = ambient temperature specified on the data sheet. JA = junction-to-ambient thermal resistance, in C/watt. PDIS = power dissipated in the device, in watts. For the ADD8707, PDIS can be calculated by PDIS = VDD x IDQ + (IOUT X(+) x (VDD - VOUT X)) + (-IOUT X(-) x VOUTX) + (VDD - VREG OUT) x ILOAD where: VDD x IDQ = nominal system power requirements. IOUT X(+) x (VDD - VOUT X) = positive-current amplifier load power dissipation (current comes from VDD). -IOU XT(-) x VOUT X = negative-current amplifier load power dissipation (current goes to GND). (VDD - VREG OUT) x ILOAD = regulator load power dissipation. In this example, TAMB = 95C. To calculate PDIS, assume the values in Table 6. Table 6.
VOUT12 VOUT11 VOUT10 VOUT9 VOUT8 VOUT7 VOUT6 VOUT5 VOUT4 VOUT3 VOUT2 VOUT1 VOUT X (V) 14.400 12.067 10.512 10.051 9.878 8.554 6.134 4.982 4.694 4.205 2.736 0.202 IOUT X (mA) 8.3 7.9 -4.5 -4.2 5.6 -3.3 -6.9 5.7 3.5 9.6 9.5 -7.2 P (W) 0.0133 0.0311 0.0473 0.0422 0.0343 0.0282 0.0423 0.0628 0.0396 0.113 0.126 0.00145 0.582
VDD x IDQ = 16 V x 15 mA = 0.240 W. (VDD - VREG OUT) x ILOAD = (16 V - 14.4 V) x 5 mA = 0.008 W. PDIS = 0.240W + 0.582W + 0.008W = 0.830W.
Example 1
Exposed pad soldered down with via JA = 28.3C/W: TJ = 95C + (28.3C/W) x (0.830 W) = 118.5C The maximum junction temperature that is guaranteed before the part breaks down is 150C. is The maximum process limit is 125C. Because TJ is < 150C and < 125C, this example demonstrates a condition where the part should perform within process limits.
Example 2
Exposed pad not soldered down JA = 47.7C/W: TJ = 95C + (47.7C/W) x (0.830 W) = 134.6C In this example, TJ is < 150C but > 125C. Although the part should not exhibit any damage here, the process limits have been exceeded. The part may no longer operate as intended. These examples show that soldering down the exposed pad is important for proper heat dissipation. Under the same powerup and loading conditions, the unsoldered part has a higher temperature than the soldered part. Therefore, it is strongly advised that the exposed pad be soldered down.
(IOUT X(+) x (VDD - VOUT X)) + (-IOUT X(-) x VOUT X)
Rev. A | Page 14 of 20
ADD8707
7.31mm HEAT SINK SOLDER PASTE AREA 5.40mm
1.90mm
1.60mm 5.93mm
5.78mm
0.69mm 0.5mm 0.075mm 0.075mm 0.33mm DIAMETER THERMAL VIA 0.28mm
04712-020
1.60mm
Figure 27. 48-Lead LFCSP (CP-48) Land Pattern--Dimensions shown in millimeters
Notes: 1. 2. 3. 4. Gray area represents the board metallization. White area represents the solder mask and vias. Hatched area is for the heat sink solder paste. The thermal pad is electrically active. The solder mask opening should be 0.150 mm larger than the pad size, resulting in 0.075 mm of clearance between the copper pad and solder mask.
Rev. A | Page 15 of 20
ADD8707 TYPICAL APPLICATIONS CIRCUIT
0.1F 14.4V VCOM IN+ VCOM IN- FB VREG OUT 2k 700* 5k 55k 14.4V 1.2V + - GAMMA BUFFERS 0 TP12 = 500 700* 2.43 TP11 = 419 1.62 TP10 = 365 480 TP9 = 349 700* VIN8 VIN7 700* 180 TP8 = 343 1.38k TP7 = 297 2.52 TP6 = 213 1.20 TP5 = 173 300 TP4 = 163 700* VIN3 VIN2 VIN1 700* 510 TP3 = 146 1.53k TP2 = 95 2.64k TP1 = 7 210 VOUT12 VOUT11 VOUT10 VOUT9 VOUT8 VOUT7 VOUT6 VOUT5 VOUT4 VOUT3 VOUT2 VOUT1 14.4V 0.1F PANEL VCOM ITO 3.3F 8.2k
NORMALLY OPEN
4.7k
VCOM
VCOM OUT
VOLTAGE REGULATOR
VDD 16V
GAMMA 12 GAMMA 11 GAMMA 10 GAMMA 9 GAMMA 8 GAMMA 7 GAMMA 6 GAMMA 5 GAMMA 4 GAMMA 3 GAMMA 2 GAMMA 1
VIN11 VIN10
12.067V
700*
10.512V
10.051V
GAMMA 12 GAMMA 11 GAMMA 10 GAMMA 9 GAMMA 8 GAMMA 7 GAMMA 6 GAMMA 5 GAMMA 4 GAMMA 3 GAMMA 2 GAMMA 1
9.878V
8.554V
NORMALLY OPEN
700* VIN6 VIN5 700*
6.134V
4.982V
4.694V
4.205V
2.736V
700*
0.202V
*ESD PROTECTION RESISTORS
GND
GND
Figure 28. Typical Applications Circuit
Rev. A | Page 16 of 20
04712-028
GAMMA 12 GAMMA 11 GAMMA 10 GAMMA 9 GAMMA 8 GAMMA 7 GAMMA 6 GAMMA 5 GAMMA 4 GAMMA 3 GAMMA 2 GAMMA 1
04712-028
ADD8707 DEVELOPMENT CIRCUIT
For development purposes, the ADD8707 is available in a generic form without the tap points (see Figure 29). The typical applications circuit for this part is shown in Figure 30. To order this version, refer to the Ordering Guide. The model listed is the development version.
VREG OUT VCOM IN- VCOM IN+
700* FB + - VREG 1.2V
VCOM GAMMA BUFFERS
VCOM OUT
VOUT12 700* VIN11 700* VIN10
VOUT11 VOUT10 VOUT9
VIN8 VIN7 VIN6 VIN5
700*
VOUT8 VOUT7 VOUT6 VOUT5 VOUT4
700*
700*
700*
700* VIN3 VIN2 VIN1 700*
VOUT3 VOUT2 VOUT1
04712-029
700*
*ESD PROTECTION RESISTORS
Figure 29. Block Diagram for ADD8707 Development Version (with No Tap Points)
Rev. A | Page 17 of 20
ADD8707
0.1F
14.4V VCOM IN+
8.2k
4.7k 55k VCOM IN- VREG OUT ESD PROTECTION RESISTOR 700 VOLTAGE REGULATOR 14.4V VDD 16V 2k 3.3F
GAMMA 12 GAMMA 11 GAMMA 10 GAMMA 9 GAMMA 8 GAMMA 7 GAMMA 6 GAMMA 5 GAMMA 4 GAMMA 3 GAMMA 2 GAMMA 1
5k FB
VCOM
VCOM OUT
PANEL VCOM ITO
1.2V
+ -
GAMMA BUFFERS ESD PROTECTION RESISTORS VIN11 VIN10 700 4.53k VOUT12 VOUT11 VOUT10 VOUT9 VOUT8 VOUT7 5.58k VOUT6 VOUT5 TP4 = 163 VOUT4 VOUT3 VOUT2 4.89k VOUT1
0.1F
14.4V
GAMMA 12 GAMMA 11 GAMMA 10 GAMMA 9 GAMMA 8 GAMMA 7 GAMMA 6 GAMMA 5 GAMMA 4 GAMMA 3 GAMMA 2 GAMMA 1
700
TP9 = 349
10.051V
VIN8 VIN7 VIN6 VIN5
700
700
700
700
4.694V
VIN3 VIN2 VIN1
700
700
700
GND
Figure 30. Typical Applications Circuit for ADD8707 Development Version (with No Tap Points)
Rev. A | Page 18 of 20
04712-030
GAMMA 12 GAMMA 11 GAMMA 10 GAMMA 9 GAMMA 8 GAMMA 7 GAMMA 6 GAMMA 5 GAMMA 4 GAMMA 3 GAMMA 2 GAMMA 1
04712-028
ADD8707 TAP POINT AND REGULATOR VOLTAGE REQUEST FORM
REGULATOR SECTION--VREG OUT
To ensure correct regulator operation VDD must exceed VREG by 600 mV minimum--that is, a VREG = 14.4 V requires a minimum VDD = 15.0 V.
Parameter VREG OUT Value (6.9 V - 15.4 V)
TAP POINT SECTION
Gamma output voltages are calculated using the following formula:
VOUT =
TP x VREG OUT 500
A Microsoft(R) Excel spreadsheet is available which automatically calculates the best tap point based on VREG OUT and the desired output voltages for each gamma output.
Output VOUT18 VOUT17 VOUT16 VOUT15 VOUT14 VOUT13 VOUT12 VOUT11 VOUT10 VOUT9 VOUT8 VOUT7 VOUT6 VOUT5 VOUT4 VOUT3 VOUT2 VOUT1 Tap Point
CUSTOMER INFORMATION
Name: Company: Address: ____________________________________________ ____________________________________________ ____________________________________________ ____________________________________________ Date: ____________________________________________
Please return this form to your local sales office.
Rev. A | Page 19 of 20
ADD8707 OUTLINE DIMENSIONS
7.00 BSC SQ 0.60 MAX 0.60 MAX
37 36
0.30 0.23 0.18
48 1
PIN 1 INDICATOR
PIN 1 INDICATOR
TOP VIEW
6.75 BSC SQ
EXPOSED PAD
(BOTTOM VIEW)
5.25 5.10 SQ 4.95
0.50 0.40 0.30
25 24
12 13
0.25 MIN 5.50 REF
1.00 0.85 0.80
12 MAX
0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.50 BSC
SEATING PLANE
0.20 REF
COPLANARITY 0.08
COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2
Figure 31. 48-Lead Lead Frame Chip Scale Package [LFCSP] 7 mm x 7 mm Body (CP-48) Dimensions shown in millimeters
ORDERING GUIDE
Model1 ADD8707WCPZ-REEL72, 3 Temperature Package -40C to +105C Package Description 48-Lead Lead Frame Chip Scale Package Package Outline CP-48
1 2 3
Available in reels only. Z = Pb-free part. Development version.
(c) 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04712-0-10/04(A)
Rev. A | Page 20 of 20

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