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a
Preliminary Technical Data
FEATURES Ultra Low Power 90mW @ 20MSPS; 135mW @ 40MSPS; 190mW @ 65MSPS SNR = 66.5 dBc (to Nyquist); SFDR = 82 dBc @ 2.4MHz Analog Input ENOB = 10.5 bits DNL= 0.5 LSB Differential Input with 500MHz Full Power Bandwidth Flexible and Selectable Analog Input: 4Vp-p to 1Vp-p Data Formats Supported; Offset Binary, Twos Complement and Gray Code Output Enable Pin 2-step power down; Full Power down and Sleep mode APPLICATIONS Ultrasound and Medical Imaging Battery Powered Instruments; Hand-Held Scopemeters; Low Cost Digital Oscilloscopes; Low Power Digital Still Cameras and Copiers; Low power communications PRODUCT DESCRIPTION
The AD9237 is a monolithic, single 3V supply, 12-bit, 20/40/65MSPS Analog to Digital Converter with a high performance sample-and-hold amplifier and voltage reference. The AD9237 uses a multistage differential pipelined architecture with output error correction logic to provide 12-bit accuracy at 20/40/65MSPS data rates and guarantee no missing codes over the full operating temperature range. The wide bandwidth, truly differential SHA allows for a variety of user-selectable input ranges and offsets including single-ended applications. It is suitable for multiplexed systems that switch full-scale voltage levels in successive channels and for sampling single-channel inputs at frequencies well beyond the Nyquist rate. With significant power savings over previously available analog to digital converters, the AD9237 is suitable for applications imaging and medical ultrasound. A single-ended clock input is used to control all internal conversion cycles. The digital output data is presented in straight binary, twos complement, or gray code formats. An out-of-range (OTR) signal indicates an overflow condition, which can be used with the most significant bit to determine low or high overflow.
12-Bit, 20/40/65 MSPS 3 V Low Power A/D Converter
AD9237
FUNCTIONAL BLOCK DIAGRAM
AVDD VINA VINB DRVDD
SHA
MDAC1
8-STAGE Pipeline
A/D
REFT REFB
4
A/D
16
3
CORRECTION LOGIC
12
OUTPUT BUFFERS
OE
OTR
AD9237
VREF
MODE SELECT
D11 (MSB) D0 (LSB)
SENSE
REF SELECT
0.5 V
AVSS
CLOCK
PDWN
MODE2
MODE
DRVSS
Fabricated on an advanced CMOS process, the AD9237 is available in a 32-pin chip scale package and is specified over the industrial temperature range (-40C to +85C). PRODUCT HIGHLIGHTS 1. Operating at 65MSPS, the AD9237 consumes a low 190mW and only consumes 135mW at 40 MSPS and 90mW at 20MSPS. 2. The AD9237 operates from a single 3V power supply, and features a separate digital output driver supply to accommodate 2.5V and 3.3V logic families. 3. The patented SHA input maintains excellent performance for input frequencies beyond Nyquist, and can be configured for single-ended or differential operation. 4. The AD9237 is pin compatible to the AD9235, a 12-bit, 20/40/65 MSPS A/D converter. This allows a simplified path for low power 12-bit systems. 5. The AD9237 is optimized for selectable and flexible input ranges from 4Vp-p to 1Vp-p. 6. Output Enable pin to allow for multiplexing of the outputs. 7. Two-step power down supports a standby mode in addition to a power down mode. 8. The OTR output bit indicates when the signal is beyond the selected input range.
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 World Wide Web Site: http://www.analog.com Fax: 617-326-8703 (c) Analog Devices, Inc., 2005
AD9237
unless otherwise noted)
Preliminary Technical Data
DC SPECIFICATIONS (AVDD = +3V, DRVDD = +3V, 2Vp-p Input, -0.5dBFS, 1.0V internal reference, TMIN to TMAX,
Parameter
RESOLUTION ACCURACY No Missing Codes Guaranteed Offset Error 1 Gain Error Differential Nonlinearity (DNL) Integral Nonlinearity (INL) TEMPERATURE DRIFT Offset Error 1 Gain Error INTERNAL VOLTAGE REFERENCE Output Voltage Error (1 V Mode) Load Regulation @ 1.0 mA Output Voltage Error (0.5 V Mode) Load Regulation @ 0.5 mA INPUT REFERRED NOISE VREF = 0.5 V VREF = 1.0 V ANALOG INPUT Input Span, VREF = 0.5V; MODE 2 = 0V; Input Span, VREF = 1.0V; MODE 2 = 0V; Input Span, VREF = 0.5V; MODE2= AVDD; Input Span, VREF = 1.0V;MODE2 = AVDD; 3 Input Capacitance REFERENCE INPUT RESISTANCE POWER SUPPLIES Supply Voltages AVDD DRVDD Supply Current 2 IAVDD 2 IDRVDD PSRR POWER CONSUMPTION 4 DC Input 2 Sine Wave Input 5 Power Down Mode 6 Standby Power Temp Full Full Full Full Full 25C Full 25C Full Full Full Full Full Full 25C 25C Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Test Level VI VI VI VI IV I IV I V V VI V V V V V IV IV IV IV V V IV IV VI VI VI V VI V V 2.7 2.25 AD9237BCPZ-20 Min 12 12 +0.5 +0.5 +0.5 +0.5 +1.2 +1.2 +2 +12 +5 0.8 +2.5 0.1 1.36 0.68 1 2 2 4 7 7 3.0 3.0 30 2 +0.01 90 95 1 17 3.6 3.6 2.7 2.25 7 7 3.0 3.0 44 5 +0.01 134 152 1 17 3.6 3.6 2.7 2.25 Typ Max AD9237BCPZ-40 Min 12 12 +0.5 +0.5 +0.5 +0.5 +1.2 +1.2 +2 +12 +5 0.8 +2.5 0.1 1.36 0.68 1 2 2 4 7 7 3.0 3.0 63 7 +0.01 188 216 1 17 3.6 3.6 Typ Max AD9237BCPZ-65 Min 12 12 +0.5 +0.5 +0.5 +0.5 +1.2 +1.2 +2 +12 +5 0.8 +2.5 0.1 1.36 0.68 1 2 2 4 Typ Max Units Bits Bits %FSR %FSR LSB LSB LSB LSB ppm/C ppm/C mV mV mV mV LSB rms LSB rms Vp-p Vp-p Vp-p pF k V V mA mA %FSR mW mW mW mW
NOTES 1. Gain error and gain temperature coefficient are based on the ADC only (with a fixed 1.0V external reference). 2. Measured at maximum Clock Rate, FIN = 2.4MHz, full-scale sine wave, with approximately 5pF loading on each output bit. 3. Input Capacitance refers to the effective capacitance between one differential input pin and AGND. 4. Measured with dc input at Maximum Clock Rate. 5. Power Down Mode power is measured with a dc input, the CLK pin inactive (i.e., set to AVDD or AGND) 6. Standby Mode power is measured with a dc input, the CLK pin active. Specifications subject to change without notice.
AD9237 Preliminary Technical Information - 5/18/2005
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Preliminary Technical Data
DIGITAL SPECIFICATIONS
Parameter
Temp Test Level AD9237BCPZ-20 Min 2.0 -10 -10 2 3.29 3.25 0.2 0.05 2.49 2.45 0.2 0.05 2.49 2.45 0.2 0.05 3.29 3.25 0.2 0.05 2.49 2.45 0.8 10 10 Typ Max AD9237BCPZ-40 Min 2.0 -10 -10 2 3.29 3.25 0.8 10 10 Typ Max
AD9237
AD9237BCPZ-65 Min 2.0 -10 -10 2 0.8 10 10 Typ Max Units V V A A PF V V V V V V V V
LOGIC INPUTS High-Level Input Voltage Full IV Low-Level Input Voltage Full IV High-Level Input Current Full IV Low-Level Input Current Full IV Input Capacitance Full V 1 LOGIC OUTPUTS DRVDD = 3.3V High-Level Output Voltage (IOH=50A) Full IV High-Level Output Voltage (IOH=0.5mA) Full IV Low-Level Output Voltage (IOL=1.6mA) Full IV Low-Level Output Voltage (IOL=50A) Full IV DRVDD = 2.5V High-Level Output Voltage (IOH=50A) Full IV High-Level Output Voltage (IOH=0.5mA) Full IV Low-Level Output Voltage (IOL=1.6mA) Full IV Low-Level Output Voltage (IOL=50A) Full IV NOTES: 1. Output Voltage Levels measured with 5pF load on each output. Specifications subject to change without notice.
0.2 0.05
0.2 0.05
SWITCHING SPECIFICATIONS
Parameter
Temp Test Level AD9237BCPZ-20 Min Typ Max AD9237BCPZ-40 Min Typ Max AD9237BCPZ-65 Min Typ Max Units
CLOCK INPUT PARAMETERS Max Conversion Rate Full IV 20 40 65 MSPS Min Conversion Rate Full V 1 1 1 MSPS CLOCK PERIOD Full V 50.0 25.0 16.6 ns CLOCK Pulsewidth High Full V 15 8.8 6.8 ns CLOCK Pulsewidth Low Full V 15 8.8 6.8 DATA OUTPUT PARAMETERS 1 Output Delay (tOD) Full V 3.5 3.5 3.5 ns Pipeline Delay (Latency) Full V 9 9 9 Cycles Output Enable Time Full V 6 6 6 ns Output Disable Time Full V 3 3 3 ns Aperture Delay Full V 1.0 1.0 1.0 ns Aperture Uncertainty (Jitter) Full V 0.5 0.5 0.5 ps rms 2 Wake-Up time (Sleep Mode) Full V 2.5 2.5 2.5 ms Wake-Up time (Standby Mode) Full V tbd tbd tbd ns OUT-OF_RANGE RECOVERY TIME Full V 1 1 2 cycles NOTES: 1. Valid Data Delay is measured from CLOCK 50% transition to DATA 50% transition, with 5pF load. 2. Wake-Up Time is dependant on value of decoupling capacitors, typical values shown with 0.1F and 10F capacitors on REFT and REFB. Specifications subject to change without notice.
N N-1 ANALOG INPUT tA N+3 N+4 N+5 N+7 N+6 N+1 N+2 N+8
CLK
DATA OUT
N-9
N-8
N-7
N-6
N-5
N-4
N-3
N-2
N-1
N tPD = 6.0ns MAX 2.0ns MIN
Figure 1. Timing Diagram AD9237 Preliminary Technical Information - 5/18/2005 -3- REV PrF
AD9237
unless otherwise noted)
Preliminary Technical Data
AD9237BCPZ-20 Min Typ 66.5 66.5 66.5 66.5 Max AD9237BCPZ-40 Min Typ 66.5 66.5 66.5 66.5 tbd 65 65 65 65 tbd 65 65 65 65 tbd 10.5 10.5 tbd 10.5 10.5 tbd 80 80 80 80 tbd 80 80 80 80 tbd tbd tbd Tbd 82 82 82 82 82 82 82 82 tbd tbd 82 82 tbd 82 82 tbd 80 80 tbd 10.5 tbd 80 80 65 65 tbd 10.5 66.5 66.5 tbd 65 65 Max AD9237BCPZ-65 Min Typ 66.5 66.5 Max Units dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB Bits Bits Bits Bits Bits dB dB dB dB dB dB dB dB dB dB dB dBc dBc dBc dBc dBc dBc dBc dBc
AC SPECIFICATIONS (AVDD = +3V, DRVDD = +3V, 2Vp-p Input, -0.5dBFS, 1.0V internal reference, TMIN to TMAX,
Parameter
SIGNAL-TO-NOISE RATIO FINPUT = 2.4 MHz FINPUT = 10.3 MHz FINPUT = 19.6 MHz FINPUT = 30 MHz FINPUT = 70 MHz SIGNAL-TO-NOISE RATIO AND DISTORTION FINPUT = 2.4 MHz FINPUT = 10.3 MHz FINPUT = 19.6 MHz FINPUT = 30 MHz FINPUT = 70 MHz EFFECTIVE NUMBER OF BITS FINPUT = 2.4 MHz FINPUT = 10.3 MHz FINPUT = 19.6 MHz FINPUT = 30 MHz FINPUT = 70 MHz TOTAL HARMONIC DISTORTION FINPUT = 2.4 MHz FINPUT = 10.3 MHz FINPUT = 19.6 MHz FINPUT = 30 MHz FINPUT = 70 MHz nd rd WORST HARMONIC (2 or 3 ) FINPUT = 9.7 MHz FINPUT = 19.6 MHz FINPUT = 30 MHz SPURIOUS FREE DYNAMIC RANGE FINPUT = 2.4 MHz FINPUT = 10.3 MHz FINPUT = 19.6 MHz FINPUT = 30 MHz FINPUT = 70 MHz Specifications subject to change without notice. Temp Full 25C Full 25C Full 25C Full 25C 25C Full 25C Full 25C Full 25C Full 25C 25C 25C 25C 25C 25C 25C Full 25C Full 25C Full 25C Full 25C 25C Full Full Full Full 25C Full 25C Full 25C Full 25C 25C Test Level IV I IV I IV I IV I V IV I IV I IV I IV I V V V V V V IV I IV I IV I IV I V IV IV IV IV I IV I IV I IV I V
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Preliminary Technical Data
ABSOLUTE MAXIMUM RATINGS1
Pin Name ELECTRICAL
With Respect to
AD9237
EXPLANATION OF TEST LEVELS
Test Level I 100% production tested. II 100% production tested at +25C and sample tested at specified temperatures. III Sample tested only. IV Parameter is guaranteed by design and characterization testing. V Parameter is a typical value only. VI 100% production tested at +25C; guaranteed by design and characterization testing for industrial temperature range; 100% production tested at temperature extremes for military devices.
Min
-0.3 -0.3 -0.3 -3.9 -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V -40
Max
+3.9 +3.9 +0.3 +3.9 DRVDD +0.3 AVDD +0.3 AVDD +0.3 AVDD +0.3 AVDD +0.3 AVDD +0.3 AVDD +0.3 AVDD +0.3 85 150 300 150
Unit
V V V V V V V V V V V V C C C C
AVDD AGND DRVDD DGND AGND DGND AVDD DRVDD Digital Outputs DGND CLK, OEB AGND MODE, MODE2 AGND VIN+, VINAGND VREF AGND SENSE AGND REFB, REFT AGND PDWN AGND 2 ENVIRONMENTAL Operating Temperature Junction Temperature Lead Temperature (10 sec) Storage Temperature
-65
NOTES 1 Absolute maximum ratings are limiting values to be applied individually, and beyond which the serviceability of the circuit may be impaired. Functional operability is not necessarily implied. Exposure to absolute maximum rating conditions for an extended period may affect device reliability. 2 Typical thermal impedances (32-terminal LFCSP); JA = 32.5C/W; JC = 32.71C/W. These measurements were taken on a 4-layer board in still air, in accordance with EIA/JESD51-1.
ORDERING GUIDE
Model AD9237BCPZ-201 AD9237BCPZ-40 AD9237BCPZ-65 AD9237BCP-20EB AD9237BCP-40EB AD9237BCP-65EB
1 1
Temperature Range -40C to +85C -40C to +85C -40C to +85C
Package Description 32-Lead Frame Chip Scale Package (LFCSP) 32-Lead Frame Chip Scale Package (LFCSP) 32-Lead Frame Chip Scale Package (LFCSP) LFCSP Evaluation Board (w/ AD9237BCPZ-20) LFCSP Evaluation Board (w/ AD9237BCPZ-40) LFCSP Evaluation Board (w/ AD9237BCPZ-65)
Package Option CP-32 CP-32 CP-32
1
It is recommended that the exposed paddle be soldered to the ground plane. There is an increased reliability of the solder joints, and maximum thermal capability of the package is achieved with the exposed paddle soldered to the customer board.
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AD9237
DEFINITIONS OF SPECIFICATIONS
INTEGRAL NONLINEARITY (INL) INL refers to the deviation of each individual code from a line drawn from "negative full scale" through "positive full scale." The point used as "negative full scale" occurs 1/2 LSB before the first code transition. "Positive full scale" is defined as a level 1 1/2 LSB beyond the last code transition. The deviation is measured from the middle of each particular code to the true straight line. DIFFERENTIAL NONLINEARITY (DNL, NO MISSING CODES) An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Guaranteed no missing codes to 12-bit resolution indicates that all 4096 codes, respectively, must be present over all operating ranges. ZERO ERROR The major carry transition should occur for an analog value 1/2 LSB below VINA = VINB. Zero error is defined as the deviation of the actual transition from that point. GAIN ERROR The first code transition should occur at an analog value 1/2 LSB above negative full scale. The last transition should occur at an analog value 1 1/2 LSB below the positive full scale. Gain error is the deviation of the actual difference between first and last code transitions and the ideal difference between first and last code transitions. TEMPERATURE DRIFT The temperature drift for zero error and gain error specifies the maximum change from the initial (25C) value to the value at TMIN or TMAX. POWER SUPPLY REJECTION The specification shows the maximum change in full scale from the value with the supply at the minimum limit to the value with the supply at its maximum limit. APERTURE JITTER Aperture jitter is the variation in aperture delay for successive samples and can be manifested as noise on the input to the ADC. APERTURE DELAY Aperture delay is a measure of the sample-and-hold amplifier (SHA) performance and is measured from the rising edge of the clock input to when the input signal is held for conversion. SIGNAL-TO-NOISE AND DISTORTION (S/N+D, SINAD) RATIO S/N+D is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for S/N+D is expressed in decibels.
Preliminary Technical Data
EFFECTIVE NUMBER OF BITS (ENOB) For a sine wave, SINAD can be expressed in terms of the number of bits. Using the following formula, N = (SINAD - 1.76)/6.02 it is possible to obtain a measure of performance expressed as N, the effective number of bits. Thus, effective number of bits for a device for sine wave inputs at a given input frequency can be calculated directly from its measured SINAD. TOTAL HARMONIC DISTORTION (THD) THD is the ratio of the rms sum of the first six harmonic components to the rms value of the measured input signal and is expressed as a percentage or in decibels. SIGNAL-TO-NOISE RATIO (SNR) SNR is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding the first six harmonics and dc. The value for SNR is expressed in decibels. SPURIOUS FREE DYNAMIC RANGE (SFDR) SFDR is the difference in dB between the rms amplitude of the input signal and the peak spurious signal. CLOCK PULSEWIDTH AND DUTY CYCLE Pulsewidth high is the minimum amount of time that the clock pulse should be left in the logic "1" state to achieve rated performance: pulse width low is the minimum time the clock pulse should be left in the low state. At a given clock rate, these specs define an acceptable clock duty cycle. MINIMUM CONVERSION RATE The clock rate at which the SNR of the lowest analog signal frequency drops by no more than 3 dB below the guaranteed limit. MAXIMUM CONVERSION RATE The clock rate at which parametric testing is performed. OUTPUT PROPAGATION DELAY The delay between the clock logic threshold and the time when all bits are within valid logic levels. TWO TONE SFDR The ratio of the rms value of either input tone to the rms value of the peak spurious component. The peak spurious component may or may not be an IMD product. May be reported in dBc (i.e., degrades as signal levels are lowered) or in dBFS (always related back to converter full scale).
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Preliminary Technical Data
PIN FUNCTION DESCRIPTIONS (32 Pin LFCSP Package)
Pin No. 1 Name MODE 2
AD9237
2 3 4
CLK OE PDWN
5,6 7-14, 17-20 15 16 21 22
DNC D0 (LSB) - D11 (MSB) DGND DRVDD OTR MODE
23 24 25 26 27,32 28,31 29 30
SENSE VREF REFB REFT AVDD AGND VIN+ VIN-
Function SHA Gain Select and Power Control (see Figure 2) MODE2 Connection SHA Gain Auto Power Control AVDD 1 Disabled 2/3 AVDD 1 Enabled 1/3 AVDD 2 Enabled AGND 2 Disabled Clock Input Pin Output Enable Pin (active low) Power-Down function selection. PWDN Function AVDD Power Down Mode: All circuits powered down, no clock 1/3 AVDD Standby Mode: Only current & voltage references powered up AGND Power Up Do Not Connect Data Output Pins Digital ground. Digital Output Driver Supply. Out of Range Flag Output Data Format Select and Duty Cycle Stabilizer Control MODE Connection Output Data Format Duty Cycle Stabilizer AVDD Twos Complement Disabled 2/3 AVDD Twos Complement Enabled 1/3 AVDD Offset Binary Enabled AGND Offset Binary Disabled Reference mode/Input Full Scale Select Voltage Reference Input/Output. Differential Reference (-). Differential Reference (+). Analog Power Supply. Analog ground. Analog Input Pin (+). Analog Input Pin (-).
Preliminary LFCSP Pin Configuration
AGND AGND AVDD AVDD REFT VINREFB 25 VIN+ 29
32
31
30
28
27
MODE 2
1
26
24
VREF
CLK OE
2
23
SENSE
3
22
MODE
PDW N
4
NC
5
NC
6
AD9237BCP Lead Fram e Chip Scale Package Top View (Not to Scale)
21
OTR
20
D11 (MSB)
19
D10
(LSB) D0
7
18
D9
D1
8
17
D8
10
11
12
13
14
15
D2
D3
D4
D5
D6
D7
DGND
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DRVDD
16
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AD9237
Preliminary Technical Data
TYPICAL PERFORMANCE CHARACTERISTICS
(AVDD = 3.0 V, DRVDD = 3.0 V, fSAMPLE = 65 MSPS, DCS Disabled, 2 Vp-p Differential Input, AIN = -0.5 dBFS, 1.0 V internal reference, TA = 25C, unless otherwise noted.)
70
65 Power Scaling Off
60
55
50 IAVDD (mA)
45 Power Scaling On 40
35
30
25
20 10 20 30 40 Clock Frequency (Msps) 50 60 70
Figure 2. AD9237-65 Analog Current vs. Clock Frequency vs. Power Scaling
AD9237 Preliminary Technical Information - 5/18/2005
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Preliminary Technical Data
AD9237
32-LFCSP Package Dimensions
AD9237 Preliminary Technical Information - 5/18/2005
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PR05455-0-5/05(PrF)

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