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| PHK12NQ03LT TrenchMOSTM logic level FET M3D315 Rev. 01 -- 22 March 2002 Product data 1. Product profile 1.1 Description N-channel enhancement mode field-effect transistor in a plastic package using TrenchMOSTM1technology. Product availability: PHK12NQ03LT in SOT96-1 (SO8). 1.2 Features s Low on-state resistance s Fast switching 1.3 Applications s DC to DC converters s Portable equipment applications 1.4 Quick reference data s VDS = 30 V s Ptot = 2.5 W s ID = 12 A s RDSon = 14 m 2. Pinning information Table 1: Pin 1,2,3 4 5,6,7,8 Pinning - SOT96-1, simplified outline and symbol Description source (s) gate (g) drain (d) g 1 Top view 4 MBK187 Simplified outline 8 5 Symbol d MBB076 s SOT96-1 (SO8) 1. TrenchMOS is a trademark of Koninklijke Philips Electronics N.V. Philips Semiconductors PHK12NQ03LT TrenchMOSTM logic level FET 3. Limiting values Table 2: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VDS VGS ID IDM Ptot Tstg Tj IS drain-source voltage (DC) gate-source voltage drain current peak drain current total power dissipation storage temperature operating junction temperature source (diode forward) current Tsp = 25 C Tsp = 25 C; Figure 2 and 3 Tsp = 25 C; pulsed; Figure 3 Tsp = 25 C; Figure 1 Conditions Tj = 25 to 150 C Min -55 -55 Max 30 20 12 45 2.5 +150 +150 12 Unit V V A A W C C A Source-drain diode 9397 750 09405 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 22 March 2002 2 of 12 Philips Semiconductors PHK12NQ03LT TrenchMOSTM logic level FET 120 Pder (%) 80 03aa17 03aa25 120 Ider (%) 80 40 40 0 0 50 100 150 Tsp (C) 200 0 0 50 100 150 Tsp ( C) o 200 P tot P der = ---------------------- x 100% P tot ( 25 C ) VGS 5 V ID I der = ------------------- x 100% I D ( 25 C ) Fig 1. Normalized total power dissipation as a function of solder point temperature. 102 ID (A) 10 Limit RDSon = VDS / ID Fig 2. Normalized continuous drain current as a function of solder point temperature. 003aaa160 1 DC tp = 10 s 100 s 1 ms 10 ms 1s 10-1 10-2 10-1 1 10 VDS (V) 102 Tsp = 25 C; IDM is single pulse Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage. 9397 750 09405 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 22 March 2002 3 of 12 Philips Semiconductors PHK12NQ03LT TrenchMOSTM logic level FET 4. Thermal characteristics Table 3: Rth(j-a) Thermal characteristics Conditions Min Typ 60 Max Unit K/W thermal resistance from junction to ambient mounted on a printed circuit board; tp 10 s; minimum footprint; Figure 4 Symbol Parameter 4.1 Transient thermal impedance 102 Zth(j-a) (K/W) = 0.5 003aaa161 0.2 10 0.1 0.05 0.02 P = tp T single pulse tp T t 1 10-4 10-3 10-2 10-1 1 10 tp (s) 102 Fig 4. Transient thermal impedance from junction to ambient as a function of pulse duration. 9397 750 09405 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 22 March 2002 4 of 12 Philips Semiconductors PHK12NQ03LT TrenchMOSTM logic level FET 5. Characteristics Table 4: Characteristics Tj = 25 C unless otherwise specified Symbol Parameter Static characteristics V(BR)DSS drain-source breakdown voltage VGS(th) IDSS gate-source threshold voltage drain-source leakage current ID = 250 A; VGS = 0 V ID = 250 A; VDS = VGS; Tj = 25 C; Figure 9 VDS = 24 V; VGS = 0 V Tj = 25 C Tj = 100 C IGSS RDSon gate-source leakage current drain-source on-state resistance VGS = 20 V; VDS = 0 V VGS = 4.5 V; ID = 10 A; Figure 7 and 8 VGS = 10 V; ID = 12 A; Figure 7 and 8 Dynamic characteristics gfs Qg(tot) Qgs Qgd Ciss Coss Crss td(on) tr td(off) tf VSD trr forward transconductance total gate charge gate-source charge gate-drain (Miller) charge input capacitance output capacitance reverse transfer capacitance turn-on delay time rise time turn-off delay time fall time source-drain (diode forward) voltage IS = 1 A; VGS = 0 V; Figure 12 reverse recovery time IS = 2.3 A; dIS/dt = -100 A/s; VGS = 0 V VDD = 16 V; RD = 10 ; VGS = 10 V VGS = 0 V; VDS = 16 V; f = 1 MHz; Figure 11 VDS = 15 V; ID = 10 A; ID = 15 A; VDD = 16 V; VGS = 5 V; Figure 13 34 17.6 4 4.4 391 190 10.6 11.7 37 19 0.7 70 1.0 S nC nC nC pF pF pF ns ns ns ns V ns 11 8.9 1 5 100 14 10.5 A A nA m m 30 1 2 V V Conditions Min Typ Max Unit 1335 - Source-drain (reverse) diode 9397 750 09405 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 22 March 2002 5 of 12 Philips Semiconductors PHK12NQ03LT TrenchMOSTM logic level FET 003aaa162 16 ID (A) 12 5V 20 ID (A) 16 003aaa163 4V 2.8 V 12 8 8 2.5 V 4 4 VGS = 2.2 V 0 0 0.4 0.8 1.2 1.6 2.0 VDS (V) 0 0 1 150 C 25 C 2 3 VGS (V) 4 Tj = 25 C Tj = 25 C and 150 C; VDS > ID x RDSon Fig 5. Output characteristics: drain current as a function of drain-source voltage; typical values. Fig 6. Transfer characteristics: drain current as a function of gate-source voltage; typical values. 03aa27 200 RDSon (m) 160 003aaa164 2 a 2.2 V VGS = 2.5 V 1.6 120 1.2 80 5V 40 4V 0 0 4 8 12 ID (A) 16 0.8 0.4 0 -60 0 60 120 Tj ( C) o 180 Tj = 25 C R DSon a = ----------------------------R DSon ( 25C ) Fig 8. Normalized drain source on-state resistance factor as a function of junction temperature. Fig 7. Drain-source on-state resistance as a function of drain current; typical values. 9397 750 09405 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 22 March 2002 6 of 12 Philips Semiconductors PHK12NQ03LT TrenchMOSTM logic level FET 2.5 VGS(th) (V) 2 max 03aa33 10-1 ID (A) 10-2 03aa36 typ 1.5 min 1 10-3 min typ max 10-4 0.5 10-5 0 -60 0 60 120 Tj (C) 180 10-6 0 1 2 VGS (V) 3 ID = 1 mA; VDS = VGS Tj = 25 C; VDS = 5 V Fig 9. Gate-source threshold voltage as a function of junction temperature. Fig 10. Sub-threshold drain current as a function of gate-source voltage. 104 C (pF) 003aaa165 20 IS (A) 16 003aaa166 Ciss 103 12 150 C 8 Coss 4 25 C Crss 102 0 10-1 1 10 VDS (V) 102 0.4 0.6 0.8 VSD (V) 1 VGS = 0 V; f = 1 MHz Tj = 25 C and 150 C; VGS = 0 V Fig 11. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values. Fig 12. Source (diode forward) current as a function of source-drain (diode forward) voltage; typical values. 9397 750 09405 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 22 March 2002 7 of 12 Philips Semiconductors PHK12NQ03LT TrenchMOSTM logic level FET 10 VGS (V) 8 003aa167 6 4 2 0 0 10 20 30 QG (nC) 40 ID = 15 A; VDD = 16 V Fig 13. Gate-source voltage as a function of gate charge; typical values. 9397 750 09405 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 22 March 2002 8 of 12 Philips Semiconductors PHK12NQ03LT TrenchMOSTM logic level FET 6. Package outline SO8: plastic small outline package; 8 leads; body width 3.9 mm SOT96-1 D E A X c y HE vMA Z 8 5 Q A2 pin 1 index Lp 1 e bp 4 wM L detail X A1 (A 3) A 0 2.5 scale 5 mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 1.75 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 5.0 4.8 0.20 0.19 E (2) 4.0 3.8 0.16 0.15 e 1.27 HE 6.2 5.8 L 1.05 Lp 1.0 0.4 Q 0.7 0.6 v 0.25 0.01 w 0.25 0.01 y 0.1 Z (1) 0.7 0.3 0.010 0.057 0.069 0.004 0.049 0.019 0.0100 0.014 0.0075 0.244 0.039 0.028 0.050 0.041 0.228 0.016 0.024 0.028 0.004 0.012 8 0o o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT96-1 REFERENCES IEC 076E03S JEDEC MS-012AA EIAJ EUROPEAN PROJECTION ISSUE DATE 95-02-04 97-05-22 Fig 14. SOT96-1 (SO8). 9397 750 09405 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 22 March 2002 9 of 12 Philips Semiconductors PHK12NQ03LT TrenchMOSTM logic level FET 7. Revision history Table 5: Rev Date 01 20020322 Revision history CPCN Description Product data; initial version 9397 750 09405 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 22 March 2002 10 of 12 Philips Semiconductors PHK12NQ03LT TrenchMOSTM logic level FET 8. Data sheet status Data sheet status[1] Objective data Preliminary data Product status[2] Development Qualification Definition This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A. Product data Production [1] [2] Please consult the most recently issued data sheet before initiating or completing a design. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 9. Definitions Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 10. Disclaimers Life support -- These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Contact information For additional information, please visit http://www.semiconductors.philips.com. For sales office addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com. 9397 750 09405 Fax: +31 40 27 24825 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data Rev. 01 -- 22 March 2002 11 of 12 Philips Semiconductors PHK12NQ03LT TrenchMOSTM logic level FET Contents 1 1.1 1.2 1.3 1.4 2 3 4 4.1 5 6 7 8 9 10 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data. . . . . . . . . . . . . . . . . . . . . 1 Pinning information . . . . . . . . . . . . . . . . . . . . . . 1 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2 Thermal characteristics. . . . . . . . . . . . . . . . . . . 4 Transient thermal impedance . . . . . . . . . . . . . . 4 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 10 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 11 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 (c) Koninklijke Philips Electronics N.V. 2002. Printed in The Netherlands All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 22 March 2002 Document order number: 9397 750 09405 |
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