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| IRF840 Data Sheet July 1999 File Number 2312.3 8A, 500V, 0.850 Ohm, N-Channel Power MOSFET This N-Channel enhancement mode silicon gate power field effect transistor is an advanced power MOSFET designed, tested, and guaranteed to withstand a specified level of energy in the breakdown avalanche mode of operation. All of these power MOSFETs are designed for applications such as switching regulators, switching converters, motor drivers, relay drivers, and drivers for high power bipolar switching transistors requiring high speed and low gate drive power. These types can be operated directly from integrated circuits. Formerly developmental type TA17425. Features * 8A, 500V * rDS(ON) = 0.850 * Single Pulse Avalanche Energy Rated * SOA is Power Dissipation Limited * Nanosecond Switching Speeds * Linear Transfer Characteristics * High Input Impedance * Related Literature - TB334 "Guidelines for Soldering Surface Mount Components to PC Boards" Ordering Information PART NUMBER IRF840 NOTE: PACKAGE TO-220AB BRAND IRF840 Symbol D When ordering, include the entire part number. G S Packaging JEDEC TO-220AB TOP VIEW SOURCE DRAIN GATE DRAIN (FLANGE) 4-257 CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999 IRF840 Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified IRF840 500 500 8.0 5.1 32 20 125 1.0 510 -55 to 150 300 260 UNITS V V A A A V W W/oC mJ oC oC oC Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDS Drain to Gate Voltage (RGS = 20k) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID TC = 100oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VGS Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .PD Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single Pulse Avalanche Energy Rating (Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .EAS Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ , TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 125oC. Electrical Specifications PARAMETER TC = 25oC, Unless Otherwise Specified SYMBOL BVDSS VGS(TH) IDSS ID(ON) IGSS rDS(ON) gfs tD(ON) tr tD(OFF) tf Qg(TOT) Qgs Qgd CISS COSS CRSS LD Modified MOSFET Symbol Showing the Internal Devices Measured from the Drain Inductances D Lead, 6mm (0.25in) from Package to Center of Die LD Measured from the Source Lead, 6mm (0.25in) from Header to Source Bonding Pad G LS S TEST CONDITIONS VGS = 0V, ID = 250A (Figure 10) VGS = VDS, ID = 250A VDS = Rated BVDSS , VGS = 0V VDS = 0.8 x Rated BVDSS , VGS = 0V, TJ = 125oC VDS > ID(ON) x rDS(ON)MAX , VGS = 10V VGS = 20V VGS = 10V, ID = 4.4A (Figures 8, 9) VDS 50V, ID = 4.4A (Figure 12) VDD = 250V, ID 8A, RG = 9.1, RL = 30 MOSFET Switching Times are Essentially Independent of Operating Temperature. MIN 500 2.0 8.0 4.9 - TYP 0.8 7.4 15 21 50 20 42 7.0 22 1225 200 85 3.5 MAX 4.0 25 250 100 0.85 21 35 74 30 63 - UNITS V V A A A nA S ns ns ns ns nC nC nC pF pF pF nH Drain to Source Breakdown Voltage Gate to Threshold Voltage Zero-Gate Voltage Drain Current On-State Drain Current (Note 2) Gate to Source Leakage Current Drain to Source On Resistance (Note 2) Forward Transconductance (Note 2) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Total Gate Charge (Gate to Source + Gate to Drain) Gate to Source Charge Gate to Drain "Miller" Charge Input Capacitance Output Capacitance Reverse-Transfer Capacitance Internal Drain Inductance VGS = 10V, ID = 8A, VDS = 0.8 x Rated BVDSS Ig(REF) = 1.5mA (Figure 14) Gate Charge is Essentially Independent of Operating Temperature VGS = 0V, VDS = 25V, f = 1.0MHz (Figure 11) - Measured from the Contact Screw on Tab to Center of Die - - 4.5 - nH Internal Source Inductance LS - 7.5 - nH Thermal Resistance Junction to Case Thermal Resistance Junction to Ambient RJC RJA Free Air Operation - - 1.0 62.5 oC/W oC/W 4-258 IRF840 Source to Drain Diode Specifications PARAMETER Continuous Source to Drain Current Pulse Source to Drain Current (Note 3) SYMBOL ISD ISDM TEST CONDITIONS Modified MOSFET Symbol Showing the Integral Reverse P-N Junction Diode G D MIN - TYP - MAX 8.0 32 UNITS A A S Source to Drain Diode Voltage (Note 2) Reverse Recovery Time Reverse Recovered Charge NOTES: VSD trr QRR TJ = 25oC, ISD = 8.0A, VGS = 100A/s (Figure 13) TJ = 25oC, ISD = 8.0A, dISD/dt = 100A/s TJ = 25oC, ISD = 8.0A, dISD/dt = 100A/s 210 2.0 475 4.6 2.0 970 8.2 V ns C 2. Pulse Test: Pulse width 300s, duty cycle 2%. 3. Repetitive Rating: Pulse width limited by Max junction temperature. See Transient Thermal Impedance curve (Figure 3). 4. VDD = 50V, starting TJ = 25oC, L = 14mH, RG = 25, peak IAS = 8A. Typical Performance Curves 1.2 POWER DISSIPATION MULTIPLIER 1.0 Unless Otherwise Specified 10 0.8 0.6 0.4 0.2 0 ID , DRAIN CURRENT (A) 0 50 100 150 8 6 4 2 0 25 50 75 100 125 150 TC , CASE TEMPERATURE (oC) TC , CASE TEMPERATURE (oC) FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE 1 ZJC , NORMALIZED TRANSIENT 0.5 THERMAL IMPEDANCE 0.2 0.1 0.1 0.05 0.02 0.01 10-2 SINGLE PULSE PDM t1 t2 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJC x RJC + TC 10-4 10-3 10-2 0.1 t1 , RECTANGULAR PULSE DURATION (s) 1 10 10-3 -5 10 FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE 4-259 IRF840 Typical Performance Curves 102 10s ID, DRAIN CURRENT (A) 10 ID , DRAIN CURRENT (A) Unless Otherwise Specified (Continued) 15 VGS = 10V 12 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VGS = 6.0V 100s 1ms 9 VGS = 5.5V 6 1 OPERATION IN THIS REGION IS LIMITED BY rDS(ON) TC = 25oC TJ = MAX RATED SINGLE PULSE 1 10 102 10ms DC 3 VGS = 5.0V VGS = 4.5V VGS = 4.0V 200 250 0.1 103 0 0 50 100 150 VDS , DRAIN TO SOURCE VOLTAGE (V) VDS , DRAIN TO SOURCE VOLTAGE (V) FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. OUTPUT CHARACTERISTICS 15 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX ID , DRAIN CURRENT (A) 12 VGS = 6.0V VGS = 10V 100 ISD(ON), DRAIN TO SOURCE CURRENT (A) PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VDS 50V 10 9 1 TJ = 150oC 0.1 TJ = 25oC 6 VGS = 5.5V 3 VGS = 4.0V 0 0 VGS = 5.0V VGS = 4.5V 0.01 3 6 9 12 VDS , DRAIN TO SOURCE VOLTAGE (V) 15 0 2 4 6 8 VSD , GATE TO SOURCE VOLTAGE (V) 10 FIGURE 6. SATURATION CHARACTERISTICS FIGURE 7. TRANSFER CHARACTERISTICS 10 NORMALIZED DRAIN TO SOURCE ON RESISTANCE VOLTAGE PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX 3.0 rDS(ON) , DRAIN TO SOURCE ON RESISTANCE () 8 2.4 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX ID = 4.4A, VGS = 10V 6 VGS = 10V 4 1.8 1.2 2 VGS = 20V 0.6 0 0 8 32 16 24 TC , CASE TEMPERATURE (oC) 40 0 -60 -40 -20 0 20 40 60 80 100 120 140 160 TJ , JUNCTION TEMPERATURE (oC) FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs VOLTAGE AND DRAIN CURRENT FIGURE 9. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE 4-260 IRF840 Typical Performance Curves 1.25 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE ID = 250A Unless Otherwise Specified (Continued) 3000 VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS CDS + CGD 1.15 C, CAPACITANCE (pF) 2400 1.05 1800 CISS 1200 COSS 600 CRSS 0.95 0.85 0.75 -60 -40 -20 0 20 40 60 80 100 120 140 160 0 1 2 5 10 2 5 VDS , DRAIN TO SOURCE VOLTAGE (V) 102 TJ , JUNCTION TEMPERATURE (oC) FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE 15 gfs, TRANSCONDUCTANCE (S) ISD, SOURCE TO DRAIN CURRENT (A) 12 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VDS 50V 100 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX 10 TJ = 150oC 1.0 TJ = 25oC 9 TJ = 25oC TJ = 150oC 6 3 0 0 3 6 9 ID , DRAIN CURRENT (A) 12 15 0.1 0 1.2 0.3 0.6 0.9 VSD , SOURCE TO DRAIN VOLTAGE (V) 1.5 FIGURE 12. TRANSCONDUCTANCE vs DRAIN CURRENT FIGURE 13. SOURCE TO DRAIN DIODE VOLTAGE 20 VGS , GATE TO SOURCE VOLTAGE (V) ID = 8A 16 VDS = 100V 12 VDS = 250V VDS = 400V 8 4 0 0 12 24 36 48 60 Qg, GATE CHARGE (nC) FIGURE 14. GATE TO SOURCE VOLTAGE vs GATE CHARGE 4-261 IRF840 Test Circuits and Waveforms VDS BVDSS L VARY tP TO OBTAIN REQUIRED PEAK IAS VGS DUT tP RG IAS VDD tP VDS VDD + - 0V IAS 0.01 0 tAV FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 16. UNCLAMPED ENERGY WAVEFORMS tON td(ON) tr RL VDS + tOFF td(OFF) tf 90% 90% RG DUT - VDD 0 10% 90% 10% VGS VGS 0 10% 50% PULSE WIDTH 50% FIGURE 17. SWITCHING TIME TEST CIRCUIT FIGURE 18. RESISTIVE SWITCHING WAVEFORMS CURRENT REGULATOR VDS (ISOLATED SUPPLY) VDD SAME TYPE AS DUT Qg(TOT) Qgd Qgs D VDS VGS 12V BATTERY 0.2F 50k 0.3F G DUT 0 Ig(REF) 0 IG CURRENT SAMPLING RESISTOR S VDS ID CURRENT SAMPLING RESISTOR Ig(REF) 0 FIGURE 19. GATE CHARGE TEST CIRCUIT FIGURE 20. GATE CHARGE WAVEFORMS 4-262 IRF840 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 4-263 |
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