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 SI9145
Vishay Siliconix
SI9145
Low-Voltage Switchmode Controller
FEATURES
* 2.7-V to 7-V Input Operating Range * Voltage-Mode PWM Control * High-Speed, Source-Sink Output Drive (200 mA) * Internal Oscillator (up to 2 MHz) * Standby Mode * 0-100% Controllable Maximum Duty-Cycle
DESCRIPTION
The SI9145 switchmode controller IC is ideally suited for high efficiency dc/dc converters in low input voltage systems. Operation is guaranteed down to 2.7 V, with a minimum startup voltage of 3.0 V making the SI9145 ideal for use with NiCd, NMH, and lithium ion battery packs. A mode select pin allows the output driver polarity to be programmed allowing the device to function as a step-up or step-down converter. Features include a precision bandgap reference, a wide bandwidth error amplifier, a 2-MHz oscillator, an input voltage monitor with standby mode and a 200-mA output driver. Supply current in normal operation is typically 1.1 mA and 250 A in standby mode. The SI9145 implements conventional voltage mode control. The maximum duty cycle in boost mode can be limited by voltage on DMAX/SS pin. Frequency can be externally programmed by selection of ROSC and COSC. The SI9145 is available in 16-pin SOIC and TSSOP packages and is specified over the industrial temperature range (-25C to 85C).
FUNCTIONAL BLOCK DIAGRAM
PentiumTM is a trademark of Intel Corporation. PowerPCTM is a trademark of IBM.
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S-60752--Rev. H, 05-Apr-99 1
SI9145
Vishay Siliconix
ABSOLUTE MAXIMUM RATINGS
Voltages Referenced to GND. VDD, VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 V PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.3 V VDD to VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V Linear Inputs . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3 V to VDD to +0.3 V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3 V to VDD to +0.3 V Continuous Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . .100 mA Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 to 125C Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . 150C Power Dissipation (Package)a 16-Pin SOIC (Y Suffix)b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 900 mW 16-Pin TSSOP (Q Suffix)c . . . . . . . . . . . . . . . . . . . . . . . . . . . 925 mW Thermal Impedance (JA) 16-Pin SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140C/W 16-Pin TSSOP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135C/W Notes a. Device mounted with all leads soldered or welded to PC board. b. Derate 7.2 mW/C above 25C. c. Derate 7.4 mW/C above 25C.
RECOMMENDED OPERATING RANGE
Voltages Referenced to GND. VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7 V to 7 V VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7 V to 7 V fOSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 kHz to 2 MHz ROSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 k to 250 k COSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 pF to 200 pF Linear Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to VDD Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to VDD VREF Load Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >150 k
SPECIFICATIONS
Test Conditions Unless Otherwise Specifieda Parameter Reference
Output Voltage VREF IREF = -10 A TA = 25C 1.455 1.477 1.50 1.545 1.523 V
Limits
B Suffix - 25 to 85C
Symbol
2.7 V VDD 7 V, VDD = VS GND = PGND
Minb
Typ
Maxb
Unit
Oscillator
Maximum Frequencyc Accuracy ROSC Voltage Minimum Start-Up Voltage 50% DMAX/SS 100% DMAX/SS DMAX/SS Input Current Voltage Stabilityc Temperature Stabilityc fMAX fOSC VROSC VDDOSC VDMAX 50% VDMAX 100% IDMAX 3.0 1.25 MODE SELECT = VDD 1.54 DMAX = 0 to VDD 2.7 V VDD 7 V, Ref to 4.8 V f/f 2.7 V VDD 4.2 V, Ref to 3.5 V 3.8 V VDD 5.6 V, Ref to 4.7 V Referenced to 25C TA = 25C -100 -16 -8 -7 5 100 16 8 7 % nA V VCC = 3.0 V, COSC = 47 pF, ROSC = 5.0 k VCC = 3.0 V COSC = 100 pF, ROSC = 6.98 k TA = 25C 2.0 0.85 1.0 1.0 1.15 MHz
Error Amplifier (COSC = GND, OSC Disabled)
Input Bias Current Open Loop Voltage Gain Offset Voltage Unity Gain Bandwidthc Output Current Power Supply Rejectionc IFB AVOL VOS BW IEA PSRR Source (VFB = 1 V, NI = VREF) Sink (VFB = 2 V, NI = VREF) 2.7 V < VDD < 7.0 V 0.4 VNI = VREF VNI = VREF , VFB = 1.0 V -1.0 47 -15 55 0 10 -2.0 0.8 60 -1.0 15 1.0 A dB mV MHz mA dB
S-60752--Rev. H, 05-Apr-99 2
FaxBack 408-970-5600, request 70021 www.siliconix.com
SI9145
Vishay Siliconix
SPECIFICATIONS
Test Conditions Unless Otherwise Specifieda Parameter UVLOSET Voltage Monitor
Under Voltage Lockout Hysterisis UVLO Input Current VUVLOHL VUVLOLH VHYS IUVLO UVLOSET High to Low UVLOSET Low to High VUVLOLH - VUVLOHL VUVLO = 0 to VDD -100 0.85 1.0 1.2 200 100 1.15 V mV nA
Limits
B Suffix - 25 to 85C
Symbol
2.7 V VDD 7 V, VDD = VS GND = PGND
Minb
Typ
Maxb
Unit
Output
Output High Voltage Output Low Voltage Peak Output Current Peak Output Current VOH VOL ISOURCE ISINK VDD = 2.7 V, IOUT = -10 mA VDD = 2.7 V, IOUT = 10 mA VDD = 2.7 V, VOUT = 0 V VDD = 2.7 V, VOUT = 2.7 V 150 2.55 2.60 0.06 -180 200 0.15 -130 V
mA
Logic
ENABLE Delay to Output ENABLE Logic Low ENABLE Logic High ENABLE Input Current MODE SELECT Logic Low MODE SELECT Logic High MODE SELECT Input Current tdEN VENL VENH IEN VMODEL VMODEH IMODE MODE SELECT = 0 to VDD 0.8 VDD -1.0 1.0 ENABLE = 0 to VDD 0.8 VDD -1.0 1.0 0.2 VDD ENABLE Rising to OUTPUT 1.5 0.2 VDD s V A V A C 0.15 V
Over Temperature Sense
Trip Point Output Low Voltage Output High Voltage TTRIP VOTSL VOTSH VDD = 2.7 V, IOUT = 1 A VDD = 2.7 V, IOUT = -1 A 2.55 150 0.06 2.6
Supply
Supply Current - Normal Mode Supply Current - Standby Mode Notes a. CSTRAY < 5 pF on COSC. After Start-Up, VDD of 3 V. b. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. c. Guaranteed by design, not subject to production testing. VDD = 2.7 V, fOSC = 1 MHz, ROSC = 6.98 k IDD VDD = 7 V, fOSC = 1 MHz, ROSC = 6.98 k ENABLE = Low 1.1 1.6 250 1.5 2.3 330 mA A
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S-60752--Rev. H, 05-Apr-99 3
SI9145
Vishay Siliconix
TYPICAL CHARACTERISTICS (25C UNLESS OTHERWISE NOTED)
S-60752--Rev. H, 05-Apr-99 4
FaxBack 408-970-5600, request 70021 www.siliconix.com
SI9145
Vishay Siliconix
TYPICAL CHARACTERISTICS (25C UNLESS OTHERWISE NOTED)
FaxBack 408-970-5600, request 70021 www.siliconix.com
S-60752--Rev. H, 05-Apr-99 5
SI9145
Vishay Siliconix
TYPICAL CHARACTERISTICS (25C UNLESS OTHERWISE NOTED)
S-60752--Rev. H, 05-Apr-99 6
FaxBack 408-970-5600, request 70021 www.siliconix.com
SI9145
Vishay Siliconix
TIMING WAVEFORMS
FIGURE 1. SI9145 Timing Diagram (MODE SELECT = High)
FIGURE 2. SI9145 Timing Diagram (MODE SELECT = Low)
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S-60752--Rev. H, 05-Apr-99 7
SI9145
Vishay Siliconix
PIN CONFIGURATIONS
PIN DESCRIPTION
Pin 1: VDD The positive power supply for all functional blocks except output driver. A bypass capacitor of 0.1 F (minimum) is recommended. Pin 2: MODE SELECT This pin is used to enable maximum duty cycle limit and set output polarity of controller. When connected to VDD, the maximum duty cycle function is controlled by the DMAX/SS pin. The maximum duty cycle limit is usually used for forward, flyback, and boost converters. The output polarity is high when the PWM circuitry requires the external device to be turned on. When connected to GND, the maximum duty cycle is not limited (usually for buck converters driving a p-channel MOS). The output polarity is low when the PWM circuitry requires the external PMOS to be turned on. Pin 3: DMAX/SS DMAX/SS pin controls the maximum duty cycle achievable by the PWM circuitry when the MODE SELECT = VDD. When DMAX/SS is at less than 1.0 V (typical) the OUTPUT is held low (0% duty cycle). When DMAX/SS is at more than 1.5 V (typical), the PWM circuitry can achieve 100% duty cycle. With voltage at DMAX/SS between 1.0 V and 1.5 V, the maximum duty cycle is proportionally limited to this voltage. The addition of external components can implement a soft start function. Pin 5: FB The inverting input of the error amplifier. External resistors are connected to this pin to set the regulated output voltage. The compensation network is also connected to this pin. Pin 6: NI The non-inverting input of the error amplifier. In normal operation it is externally connected to the VREF pin. Pin 7: VREF This pin supplies 1.5 V trimmed to 1.5%. The reference voltage is generated by a band-gap reference. Pin 8: GND Negative return for VDD. Pin 9: ROSC This pin is the equivalent of a 1.0-V voltage source derived from the on-chip VREF. When a low T.C. resistor is externally connected from this pin to GND, a temperature independent current is generated internally. This current is used as the charging current source connected to the COSC pin. The current is internally multiplied by 2 and is used as the discharging current source connected to the COSC pin.
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Pin 4: COMP This pin is the output of the error amplifier. A compensation network is connected from this pin to the FB pin to stabilize the system. This pin drives one input of the internal pulse width modulation comparator.
S-60752--Rev. H, 05-Apr-99 8
SI9145
Vishay Siliconix
Therefore, the external resistor is one of the factors that determine the oscillator frequency. Pin 10: COSC An external capacitor is connected to this pin to set the oscillator frequency. Internal current sources alternately charge and discharge the external capacitor. The oscillator waveform is a symmetrical triangular type with a typical voltage swing between 1.0 V and 1.5 V.
0.9 f OSC ----------------------------------R OSC x C OSC
operation is disabled, supply current is reduced, the oscillator stops and the output is held high for MODE SELECT = low, and low for MODE SELECT = high. Pin 13: UVLOSET This pin will place the chip in the standby mode if the UVLOSET voltage drops below 1.2 V. Once the UVLOSET voltage exceeds 1.2 V, the chip operates normally. There is a built-in hysteresis of 200 mV. Pin 14: PGND The negative return for the VS supply.
Pin 11: OTS This pin indicates an over-temperature condition on the device when the output is low. The output is latched low and is reset with the ENABLE pin going low then high, or by turning power off and on. Pin 12: ENABLE A logic high on this pin allows normal operation. A logic low places the chip in the standby mode. In standby mode normal
Pin 15: OUTPUT This CMOS push-pull output pin drives the external MOSFET and is capable of sinking 150 mA or sourcing 130 mA with VS equal to 2.7 V. Pin 16: VS The positive terminal of the power supply which powers the CMOS output driver. A bypass capacitor is required.
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S-60752--Rev. H, 05-Apr-99 9
SI9145
Vishay Siliconix
APPLICATIONS
FIGURE 3. Non-Isolated Step Up Boost Converter for VOUT > VIN
FIGURE 4. Non-Isolated Step Down Buck Converter for VOUT < VIN
FIGURE 5. Non-Isolated Synchronous Buck Converter for VOUT < VIN
S-60752--Rev. H, 05-Apr-99 10
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