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PLL520-28/-29
Low Phase Noise VCXO (for 120-200MHz Fund Xtal)
FEATURES
* * * * * * * * 120MHz to 200MHz Fundamental Mode Crystal. Output range: 120 - 200MHz (no PLL). Low Injection Power for crystal 50uW. Sub 0.5pS RMS phase jitter ( 12kHz to 20MHz ). PECL (PLL520-28) or LVDS output (PLL520-29). Integrated variable capacitors. Supports 2.5V or 3.3V-Power Supply. Available in 16-Pin (TSSOP or 3x3mm QFN).
PIN CONFIGURATION (Top View)
VDD XIN XOUT N/C N/C
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
N/C N/C GND CLKC VDD CLKT N/C N/C
PLL 520-2x
DESCRIPTION
The PLL520-28/-29 are a family of VCXO IC's specifically designed to pull high frequency fundamental crystals. They achieve very low current into the crystal resulting in better overall stability. Their internal varicaps allow an on chip frequency pulling, controlled by the VCON input. Their very low jitter makes them ideal for the most demanding timing requirements.
OE VCON GND
VDD
VDD
N/C
10
XIN XOUT N/C OE
12 13 14 15 16 1
11
N/C
9
8 7 6 5
GND CLKC VDD CLKT
P520-2x
2 3 4
GND
GND
OE VCON Oscillator XIN XOUT Q Q
OUTPUT ENABLE LOGICAL LEVELS
Part # PLL520-28 PLL520-29 OE 0 (Default) 1 0 1 (Default) State Output enabled Tri-state Tri-state Output enabled
Amplifier w/ integrated varicaps
PLL520-28/-29
OE input: Logical states defined by PECL levels for PLL520-28 Logical states defined by CMOS levels for PLL520-29
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 1
VCON
GND
BLOCK DIAGRAM
PLL520-28/-29
Low Phase Noise VCXO (for 120-200MHz Fund Xtal)
PIN DESCRIPTIONS
Name
XIN XOUT OE VCON GND CLKT CLKC N/C VDD
TSSOP Pin number
2 3 6 7 8, 14 11 13 4,5,9,10,15,16 1, 12
3x3mm QFN Pin number
13 14 16 1 2,3,4,8 5 7 9,10,15 6,11,12
Type
I I I I P O O P
Description
Crystal input. See Crystal Specifications on page 2. Crystal output. See Crystal Specifications on page 2. Output enable pin. See Output Enable Logic Levels on page 1. Voltage control input. Ground. True output PECL (PLL520-28) or LVDS (PLL520-29) Complementary output PECL (PLL520-28) or LVDS (PLL520-29). Not connected. +3.3V power supply.
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings PARAMETERS
Supply Voltage Input Voltage, dc Output Voltage, dc Storage Temperature Ambient Operating Temperature* Junction Temperature Lead Temperature (soldering, 10s) ESD Protection, Human Body Model
SYMBOL
VDD VI VO TS TA TJ
MIN.
-0.5 -0.5 -65 -40
MAX.
4.6 VDD+0.5 VDD+0.5 150 85 125 260 2
UNITS
V V V C C C C kV
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. * Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only.
2. Crystal Specifications PARAMETERS
Built-in Capacitance Inter-electrode capacitance C0/C1 ratio (gamma) Oscillation Frequency
SYMBOL
CX+ CXC0 OF
CONDITIONS
120MHz to 200MHz (VDD=3.3V)
MIN.
MAX.
2 2 2 300 200
UNITS
pF MHz
Fund.
120
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 2
PLL520-28/-29
Low Phase Noise VCXO (for 120-200MHz Fund Xtal)
3. Voltage Control Crystal Oscillator (3.3V) PARAMETERS
VCXO Stabilization Time * VCXO Tuning Range CLK output pullability On-chip Varicaps control range Linearity VCXO Tuning Characteristic VCON input impedance VCON modulation BW
SYMBOL
TVCXOSTB
CONDITIONS
From power valid FXIN = 100 - 200MHz; XTAL C0/C1 < 250 0V VCON 3.3V VCON=1.65V, 1.65V VCON = 0 to 3.3V
MIN.
TYP.
MAX.
10
UNITS
ms ppm ppm pF % ppm/V k kHz
200* 100* 4 - 18* 10* 65 60
0V VCON 3.3V, -3dB
25
Note: Parameters denoted with an asterisk (*) represent nominal characterization data and are not production tested to any specific limits.
4. General Electrical Specifications PARAMETERS
Supply Current (Loaded Outputs) Operating Voltage Output Clock Duty Cycle Short Circuit Current
SYMBOL
IDD VDD
CONDITIONS
PECL/LVDS @ 1.25V (LVDS) @ VDD - 1.3V (PECL)
MIN.
TYP.
MAX.
100/80
UNITS
mA V % mA
2.97 45 45
50 50 50
3.63 55 55
5. Jitter Specifications PARAMETERS
Period jitter RMS Period jitter peak-to-peak Accumulated jitter RMS Accumulated jitter peak-to-peak Integrated jitter RMS at 155MHz
CONDITIONS
At 155.52MHz, with capacitive decoupling between VDD and GND. At 155.52MHz, with capacitive decoupling between VDD and GND. Over 10,000 cycles. Integrated 12 kHz to 20 MHz
MIN.
TYP.
2.5 18.5 2.5 24 0.3
MAX.
UNITS
ps ps ps
6. Phase Noise Specifications PARAMETERS
Phase Noise relative to carrier
FREQUENCY
155.52MHz
@10Hz
-75
@100Hz
-95
@1kHz
-125
@10kHz
-140
@100kHz
-145
UNITS
dBc/Hz
Note: Phase Noise measured at VCON = 0V
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 3
PLL520-28/-29
Low Phase Noise VCXO (for 120-200MHz Fund Xtal)
7. LVDS Electrical Characteristics PARAMETERS
Output Differential Voltage VDD Magnitude Change Output High Voltage Output Low Voltage Offset Voltage Offset Magnitude Change Power-off Leakage Output Short Circuit Current
SYMBOL
VOD VOD VOH VOL VOS VOS IOXD IOSD
CONDITIONS
MIN.
247 -50
TYP.
355 1.4 1.1 1.2 3 1 -5.7
MAX.
454 50 1.6 1.375 25 10 -8
UNITS
mV mV V V V mV uA mA
RL = 100 (see figure)
0.9 1.125 0
Vout = VDD or GND VDD = 0V
8. LVDS Switching Characteristics PARAMETERS
Differential Clock Rise Time Differential Clock Fall Time
LVDS Levels Test Circuit
OUT
SYMBOL
tr tf
CONDITIONS
RL = 100 CL = 10 pF (see figure)
MIN.
0.2 0.2
TYP.
0.7 0.7
MAX.
1.0 1.0
UNITS
ns ns
LVDS Switching Test Circuit
OUT
50
CL = 10pF
VOD
VOS
VDIFF
RL = 100
50 CL = 10pF OUT OUT
LVDS Transistion Time Waveform
OUT 0V (Differential) OUT
80% VDIFF 20% 0V
80%
20%
tR
tF
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 4
PLL520-28/-29
Low Phase Noise VCXO (for 120-200MHz Fund Xtal)
9. PECL Electrical Characteristics PARAMETERS
Output High Voltage Output Low Voltage
SYMBOL
VOH VOL
CONDITIONS
RL = 50 to (VDD - 2V) (see figure)
MIN.
VDD - 1.025
MAX.
VDD - 1.620
UNITS
V V
10. PECL Switching Characteristics PARAMETERS
Clock Rise Time Clock Fall Time
SYMBOL
tr tf
CONDITIONS
@20/80% - PECL @80/20% - PECL
MIN.
TYP.
0.6 0.5
MAX.
1.5 1.5
UNITS
ns ns
PECL Levels Test Circuit
OUT VDD OUT
PECL Output Skew
50
2.0V 50%
50 OUT OUT tSKEW
PECL Transistion Time Waveform
DUTY CYCLE
45 - 55%
55 - 45%
OUT 80% 50% 20% OUT tR tF
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 5
PLL520-28/-29
Low Phase Noise VCXO (for 120-200MHz Fund Xtal)
PACKAGE INFORMATION
16 PIN TSSOP ( mm )
Symbol A A1 B C D E H L e Min. Max. 1.20 0.05 0.15 0.19 0.30 0.09 0.20 4.90 5.10 4.30 4.50 6.40 BSC 0.45 0.75 0.65 BSC E H
D
A A1 e B C L
3x3mm QFN
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 6
PLL520-28/-29
Low Phase Noise VCXO (for 120-200MHz Fund Xtal)
ORDERING INFORMATION
For part ordering, please contact our Sales Department:
47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991
PART NUMBER
The order number for this device is a combination of the following: Device number, Package type and Operating temperature range
PLL520-2x O C
PART NUMBER TEMPERATURE C=COMMERCIAL I=INDUSTRAL
PACKAGE TYPE O=TSSOP Q=QFN
Order Number PLL520-28OC PLL520-28OC-R PLL520-28QC PLL520-28QC-R PLL520-29OC PLL520-29OC-R PLL520-29QC PLL520-29QC-R
Marking P520-28OC P520-28OC P520-28QC P520-28QC P520-29OC P520-29OC P520-29QC P520-29QC
Package Option TSSOP - Tube TSSOP - Tape & Reel QFN - Tube QFN - Tape & Reel TSSOP - Tube TSSOP - Tape & Reel QFN - Tube QFN - Tape & Reel
PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: PhaseLink's products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 7

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