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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
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1:10 LVCMOS Zero Delay Clock Buffer
The MPC9608 is a 2.5V and 3.3V compatible, 1:10 PLL based zero-delay buffer. With a very wide frequency range and low output skews the MPC9608 is targeted for high performance and mid-range clock tree designs. Features * 1:10 outputs LVCMOS zero-delay buffer
MPC9608
Ambient Temperature Range -40C to +85C 32-LEAD LQFP PACKAGE CASE 873A Functional Description The MPC9608 uses an internal PLL and an external feedback path to lock its low-skew clock output phase to the reference clock phase, providing virtually zero propagation delay. This enables nested clock designs with near-zero insertion delay. Designs using the MPC9608 as PLL fanout buffer will show significantly lower clock skew than clock distributions developed from traditional fanout buffers. The device offers one reference clock input and two banks of 5 outputs for clock fanout. The input frequency and phase is reproduced by the PLL and provided at the outputs. A selectable frequency divider sets the bank B outputs to generate either an identical copy of the bank A clocks or one half of the bank A clock frequency. Both output banks remain synchronized to the input reference for both bank B configurations. Outputs are only disabled or enabled when the outputs are already in logic low state (CLK_STOP). For system test and diagnosis, the MPC9608 outputs can also be set to high-impedance state by connecting OE to logic high level. Additionally, the device provides a PLL bypass mode for low frequency test purpose. In PLL bypass mode, the minimum frequency and static phase offset specification do not apply. CLK_STOP and OE do not affect the PLL feedback output (QFB) and down stream clocks can be disabled without the internal PLL losing lock. The MPC9608 is fully 2.5V or 3.3V compatible and requires no external components for the internal PLL. All inputs accept LVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50 transmission lines on the incident edge. For series terminated transmission lines, each of the MPC9608 outputs can drive one or two traces giving the devices an effective fanout of 1:20. The device is packaged in a 7x7 mm2 32-lead LQFP package.
* * * * * * * * * * * *
LOW VOLTAGE 3.3V/2.5V LVCMOS 1:10 ZERO-DELAY CLOCK BUFFER
Single 3.3V or 2.5V supply 150 ps maximum output skew1 100 ps static phase offset (SPO)1 Supports a clock I/O frequency range of 12.5 to 200 MHz Selectable divide-by-two for one output bank Synchronous output enable control (CLK_STOP) Output tristate control (output high impedance) PLL bypass mode for low frequency system test purpose Supports networking, telecommunications and computer applications Supports a variety of microprocessors and controllers Compatible to PowerQuicc I and II
FA SUFFIX
1.
Final AC specifications pending final device characterization.
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.
07/01
(c) Motorola, Inc. 2001
1
REV 0
MPC9608
Bank A
CCLK
QA0 QA1
STOP
CCLK
25k
Ref
PLL
00: 100-200 MHz 01: 50-100 MHz 10: 25- 50 MHz 11:12.5- 25 MHz VCO
QA2 QA3
FB_IN
25k
FB
QA4
Bank B 2
/2
F_RANGE[0:1]
25k
QB0 QB1
PLL_EN
25k
QB2 QB3
CLK_STOP
25k
QB4
PLL feedback
BSEL
25k
QFB
OE
25k
Figure 1. MPC9608 Logic Diagram
F_RANGE0 F_RANGE1 CLK_STOP
BSEL
GND
24 VCC QA4 QA3 QA2 GND QA1 QA0 VCC 25 26 27 28 29 30 31 32 1
23
22
21
20
19
18
17 16 15 14 VCC QB4 QB3 QB2 GND QB1 QB0 VCC
GND 13 12 11 10 9 8 GND
VCC
MPC9608 (Pinout subject to change)
2
3
4
5
6
PLL_EN
CCLK
VCCA
GND
VCC
FB_IN
Figure 2. MPC9608 32-Lead Package Pinout (Top View)
MOTOROLA
2
QFB
OE 7
TIMING SOLUTIONS
MPC9608
TABLE 1: PIN CONFIGURATION
Pin CCLK FB_IN F_RANGE[0:1] BSEL PLL_EN OE CLK_STOP QA0-4, QB0-4 QFB GND VCCA VCC I/O Input Input Input Input Input Input Input Output Output Supply Supply Supply Type LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS Ground VCC VCC PLL reference clock signal PLL feedback signal input, connect to a QFB output PLL frequency range select Frequency divider select for bank B outputs PLL enable/disable Output enable/disable (high-impedance tristate) Synchronous clock enable/stop Clock outputs PLL feedback signal output. Connect to FB_IN Negative power supply PLL positive power supply (analog power supply). The MPC9608 requires an external RC filter for the analog power supply pin VCCA. Please see applications section for details. Positive power supply for I/O and core Function
TABLE 2: FUNCTION TABLE
Control F_RANGE[0:1] BSEL CLK_STOP OE Default 00 0 0 0 fQB0-4 = fQA0-4 Outputs enabled Outputs enabled (active) 0 1 fQB0-4 = fQA0-4 / 2 Outputs synchronously stopped in logic low state Outputs disabled (high-impedance state), independent on CLK_STOP. Applying OE=1 and PLL_EN=1 resets the device. The PLL feedback output QFB is not affected by OE. Test mode with PLL disabled. CCLK is substituted for the internal VCO output. MPC9608 is fully static and no minimum frequency limit applies. All PLL related AC characteristics are not applicable. Applying OE=1 and PLL_EN=1 resets the device. PLL frequency range. See Table 3 "Clock frequency configuration for QFB connected to FB_IN"
PLL_EN
0
Normal operation mode with PLL enabled.
TABLE 3: Clock Frequency Configuration for QFB connected to FB_IN
F RANGE[0] F_RANGE[0] 0 0 0 0 1 1 1 1 F RANGE[1] F_RANGE[1] 0 0 1 1 0 0 1 1 BSEL 0 1 0 1 0 1 0 1 fREF ( (CCLK) ) range [MHz] 100.0--200.0 100 0--200 0 50.0--100.0 50 0--100 0 25.0--50.0 25 0--50 0 12.5--25.0 12 5--25 0 QA0-QA4 Ratio fREF fREF fREF fREF fQA0-4 [MHz] 100.0--200.0 100 0--200 0 50.0--100.0 50 0--100 0 25.0--50.0 25 0--50 0 12.5--25 12 5--25 Ratio fREF fREF / 2 fREF fREF / 2 fREF fREF / 2 fREF fREF / 2 QB0-B4 fQB0-4 [MHz] 100.0--200.0 50.0--25.0 50.0--100.0 25.0--50.0 25.0--50.0 12.5--25.0 12.5--25.0 50.0--100 QFB fREF fREF fREF fREF fREF fREF fREF fREF
TIMING SOLUTIONS
3
MOTOROLA
MPC9608
TABLE 4: GENERAL SPECIFICATIONS
Symbol VTT MM HBM LU CPD CIN Characteristics Output termination voltage ESD protection (Machine model) ESD protection (Human body model) Latch-up immunity Power dissipation capacitance Input capacitance 200 2000 200 10 4.0 Min Typ VCC / 2 Max Unit V V V mA pF pF Per output Inputs Condition
TABLE 5: ABSOLUTE MAXIMUM RATINGSa
Symbol VCC VIN VOUT IIN IOUT TS Supply Voltage DC Input Voltage DC Output Voltage DC Input Current DC Output Current Storage temperature -65 Characteristics Min -0.3 -0.3 -0.3 Max 3.6 VCC+0.3 VCC+0.3 20 50 125 Unit V V V mA mA C Condition
a. Absolute maximum continuos ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied.
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TIMING SOLUTIONS
MPC9608
TABLE 6: DC CHARACTERISTICS (VCC = 3.3V 5%, TA = -40 to 85C)
Symbol VIH VIL VOH VOL ZOUT IIN Characteristics Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Output Impedance Input Currentb 14 - 17 200 2.4 0.55 0.30 Min 2.0 Typ Max VCC + 0.3 0.8 Unit V V V V V Condition LVCMOS LVCMOS IOH=-24 mAa IOL= 24 mA IOL= 12 mA VIN = VCC or GND VCCA Pin
W
A
ICCA Maximum PLL Supply Current 3.0 5.0 mA ICCQ Maximum Quiescent Supply Current 1.0 mA All VCC Pins a. The MPC9608 is capable of driving 50 transmission lines on the incident edge. Each output drives one 50 parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50 series terminated transmission lines. b. Inputs have pull-down resistors affecting the input current.
TABLE 7: AC CHARACTERISTICS (VCC = 3.3V 5%, TA = -40 to 85C)a b
Symbol fref Characteristics Input reference frequency in PLL modec F_RANGE = 00 F_RANGE = 01 F_RANGE = 10 F_RANGE = 11 Input reference frequency in PLL bypass moded F_RANGE = 00 F_RANGE = 01 F_RANGE = 10 F_RANGE = 11 Min 100 50 25 12.5 0 100 50 25 12.5 25 Typ Max 200 100 50 25 TBD 200 100 50 25 75 1.0 100 Unit MHz MHz MHz MHz MHz MHz MHz MHz MHz % ns ps 0.8 to 2.0V PLL locked BSEL = 0 BSEL = 0 BSEL = 0 BSEL = 0 Condition
fMAX
Output Frequencye
frefDC tr, tf t()
Reference Input Duty Cycle CCLK Input Rise/Fall Time Propagation Delay (static phase offset) CCLK to FB_IN F_RANGE = 00 F_RANGE = 01 F_RANGE = 10 F_RANGE = 11 Output-to-Output Skewf Output Duty Cycle Output Rise/Fall Time Output Disable Time Output Enable Time Cycle-to-cycle jitter Period Jitter I/O Phase Jitter Setup time, CLK_STOP to CCLK Hold time, CCLK to CLK_STOP PLL closed loop bandwidthh RMS (1
tsk(o) DC tr, tf tPLZ, HZ tPZL, LZ tJIT(CC) tJIT(PER) tJIT() tS tH BW
150 45 0.1 50 55 1.0 10 10 15 10 TBD 100 100
ps % ns ns ns ps ps ps ps ps BSEL = 0 BSEL = 0 BSEL = 0 0.55 to 2.4V
s)g RMS (1 s) RMS (1 s)
F_RANGE = 00 F_RANGE = 01 F_RANGE = 10 F_RANGE = 11
TBD TBD TBD TBD
kHz kHz kHz kHz
a. b. c. d. e. f. g. h.
tLOCK Maximum PLL Lock Time 10 ms All AC characteristics are design targets and subject to change upon device characterization. AC characteristics apply for parallel output termination of 50 to VTT. PLL mode requires PLL_EN = 0 to enable the PLL and zero-delay operation. In bypass mode, the MPC9608 divides the input reference clock. Applies for bank A and for bank B if BSEL = 0. If BSEL = 1, the min. and max. output frequency of bank B must be divided by two. See application section for part-to-part skew calculation. See application section for a jitter calculation for other confidence factors than 1 -3 dB point of PLL transfer characteristics.
s.
TIMING SOLUTIONS
5
MOTOROLA
MPC9608
TABLE 8: DC CHARACTERISTICS (VCC = 2.5V 5%, TA = -40 to 85C)
Symbol VIH VIL VOH VOL ZOUT IIN ICCA ICCQ a. Characteristics Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Output Impedance Input Current Maximum PLL Supply Current 2.0 17 - 20 200 5.0 Min 1.7 -0.3 1.8 0.6 Typ Max VCC + 0.3 0.7 Unit V V V V Condition LVCMOS LVCMOS IOH=-15 mAa IOL= 15 mA VIN = VCC or GND VCCA Pin
W
A mA
Maximum Quiescent Supply Current 1.0 mA All VCC Pins The MPC9608 is capable of driving 50 transmission lines on the incident edge. Each output drives one 50 parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50 series terminated transmission lines per output. Characteristics Input reference frequency in PLL modec F_RANGE = 00 F_RANGE = 01 F_RANGE = 10 F_RANGE = 11 Input reference frequency in PLL bypass moded F_RANGE = 00 F_RANGE = 01 F_RANGE = 10 F_RANGE = 11 Min 100 50 25 12.5 0 100 50 25 12.5 25 Typ Max 200 100 50 25 TBD 200 100 50 25 75 1.0 100 Unit MHz MHz MHz MHz MHz MHz MHz MHz MHz % ns ps 0.7 to 1.7V PLL locked BSEL = 0 BSEL = 0 BSEL = 0 BSEL = 0 Condition
TABLE 9: AC CHARACTERISTICS (VCC = 2.5V 5%, TA = -40 to 85C)a b
Symbol fref
fMAX
Output Frequencye
frefDC tr, tf t()
Reference Input Duty Cycle CCLK Input Rise/Fall Time Propagation Delay (static phase offset) CCLK to FB_IN F_RANGE = 00 F_RANGE = 01 F_RANGE = 10 F_RANGE = 11 Output-to-Output Skewf Output Duty Cycle Output Rise/Fall Time Output Disable Time Output Enable Time Cycle-to-cycle jitter Period Jitter I/O Phase Jitter Setup time, CLK_STOP to CCLK Hold time, CCLK to CLK_STOP PLL closed loop bandwidthh RMS (1
tsk(o) DC tr, tf tPLZ, HZ tPZL, LZ tJIT(CC) tJIT(PER) tJIT() tS tH BW
150 45 0.1 50 55 1.0 10 10 15 10 TBD 100 100
ps % ns ns ns ps ps ps ps ps BSEL = 0 BSEL = 0 BSEL = 0 0.6 to 1.8V
s)g RMS (1 s) RMS (1 s)
F_RANGE = 00 F_RANGE = 01 F_RANGE = 10 F_RANGE = 11
TBD TBD TBD TBD
kHz kHz kHz kHz
a. b. c. d. e. f. g. h.
tLOCK Maximum PLL Lock Time 10 ms All AC characteristics are design targets and subject to change upon device characterization. AC characteristics apply for parallel output termination of 50 to VTT. PLL mode requires PLL_EN = 0 to enable the PLL and zero-delay operation. In bypass mode, the MPC9608 divides the input reference clock. Applies for bank A and for bank B if BSEL = 0. If BSEL = 1, the min. and max. output frequency of bank B must be divided by two. See application section for part-to-part skew calculation. See application section for a jitter calculation for other confidence factors than 1 -3 dB point of PLL transfer characteristics.
s.
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TIMING SOLUTIONS
MPC9608
APPLICATIONS INFORMATION
Power Supply Filtering The MPC9608 is a mixed analog/digital product. Its analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. Random noise on the VCCA (PLL) power supply impacts the device characteristics, for instance I/O jitter. The MPC9608 provides separate power supplies for the output buffers (VCC) and the phase-locked loop (VCCA) of the device.The purpose of this design technique is to isolate the high switching noise digital outputs from the relatively sensitive internal analog phase-locked loop. In a digital system environment where it is more difficult to minimize noise on the power supplies a second level of isolation may be required. The simple but effective form of isolation is a power supply filter on the VCCA pin for the MPC9608. Figure 3. illustrates a typical power supply filter scheme. The MPC9608 frequency and phase stability is most susceptible to noise with spectral content in the 100kHz to 20MHz range. Therefore the filter should be designed to target this range. The key parameter that needs to be met in the final filter design is the DC voltage drop across the series filter resistor RF. From the data sheet the ICCA current (the current sourced through the VCCA pin) is typically 3 mA (5 mA maximum), assuming that a minimum of 2.325V (VCC=3.3V or VCC=2.5V) must be maintained on the VCCA pin. The resistor RF shown in Figure 3. "VCCA Power Supply Filter" must have a resistance of 270W (VCC=3.3V) or 9-10W (VCC=2.5V) to meet the voltage drop criteria.
RF = 270 for VCC = 3.3V RF = 9-10 for VCC = 2.5V RF VCC CF 10 nF CF = 1 F for VCC = 3.3V CF = 22 F for VCC = 2.5V
overall performance is being degraded due to system power supply noise. The power supply filter schemes discussed in this section should be adequate to eliminate power supply noise related problems in most designs. Using the MPC9608 in zero-delay applications Nested clock trees are typical applications for the MPC9608. Designs using the MPC9608 as LVCMOS PLL fanout buffer with zero insertion delay will show significantly lower clock skew than clock distributions developed from CMOS fanout buffers. The external feedback option of the MPC9608 clock driver allows for its use as a zero delay buffer. By using the QFB output as a feedback to the PLL the propagation delay through the device is virtually eliminated. The PLL aligns the feedback clock output edge with the clock input reference edge resulting a near zero delay through the device. The maximum insertion delay of the device in zero-delay applications is measured between the reference clock input and any output. This effective delay consists of the static phase offset, I/O jitter (phase or long-term jitter), feedback path delay and the output-to-output skew error relative to the feedback output. Calculation of part-to-part skew The MPC9608 zero delay buffer supports applications where critical clock signal timing can be maintained across several devices. If the reference clock inputs of two or more MPC9608 are connected together, the maximum overall timing uncertainty from the common CCLK input to any output is:
VCCA MPC9608 VCC 33...100 nF
tSK(PP) = t() + tSK(O) + tPD, LINE(FB) + tJIT() CF This maximum timing uncertainty consists of 4 components: static phase offset, output skew, feedback board trace delay and I/O (phase) jitter:
CCLKCommon
-t()
tPD,LINE(FB)
QFBDevice 1
Figure 3. VCCA Power Supply Filter The minimum values for RF and the filter capacitor CF are defined by the required filter characteristics: the RC filter should provide an attenuation greater than 40 dB for noise whose spectral content is above 100 kHz. In the example RC filter shown in Figure 3. "VCCA Power Supply Filter", the filter cut-off frequency is around 3-5 kHz and the noise attenuation at 100 kHz is better than 42 dB. As the noise frequency crosses the series resonant point of an individual capacitor its overall impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the bandwidth of the PLL. Although the MPC9608 has several design features to minimize the susceptibility to power supply noise (isolated power and grounds and fully differential PLL) there still may be applications in which
Any QDevice 1
tJIT()
+tSK(O) +t()
QFBDevice2
tJIT()
Any QDevice 2 Max. skew
+tSK(O) tSK(PP)
Figure 4. MPC9608 max. device-to-device skew
TIMING SOLUTIONS
7
MOTOROLA
MPC9608
Due to the statistical nature of I/O jitter a RMS value (1 s) is specified. I/O jitter numbers for other confidence factors (CF) can be derived from Table 10. Table 10: Confidence Facter CF
CF 1s 2s 3s 4s 5s 6s Probability of clock edge within the distribution 0.68268948 0.95449988 0.99730007 0.99993663 0.99999943 0.99999999
technique terminates the signal at the end of the line with a 50 resistance to VCC/2. This technique draws a fairly high level of DC current and thus only a single terminated line can be driven by each output of the MPC9608 clock driver. For the series terminated case however there is no DC current draw, thus the outputs can drive multiple series terminated lines. Figure 6. "Single versus Dual Transmission Lines" illustrates an output driving a single series terminated line versus two series terminated lines in parallel. When taken to its extreme the fanout of the MPC9608 clock driver is effectively doubled due to its capability to drive multiple lines.
MPC9608 OUTPUT BUFFER IN
14
The feedback trace delay is determined by the board layout and can be used to fine-tune the effective delay through each device. In the following example calculation a I/O jitter confidence factor of 99.7% ( 3s) is assumed, resulting in a worst case timing uncertainty from input to any output of -295 ps to 295 ps1 relative to CCLK:
RS = 36
ZO = 50 OutA
tSK(PP) = tSK(PP) =
[-100ps...100ps] + [-150ps...150ps] + [(15ps @ -3)...(15ps @ 3)] + tPD, LINE(FB) [-295ps...295ps] + tPD, LINE(FB)
IN
MPC9608 OUTPUT BUFFER
14
RS = 36
ZO = 50 OutB0
Due to the frequency dependence of I/O jitter, Figure 5 "Max. I/O Jitter versus frequency" can be used for a more precise timing performance analysis.
RS = 36
ZO = 50 OutB1
Figure 6. Single versus Dual Transmission Lines The waveform plots in Figure 7. "Single versus Dual Line Termination Waveforms" show the simulation results of an output driving a single line versus two lines. In both cases the drive capability of the MPC9608 output buffer is more than sufficient to drive 50 transmission lines on the incident edge. Note from the delay measurements in the simulations a delta of only 43ps exists between the two differently loaded outputs. This suggests that the dual line driving need not be used exclusively to maintain the tight output-to-output skew of the MPC9608. The output waveform in Figure 7. "Single versus Dual Line Termination Waveforms" shows a step in the waveform, this step is caused by the impedance mismatch seen looking into the driver. The parallel combination of the 36 series resistor plus the output impedance does not match the parallel combination of the line impedances. The voltage wave launched down the two lines will equal: VL = VS ( Z0 / (RS+R0 +Z0)) Z0 = 50 || 50 RS = 36 || 36 R0 = 14 VL = 3.0 ( 25 / (18+17+25) = 1.31V At the load end the voltage will double, due to the near unity reflection coefficient, to 2.6V. It will then increment towards the quiescent 3.0V in steps separated by one round trip delay (in this case 4.0ns).
1. Skew data are design targets and pending device specifications.
TBD
Figure 5. Max. I/O Jitter versus frequency Driving Transmission Lines The MPC9608 clock driver was designed to drive high speed signals in a terminated transmission line environment. To provide the optimum flexibility to the user the output drivers were designed to exhibit the lowest impedance possible. With an output impedance of less than 20 the drivers can drive either parallel or series terminated transmission lines. For more information on transmission lines the reader is referred to Motorola application note AN1091. In most high performance clock networks point-to-point distribution of signals is the method of choice. In a point-to-point scheme either series terminated or parallel terminated transmission lines can be used. The parallel
MOTOROLA
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TIMING SOLUTIONS
MPC9608
3.0 OutA tD = 3.8956 OutB tD = 3.9386
2.5
VOLTAGE (V)
2.0 In 1.5
match the impedances when driving multiple lines the situation in Figure 8. "Optimized Dual Line Termination" should be used. In this case the series terminating resistors are reduced such that when the parallel combination is added to the output buffer impedance the line impedance is perfectly matched.
MPC9608 OUTPUT BUFFER
14
RS = 22
ZO = 50
1.0
0.5
RS = 22
ZO = 50
0 2 4 6 8 TIME (nS) 10 12 14
14 + 22 k 22 = 50 k 50 25 = 25 Figure 8. Optimized Dual Line Termination
Figure 7. Single versus Dual Waveforms Since this step is well above the threshold region it will not cause any false clock triggering, however designers may be uncomfortable with unwanted reflections on the line. To better
MPC9608 DUT Pulse Generator Z = 50W ZO = 50 ZO = 50
RT = 50 VTT
RT = 50 VTT
Figure 9. CCLK MPC9608 AC test reference for Vcc = 3.3V and Vcc = 2.5V
TIMING SOLUTIONS
9
MOTOROLA
MPC9608
VCC VCC VCC VCC
B2 B2
CCLK
VCC VCC VCC VCC
B2 B2
GND FB_IN
GND
GND tSK(O) The pin-to-pin skew is defined as the worst case difference in propagation delay between any similar delay path within a single device t()
GND
Figure 10. Output-to-output Skew tSK(O)
VCC VCC tP T0 DC = tP /T0 x 100% The time from the PLL controlled edge to the non controlled edge, divided by the time between PLL controlled edges, expressed as a percentage
Figure 11. Propagation delay (tPD, static phase offset) test reference
B2
CCLK
GND FB_IN
TJIT() = |T0 -T1 mean| The deviation in t0 for a controlled edge with respect to a t0 mean in a random sample of cycles
Figure 12. Output Duty Cycle (DC)
Figure 13. I/O Jitter
TN
TN+1
TJIT(CC) = |TN -TN+1 |
T0
TJIT(PER) = |TN -1/f0 |
The variation in cycle time of a signal between adjacent cycles, over a random sample of adjacent cycle pairs
The deviation in cycle time of a signal with respect to the ideal period over a random sample of cycles
Figure 14. Cycle-to-cycle Jitter
Figure 15. Period Jitter
VCC=3.3V 2.4 0.55 tF tR
VCC=2.5V 1.8V 0.6V
CCLK
VCC VCC VCC VCC ts tH
B2 B2
GND CLK_STOP
GND
Figure 16. Output Transition Time Test Reference
Figure 17. Setup and Hold Time (ts, tH) Test Reference
MOTOROLA
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TIMING SOLUTIONS
MPC9608
OUTLINE DIMENSIONS
FA SUFFIX LQFP PACKAGE CASE 873A-02 ISSUE A
A A1
32 25 4X
0.20 (0.008) AB T-U Z
1
-T- B B1
8
-U- V P DETAIL Y
17
AE
V1 AE DETAIL Y
9
-Z- 9 S1 S
4X
0.20 (0.008) AC T-U Z
G -AB-
SEATING PLANE
DETAIL AD
-AC-
BASE METAL
F
8X
M_ R
CE
SECTION AE-AE
X DETAIL AD
TIMING SOLUTIONS
GAUGE PLANE
0.250 (0.010)
H
W
K
Q_
11
EE EE EE EE
N
D
0.20 (0.008)
M
AC T-U Z
0.10 (0.004) AC
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE -AB- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS -T-, -U-, AND -Z- TO BE DETERMINED AT DATUM PLANE -AB-. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -AC-. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.250 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -AB-. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.520 (0.020). 8. MINIMUM SOLDER PLATE THICKNESS SHALL BE 0.0076 (0.0003). 9. EXACT SHAPE OF EACH CORNER MAY VARY FROM DEPICTION. MILLIMETERS MIN MAX 7.000 BSC 3.500 BSC 7.000 BSC 3.500 BSC 1.400 1.600 0.300 0.450 1.350 1.450 0.300 0.400 0.800 BSC 0.050 0.150 0.090 0.200 0.500 0.700 12_ REF 0.090 0.160 0.400 BSC 1_ 5_ 0.150 0.250 9.000 BSC 4.500 BSC 9.000 BSC 4.500 BSC 0.200 REF 1.000 REF INCHES MIN MAX 0.276 BSC 0.138 BSC 0.276 BSC 0.138 BSC 0.055 0.063 0.012 0.018 0.053 0.057 0.012 0.016 0.031 BSC 0.002 0.006 0.004 0.008 0.020 0.028 12_ REF 0.004 0.006 0.016 BSC 1_ 5_ 0.006 0.010 0.354 BSC 0.177 BSC 0.354 BSC 0.177 BSC 0.008 REF 0.039 REF
J
DIM A A1 B B1 C D E F G H J K M N P Q R S S1 V V1 W X
-T-, -U-, -Z- MOTOROLA
MPC9608
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JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center, 3-20-1, Minami-Azabu. Minato-ku, Tokyo 106-8573 Japan. 81-3-3440-3569 ASIA / PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, 2, Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong. 852-26668334
HOME PAGE: http://www.motorola.com/semiconductors/
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TIMING SOLUTIONS MPC9608/D

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