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| Features * 50 Input Clock and Data (Differential ECL) through 2.54 mm Pitch Connectors * Demultiplexed Outputs (Single-ended ECL) 50 Adapted on up to 8 x 2.54 mm Pitch Connectors * DMUX Functions Adjusted by Jumpers and Potentiometers * Separated Ground and Supplies * Suitable for High-frequency Evaluation (up to 2.2 GHz) over the Military Temperature Range * Board Dimensions: 200 mm x 190 mm * Fully Assembled and Tested For optimal understanding and use of this evaluation board, please refer to the TS81102G0 DMUX specification also. Description The TSEV81102G0TPZR3 DMUX Evaluation Board (EB) is designed to simplify the characterization and the evaluation of the TS81102G0 device (2 Gsps DMUX). The DMUX EB enables the test of all the functions of the DMUX: Synchronous and Asynchronous reset functions, selection of the DMUX ratio (1:4 or 1:8), selection of the number of bits (8 or 10), output data common mode and swing adjustment, die junction temperature measurements over military temperature range, etc. The DMUX EB has been designed to enable an easy connection with Atmel ADC Evaluation Boards (i.e.: TSEV8388BG, TSEV83102G0 or TSEV83084G0) for an extended functionality evaluation (ADC+DMUX multi-channels applications). The DMUX EB comes fully assembled and tested, with a TS81102G0 device implemented on-board and a heatsink assembled on the device. DMUX 8-/10-bit 1:4/1:8 2 Gsps Evaluation Board TSEV81102G0TPZR3 Rev. 2108A-BDC-07/02 1 Block Diagram Figure 1. TSEV81102G0TPZR3 Block Diagram BANANA JACKS (4 mm) SMA Connectors GND VCC PITCH CONNECTORS (2.54 mm) PORT D Potentiometer Jumpers PORT B Power Supplies ADC DelAdj ADCDelAdjOut (Diff.) SwiA ADCDelAdjIn BIST NbBit RatioS ClkInType 1 1 1 1 1 1 PORT F PITCH CONNECTORS (2.54 mm) PORT H 2 2 2 2 10 bits+Ref (Single) DR (Diff.) 200 mm Data In (10 bits Diff.) 2 TS81102G0 ClkIn (Diff.) PORT G Async Reset (Single) BANANA JACKS (4 mm) Temperature Measurments IGND VDIOD IDIOD VGN Sync Reset (Diff.) 2 1 1 PORT E DMUX DelAdj Power Supplies PORT C GND VEE BANANA JACKS (4 mm) 152 mm 38 mm TSEV81102G0TP 2 TSEV81102G0TPZR3 2108A-BDC-07/02 VPLUS VTT SMA Connectors SUBVIS Connectors PORT A TSEV81102G0TPZR3 Board Structure Board Layers Thickness Profile The TSEV81102G0TPZR3 is a seven-layered PCB constituted by four copper layers and three dielectric layers. The board is 1.75 mm thick. The board has the following structure, from top to bottom. Table 1. Board Layers Thickness Profile Layer Layer 1 Copper layer Layer 2 R4003 dielectric layer (Hydrocarbon/Wovenglass) Characteristics Copper thickness = 35 m Input signals: 50 microstrip lines Output data signals: 60 microstrip lines, 50 terminated Layer thickness = 200 m Dielectric constant = 3.4 at 10 GHz -0.044 dB / inch insertion loss at 2.5 GHz -0.318 dB / inch insertion loss at 18 GHz Copper thickness = 35 m Upper reference plane, divided in two parts: GND and VPLUSDOUT Layer thickness = 0.4 mm Copper thickness = 35 m Power plane: VEE, VCC, VTT, GND Layer thickness = 1.0 mm Copper thickness = 35 m Lower reference plane (replica of layer 3) Layer 3 Copper layer Layer 4 BT/Epoxy dielectric layer Layer 5 Copper layer Layer 6 BT/Epoxy dielectric layer Layer 7 Copper layer Metal Layers The four metal layers respectively correspond to: the signals' layer (layer 1) (Figure 7), the two reference layers (layer 3 and layer 7) (Figure 8) and the supply layer (layer 5) (Figure 9 on page 16). The upper and the lower reference planes (layer 3 and 7) are partitioned into GND (reference for input signals) and VPLUSDOUT (reference for digital output signals), according to the same partition of the DMUX package. Layer 5 is dedicated to power supplies (and ground). 3 2108A-BDC-07/02 Dielectric Layers The three dielectric layers are respectively constituted by a low insertion loss dielectric (RO4003) layer (layer 2) and by a BT/Epoxy dielectric layer (layer 4 and 6). Considering the severe mechanical constraints due to the wide temperature range and the high frequency domain in which the board is to operate, two different dielectric materials are used: * The low insertion loss RO4003 Hydrocarbon/Wovenglass dielectric (-0.044 dB/inch loss at 2.5 GHz) which has an enhanced dielectric consistency in the high frequency domain is dedicated to the routing of 50 and 60 traces. The RO4003 dielectric constant is typically 3.4 at 10 GHz. The BT/Epoxy layer is chosen because of its enhanced mechanical characteristics for elevated temperature operations. The typical dielectric constant is 4.5 at 1 MHz. The BT/Epoxy dielectric has enhanced characteristics compared to FR4 Epoxy dielectric, namely: - - higher operating temperature value: 170C (125C for FR4), better withstanding of thermal shocks (from -65C up to 170C). * The characteristics of these two dielectrics make the board particularly suitable for performing measurements in the high frequency domain and over the military temperature range. I/O Accesses Power Supplies and Ground Access The power supplies and ground access are provided by four 4 mm section banana jacks (red jacks) respectively for VEE, VCC, VTT, VPLUSDOUT. The Ground access is provided by two 4 mm banana jacks (black jacks). Note: Two distinct Ground pads GND have been implemented on the board because of layout considerations. For proper use, connect them together to the same Ground. Input Access Input Data and Clock Access Access to the differential data and clock inputs (ClkIn, ClkInb, I[0..9], I[0..9]b) are provided by a female 2.54 mm pitch connector, via 50 microstrip lines. The connector is made of 2 rows of pitches. The lower row is connected to GND. The upper row is used for the data and the clock connections. Each differential signal is separated by a pitch connected to GND, as shown: Figure 2. Input Data Pitch Connector GN ... GN ... GN GN GN GN GN GN ... In1 In1b GN In2 In2b GN ... Note: 100 differential adaptation is performed on-chip. 4 TSEV81102G0TPZR3 2108A-BDC-07/02 TSEV81102G0TPZR3 Synchronous Reset Access Access to the signals SyncReset and SyncResetb is provided by two SMA connectors, via 50 microstrip lines. Note: 100 differential adaptation is performed on-chip. Asynchronous Reset Access ADC Synchronization Input Signal Access Access to the signal AsyncReset is provided by a SUBVIS connector. Access to the differential signal ADCDELADJIN is provided by two SMA connectors, via 50 microstrip lines. Note: 100 differential adaptation is performed on-chip. Outputs Access Digital Outputs Access to the single-ended output data and to the differential output clock (A[0..9] to H[0..9], RefA to RefH, DR, DRb) is provided by male 2.54 mm pitch connectors, via 60 microstrip lines. The microstrip lines are 50 terminated. The connectors are made of 2 rows of pitches. The upper rows are used for the signals' connections. The lower rows are connected to VPLUSDOUT. The output ports are separated from one another by a column (2 pitches) connected to VPLUSDOUT, as shown: Figure 3. Output Data Pitch Connector ... ... X9 V+ V+ V+ REF V+ Y1 V+ Y V+ ... ... Y9 V+ V+ V+ REFZ V+ ... ... Note: The characteristic impedance of the data output microstrip lines has been chosen to be 60, in order to terminate the lines either by 50 (ECL/PECL output format) or 75 resistors (TTL output format, available on request only). ADC Synchronization Output Signal Access Accesses to the differential signal ADCDELADJOUT are provided by two SMA connectors, via 50 microstrip lines. DMUX Functions Settings Four 2 mm-section banana jacks are provided to perform die temperature measurements (see "DMUX Settings Adjustment" on page 14). Three potentiometers are provided for the adjustment of SWIADJ, ADCDELADJCTRL and DMUXDELADJCTRL respectively. Four jumpers are provided for the setting of the static control signals NBBIT, RATIOSEL, CLKINTYPE and BIST (jumper on board = logic 0). 5 2108A-BDC-07/02 Layout Information Because the DMUX processes high-frequency signals, special attention was given to the board layout in order to achieve full speed operation efficiency. Thus, special effort was made in order to match the length of transmission lines for both input and output signals. In addition, cross-talk effects were reduced by increasing, wherever possible, the space between the lines. Power Supplies Decoupling Each power supply is bypassed by a 1 F Tantalum capacitor in parallel with a 100 nF chip capacitor. Each power supply access of the DMUX is also bypassed as close as possible to the device, by a 10 nF and a 100 pF surface mount chip capacitor in parallel. Note: Those capacitors are superposed. Reference Planes Each reference plane (layer 3 and layer 7) is physically divided in two parts: one GND trace and one VPLUSDOUT trace, which is the voltage reference of the output buffers of the DMUX. VPLUSDOUT can be set to GND (ECL format) or to 3.3V (PECL/TTL format) according to the desired output format. I/O Transmission Lines The following table summarizes the main properties of the microstrip lines of all the input and output signals. Note that the transmission delay through a transmission line is approximately 6.1 ps/mm. Table 2. I/O Transmission Lines Signal ClkIn ClkInb I[0..9], I[0..9]b A[0..9], ..., H[0..9] DR DRb SyncReset, SyncResetb ADCDELADJIN, ADCDELADJINb ADCDELADJOUT, ADCDELADJOUTb Note: Type Differential Differential Single Differential Differential Differential Differential Typical Length 69 mm 69.7 mm 68.8 mm 111.4 mm 111.9 mm 114.5 mm 96 mm 104 mm 111 mm Length Matching - - 1 8 - - 1 1 1 Characteristic Impedance 50 50 50 60 60 60 50 50 50 Adaptation On-chip 100 diff. On-chip 100 diff. 50 50 50 On-chip 100 diff. On-chip 100 diff. None Min length (I3): 67.8 mm Max length (I9): 69.6 mm Min length (F3 & E5): 104.2 mm Max length (C9): 119.3 mm Comments Two ground accesses, OSC1 and OSC2, have been provided near the DMUX for measurements purposes. 6 TSEV81102G0TPZR3 2108A-BDC-07/02 TSEV81102G0TPZR3 Pin and Package Description Information in this section is extracted from the TS81102G0 DMUX datasheet. For exhaustive information about the device's package, please refer to its datasheet. Pin Description Table 3. TSEV81102G0TPZR3 Pin Description Type Digital Inputs Name I[0...9] Clkln Outputs A[0...9] H[0...9] Levels Differential ECL Differential ECL Adjustable Logic Single Adjustable Logic Single Adjustable Single TTL TTL TTL 0V 0.5V Analog TTL TTL Differential ECL Differential analog input of 0.5V Comments Data input. Clock input. Data output for channel A to H. Common mode is adjusted with VPLUSDOUT. Swing is adjusted with SwiAdj. Data output for channel A to H. Common mode is adjusted with VPLUSDOUT. Swing is adjusted with SwiAdj. Reference voltage for channels A to H. Common mode is adjustable with VPLUSDOUT. Mode DR or DR/2 (logic 1: Data Ready). DMUX ratio (logic 1: 1:4). BIST selection (logic 0: BIST active). Swing fine adjustment of output buffers. Diode for chip temperature measurement. Number of bits: 8 or 10 (logic 1: 10 bits). Asynchronous reset (logic 1: reset on). Synchronous reset (on rising edge). Control of the delay line of DataReady input: Differential input = -0.5V, delay = 250 ps Differential input = 0V, delay = 500 ps Differential input = 0.5V, delay = 750 ps Control of the delay line for ADC: Differential input = -0.5V, delay = 250 ps Differential input = 0V, delay = 500 ps Differential input = 0.5V, delay = 750 ps Stand-alone delay adjust input for ADC. Differential termination of 100 inside the buffer. Stand-alone delay adjust output for ADC. Common ground. Digital negative power supply. Common mode adjustment for output buffers. Digital positive power supply. DR RefA RefH Control Signals ClklnType RatioSel Bist SwiAdj Diode NbBit Synchronization AsyncReset SyncReset DMUXDelAdjCtrl ADCDelAdjCtrl Differential analog input of 0.5V ADCDelAdjln ADCDelAdjOut Power Supplies GND VEE VPLUSDOUT VCC Differential ECL 50 differential output Ground 0V Power -5V Adjustable power from 0V to +3.3V Power +5V 7 2108A-BDC-07/02 TBGA 240 Package - Pinout Row A A A A A A A A A A A A A A A A A A A B B B B B B B B B B B B B B B B B B B C C C C C C C C C C C C C C C C C C C D D D Col 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 1 2 3 Name NC E3 E5 E7 E9 C0 C2 C4 C6 C8 REFA A1 A3 A5 A7 A9 DEMUXDELADJCTRL RSTSYNCB NC E1 E2 E4 E6 E8 REFC C1 C3 C5 C7 C9 A0 A2 A4 A6 A8 ASYNCRESET DEMUXDELADJCTRLB RSTSYNC REFE E0 VEE VPLUSDOUT VPLUSDOUT VPLUSDOUT VPLUSDOUT VEE VPLUSDOUT VEE VPLUSDOUT VEE VPLUSDOUT VPLUSDOUT VPLUSDOUT GND GND GND DIODE G8 G9 VEE Row D D D D D D D D D D D D D D D D E E E E E E E E F F F F F F F F G G G G G G G G H H H H H H H H J J J J J J J J K K K K Col 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 1 2 3 4 16 17 18 19 1 2 3 4 16 17 18 19 1 2 3 4 16 17 18 19 1 2 3 4 16 17 18 19 1 2 3 4 16 17 18 19 1 2 3 4 Name VEE VEE VPLUSDOUT VPLUSDOUT VEE VPLUSDOUT VEE VPLUSDOUT VEE VPLUSDOUT GND VCC VCC GND I0B I0 G6 G7 VPLUSDOUT VEE VEE VEE I1B I1 G4 G5 GND GND GND GND I2B I2 G2 G3 VEE VEE VEE VEE I3B I3 G0 G1 GND GND GND GND CLKINB CLKIN DR REFG VPLUSDOUT VCC VEE VEE I4B I4 SWIADJ DRB VEE VEE Row K K K K L L L L L L L L M M M M M M M M N N N N N N N N P P P P P P P P R R R R R R R R T T T T T T T T T T T T T T T T Col 16 17 18 19 1 2 3 4 16 17 18 19 1 2 3 4 16 17 18 19 1 2 3 4 16 17 18 19 1 2 3 4 16 17 18 19 1 2 3 4 16 17 18 19 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Name VEE GND I5B I5 H9 RATIOSEL VPLUSDOUT VPLUSDOUT VEE VEE I6B I6 H7 H8 GND GND GND GND I7B I7 H5 H6 VPLUSDOUT VPLUSDOUT VEE VEE I8B I8 H3 H4 GND GND GND GND I9B I9 H1 H2 VPLUSDOUT VPLUSDOUT VEE GND ADCDELADJOUT ADCDELADJOUTB REFH H0 VEE VEE VEE VPLUSDOUT VPLUSDOUT VEE VPLUSDOUT VEE VPLUSDOUT VEE VPLUSDOUT VPLUSDOUT GND VEE Row T T T U U U U U U U U U U U U U U U U U U U V V V V V V V V V V V V V V V V V V V W W W W W W W W W W W W W W W W W W W Col 17 18 19 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Name VEE ADCDELADJIN ADCDELADJINB F8 F9 VEE VPLUSDOUT VPLUSDOUT VPLUSDOUT VPLUSDOUT VEE VPLUSDOUT VEE VPLUSDOUT VEE VPLUSDOUT VPLUSDOUT VPLUSDOUT GND GND GND GND F7 F6 F4 F2 F0 D9 D7 D5 D3 D1 REFD B8 B6 B4 B2 B0 BIST CLKINTYPE ADCDELADJCTRL NC F5 F3 F1 REFF D8 D6 D4 D2 D0 B9 B7 B5 B3 B1 REFB NBBIT ADCDELADJCTRLB NC 8 TSEV81102G0TPZR3 2108A-BDC-07/02 TSEV81102G0TPZR3 Figure 4. TBGA 240 Package: Bottom View 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Ball A1 index A E1 RstSyncb Demuxdeladjctrcl A9 A7 A5 A3 A1 REFA C8 C6 C4 C2 C0 E9 E7 E5 E3 RstSync Demuxdeladjctrclb Asyncreset A8 A6 A4 A2 A0 C9 C7 C5 C3 C1 REFC E8 E6 E4 E2 B C D E F G H J K L M N P R T U V W DIODE GND GND GND VPLUSD VPLUSD VPLUSD VEE VPLUSD VEE VPLUSD VEE VPLUSD VPLUSD VPLUSD VPLUSD VEE E0 REFE I0 I0b GND VCC VCC GND VPLUSD VEE VPLUSD VEE VPLUSD VEE VPLUSD VPLUSD VEE VEE VEE G9 G8 I1 I1b VEE VEE VEE VPLUSD G7 G6 I2 I2b GND GND GND GND G5 G4 I3 I3b VEE VEE VEE VEE G3 G2 CLK CLKb GND GND GND GND G1 G0 I4 I4b VEE VEE VCC VPLUSD REFG DR I5 I5b GND VEE VEE VEE DRb SWIadj I6 I6b VEE VEE VPLUSD VPLUSD RATIOSEL H9 I7 I7b GND GND GND GND H8 H7 I8 I8b VEE VEE VPLUSD VPLUSD H6 H5 I9 I9b GND GND GND GND H4 H3 ADCdelayadjoutB ADCdelayadjout GND VEE VPLUSD VPLUSD H2 H1 ADCdelayadjinB ADCdelayadjin VEE VEE GND VPLUSD VPLUSD VEE VPLUSD VEE VPLUSD VEE VPLUSD VPLUSD VEE VEE VEE H0 REFH GND GND GND GND VPLUSD VPLUSD VPLUSD VEE VPLUSD VEE VPLUSD VEE VPLUSD VPLUSD VPLUSD VPLUSD VEE F9 F8 ADCDELADJCTRL CLKINTYPE BIST B0 B2 B4 B6 B8 REFD D1 D3 D5 D7 D9 F0 F2 F4 F6 F7 ADCDELADJCTRLb NbBIT REFB B1 B3 B5 B7 B9 D0 D2 D4 D6 D8 REFF F1 F3 F5 9 2108A-BDC-07/02 Thermal and Moisture Characteristics Thermal Resistance from Junction to Case: RTHJC The Rth from junction to case for the TBGA package is estimated at 0.7C/W which can be decomposed in: * * * Silicon: 0.1C/W Die attach epoxy: 0.5C/W (thickness # 50 m) Copper block (back side of the package): 0.1C/W. Thermal Resistance from Junction to Ambient: RTHJA A pin-fin type heatsink, size 40 mm x 40 mm x 8 mm can be used to reduce thermal resistance. This heatsink should not be glued on top of the package as Atmel does not guarantee the attachment on the board in such a configuration. The heatsink could be clipped or screwed on the board. With such a heatsink the Rthj-a is about 6C/W. (If Atmel takes 10C/W for Rth through the heatsink in parallel with 15C/W for Rth through the balls). Without a heatsink, the Rth junction to air for a package reported on-board can be estimated from 13 to 20C/W (depending on the board used). The worst value 20C/W is given for 1-layer board (13C for 4-layer board). Temperature Diode Characteristic The theoretical characteristic of the diode, in function of the temperature when I = 3 mA is depicted below. Figure 5. Temperature Diode Characteristic Vdiode 1.0 DiodeT I = 3 mA dV/dT = 1.32 mV/degC 900m (V) 800m 700m -70.0 -20.0 30.0 80.0 130.0 Temperature (C) Moisture Characteristic This device is sensitive to the moisture (MSL3 according JEDEC standard). Shelf life in sealed bag: 12 months at < 40C and < 90% relative humidity (RH). After this bag is opened, devices that will be subjected to infrared reflow, vapor-phase reflow, or equivalent processing (peak package body temperature 220C) must be: * * mounted within 168 hours at factory conditions of 30C/60% RH, or stored at 20% RH. 10 TSEV81102G0TPZR3 2108A-BDC-07/02 TSEV81102G0TPZR3 Devices require baking, before mounting, if Humidity Indicator is > 20% when read at 23C 5C. If baking is required, devices may be baked for: * * 192 hours at 40C + 5C/-0C and < 5% RH for low temperature device containers, or 24 hours at 125C 5C for high-temperature device containers. DC Characteristics and Current Consumption In this section, the typical values of the board's I/O signals and power sources are listed. These values refer to a nominal use of the evaluation board. These values are purely indicative and may depend on temperature, frequency of use, etc. The following tables give an estimation of the power consumption of the board, including the current consumption of DMUX and the current consumption induced by the components added on the board. The values given below are relevant for ECL 50, PECL 50 and TTL 75 output formats only, assuming that the DMUX is working in ratio 1:8, 10 bits. For further information about output formats, please also refer to "DMUX Settings Adjustment" on page 14. Table 4. Supply Voltage Parameter VCC VPLUSDOUT VTT VEE ECL 50 5 0 -2 -5 PECL 50 5 3.3 1.3 -5 TTL 75 5 3.3 0.25 -5 Unit V V V V Table 5. Output Voltage (at T = 125C) Parameter VOL VPH VREF ECL 50 -1.8 -0.8 -1.3 PECL 50 1.5 2.5 2.0 TTL 75 0.5 2.5 1.5 Unit V V V Table 6. Maximum Current Consumption Parameter ICC IPLUSDOUT ITT IEE ECL 50 (SWIADJ = 0V) 40 2200 1940 800 PECL 50 (SWIADJ = 0V) 40 2200 1940 800 TTL 75 (SWIADJ = 0.5V) 40 3010 2630 880 Unit mA mA mA mA 11 2108A-BDC-07/02 Absolute Maximum Ratings The following table lists the absolute maximum values of the board. These maximum ratings are limiting values to be considered individually, while other parameters are within specified operating conditions. Long exposure to maximum ratings may affect the DMUX reliability. Table 7. Absolute Maximum Ratings Parameter Positive supply voltage Positive output buffer supply voltage Negative supply voltage Analog input voltages Symbol VCC VPLUSD VEE ADCDelAdjCtrl, ADCDelAdjCtrlb or DMUXDelAdjCtrl, DMUXDelAdjCtrlb or SwiAdj Clkln or Clklnb or I[0...9] or I[0...9]b or SyncReset or SyncResetb or ADCDelAdjln or ADCDelAdjlnb Clkln - Clklnb or I[0...9] - I[0...9]b or SyncReset - Syncresetb or ADCDelAdjln ADCDelAdjlnb A[0...9] to H[0...9] or RefA to RefH or DR or DRb Clkln Type RatioSel NbBit AsyncReset BIST DIODE DIODE Tj Tstg Voltage range for each pad Differential voltage range Voltage range for each pad Comments Value GND to 6 GND to 4 GND to -6 0 to 1 Unit V V V V -1 to 1 -2.2 to 0.6 V ECL 50 input voltage Maximum difference between ECL 50 input voltages Minimum differential swing Maximum differential swing 0.1 V 2 Data output current Maximum current 36 mA TTL input voltages GND to VCC V Maximum input voltage on diode for temperature measurement Maximum input current on diode Maximum junction temperature Storage temperature Note: 700 8 135 TBD mV mA C C Absolute maximum ratings are limiting values, to be applied individually, while other parameters are within specified operating conditions. Long exposure to maximum rating may affect device reliability. The use of a thermal heat sink is mandatory. 12 TSEV81102G0TPZR3 2108A-BDC-07/02 TSEV81102G0TPZR3 Main Function Description Other function descriptions are available in the TS81102G0 DMUX datasheet. Quick Start The evaluation board is delivered fully assembled and tested. A heatsink, which is strongly recommended, is also delivered assembled. Do not turn on the power supplies until all power connections to the evaluation board are established. The procedure described below aims at helping when the board is used for the first time. It describes the steps to accomplish a BIST test (Built-In Self Test, see "Miscellaneous" on page 15) in order to verify whether the board is functional or not. At the end of the procedure, the DMUX will be in the following configuration: DR mode, 10 bits mode, 1:8 ratio, BIST activated, SWIADJ = 0V, ECL output format. 1. Connect the board's ground pads together. 2. Connect the pad marked VPLUSDOUT to the GND pad. 3. Connect a -5V power supply source to the pad marked VEE. Then, connect the supply's ground to the GND pad. 4. Connect a +5V power supply source to the pad marked VCC. Then, connect the supply's ground to the GND pad. 5. Connect a -2V power supply source to the pad marked VTT. Then, connect the supply's ground to the GND pad. 6. Connect your input clock to the board (pitches CLKIN and CLKINB). This clock may either be differential or single-ended (see "BIST" on page 14). 7. Remove the jumpers marked NBBIT and CLKINTYPE. The remaining jumpers are RATIOSEL and BIST. 8. Connect a logic analyzer, such as an HP16500 at the output of the board. 9. Turn on the supply and signal sources according to the following sequence: - - - - - VEE first VCC VPLUSDOUT VTT Input clock 10. Set the potentiometer marked SWIADJ such that the voltage on the SWIADJ pin of the DMUX is 0V. 11. Connect pad ASYNCRESET to ground (the ASYNCHRESET is active at TTL high level and must be tied to ground when the device is running). At the output, the demultiplexed BIST sequence shall be observed. Note: It is not necessary to verify the 512 codes of the BIST to make sure that the DMUX is functional. Verifying the first 16 codes is indeed sufficient. 13 2108A-BDC-07/02 DMUX Settings Adjustment Four jumpers are provided in order to activate the functions RATIOSEL, BIST, CLKINTYPE and NBBIT. When the jumper is on-board, it corresponds to logic 0. The following table recapitulates which functions are active when the jumpers are on-board or not. Table 8. DUMX Settings Adjustment Name CLKINTYPE Jumper ON OUT BIST ON OUT NBBIT ON OUT RATIOSEL ON OUT Function DR/2 mode DR mode BIST active BIST inactive 8 bits mode 10 bits mode 1:8 DMUX Ration 1:8 DMUX Ration BIST A pseudo-random 10-bit generator is implemented in the DMUX. It generates a 10 bits signal at the output of the DMUX, with a period of 512 input clock's periods. The sequence start on port A. The output obtained on port A to H depends on the conversion ratio. The driving clock of BIST is ClkIn. CLKINTYPE must be set to logic 1 (jumper out) to have different 10-bit code on each output. The complete BIST sequence is available on request. Delay Adjust Two delay adjusts of 250 ps, controlled by potentiometers, are available in order to synchronize the input clock and data of the DMUX on the one hand, and to delay the signal ADCDELADJIN on the other hand. The input DelAdjCtrl has been set to 0V. The input DelAdjCtrlb varies from -0.55V to 0.55V, according to the potentiometer position. The generated delay is proportional to the differential voltage V(DelAdjCtrl)-V(DelAdjCtrlb) as shown in the next graph. Figure 6. Delay Adjustment Characteristic 300 200 100 Delay (ps) Tj=25C 0 -100 -200 -300 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 V(DelAdjCtrl)-V(DelAdjCtrlB) (V) Note: The variation of the delay in function of the temperature is insignificant. 14 TSEV81102G0TPZR3 2108A-BDC-07/02 TSEV81102G0TPZR3 Miscellaneous * * * * * Always wear an anti-static strap when manipulating the board, the DMUX being very sensitive to ESDs. Make sure that the current as delivered by your power supplies is sufficient to supply the board. Always switch on the DMUX board supplies in the following order: VPLUSDOUT first, VEE, VCC, VTT. Always make sure that the output current through the termination resistors does not exceed 36 mA. After the supplies are switched on, send an asynchronous reset pulse into the DMUX (i.e. leave the pad ASYNCRESET open and then connect it to the ground). 15 2108A-BDC-07/02 Evaluation Board Schematics Figure 7. Component Side Figure 8. Reference Planes Figure 9. Power Supplies Plane 16 TSEV81102G0TPZR3 2108A-BDC-07/02 TSEV81102G0TPZR3 TSEV81102G0TPZR3 Electric Schematic Figure 10. TSEV81102G0TPZR3 Electric Schematic ADC Delay Adjust Control GND_0 VCC J21 R9 P3 C1 1uF SyncResetB VPLUSDOUT AsyncReset SyncReset Power Supplies (Banana Jacks 4 mm) GND VCC VTT DEMUX Delay Adjust Control VCC R5 P2 1k VCC R3 SMA SUBVIS J13 J12 J14 Banana Jacks 2 mm Vdiode Idiode Vgnd VEE Ignd VCC R7 J17 J16 J18 J15 SWING ADUST VCC J22 J23 J24 J25 J26 4k 2.5k 4k 2.5k C87 10nF C88 10nF D1 D2 D4 D5 D6 R1 P1 5k C2 1uF C3 1uF C4 1uF 1k R10 4k R8 R102 4k R4 2.5k R101 2k 2k D3 R2 2k 5k C5 VEE 100nF gnd C6 100nF C7 VPLUSD 100nF 2.5k R6 C8 GND VCC GND VTT 100nF gnd gnd VEE VEE VEE VEE VEE gnd NbBit S1 S2 S3 S4 VEE SMA J11 ADCDelAdjIn Connectors J10 ADCDelAdjInB J20 ADCDelAdjOut J19 ADCDelAdjOutB Bist RatioSel ClkInType gnd ADCDelAdjCtrl DEMUXDelAdjCtrlB DEMUXDelAdjCtrl ADCDelAdjOutB ADCDelAdjOut ADCDelAdjInB ADCDelAdjIn ADCDelAdjCtrlB NbBit Diode SwiAdj Bist RatioSel SyncResetB SyncReset AsyncReset ClkInType U1 PITCH Connectors (2.54 mm) I0 I0B I1 I1B I2 I2B I3 I3B I4 I4B I5 I5B I6 I6B I7 I7B I8 I8B I9 I9B ClkIn ClkInB I0 I0B I1 I1B I2 I2B I3 I3B I4 I4B I5 I5B I6 I6B I7 I7B I8 I8B I9 I9B PITCH Connectors (2.54 mm) A[0..9] REFA B[0..9] REFB C[0..9] REFC D[0..9] REFD R89,...98 R88 50 A[0..9] VTT REFA VTT B[0..9] VTT REFB VTT C[0..9] VTT REFC VTT D[0..9] VTT REFD VTT E[0..9] VTT REFE VTT F[0..9] VTT REFF VTT G[0..9] VTT REFG VTT H[0..9] VTT REFH VTT DR 50 R100 50 VTT DRB VTT J4 50 R78,...87 R77 50 50 R67,...76 R66 50 J2 50 R56,...65 R55 50 J1 TS81102G0 DEMUX E[0..9] REFE F[0..9] REFF G[0..9] REFG H[0..9] 50 R45,...54 R44 50 50 R34,...43 R33 50 J3 50 R23,...32 R22 50 ClkIn ClkInB VPLUSD REFH DR VCC DRB 50 R12,...21 R11 R99 50 50 J5 GND Power Supplies accesses of the DEMUX are bypassed very close to the device by a 10 nF capacitor in parallel with a 100 pF capacitor VEE (J3) VPLUSD GND VCC VEE TSEV81102G0TP 17 2108A-BDC-07/02 Component List Table 9. Component List Type SMA CONNECTOR Reference VITELEC 142 - 0701 - 851 RADIALL R125 620 001 BANANA JACK 4 mm DELTRON E. F. JOHNSON SUBVIS CONNECTOR PITCH CONNECTOR 2.54 mm (two rows) CAPACITOR RADIALL R112 665 - CHIP TANTALE 1 uF, 20V CHIP Ceramic 100 nF CHIP Ceramic 10 nF Quantity 2 4 6 4 1 5 4 4 39 Label J12, J13 J10, J11, J19, J20 J21 to J26 J15 to J18 J14 J1 to J5 C1 to C4 C5 to C8 C9, C11, C13, C15, C17, C19, C21, C23, C25, C27, C29, C31, C33, C35, C37, C39, C41, C43, C45, C47, C49, C51, C53, C55, C57, C59, C61, C63, C65, C67, C69, C71, C73, C75, C77, C79, C81, C83, C85, C87, C88 C10, C12, C14, C16, C18, C20, C22, C24, C26, C28, C30, C32, C34, C36, C38, C40, C42, C44, C46, C48, C50, C52, C54, C56, C58, C60, C62, C64, C66, C68, C70, C72, C74, C76, C78, C80, C82, C84, C86 R1, R2 R5, R6, R9, R10 R3, R4, R7, R8 R101, R102 R11 to R100 P1 P2, P3 D1 to D6 U1 Ceramic 10 nF 39 RESISTOR CHIP 5 K 1% CHIP 4 K 1% CHIP 2.5 K 1% CHIP 2 K 1% CHIP 50 1% 2 4 2 2 90 1 2 6 1 POTENTIOMETER BOURNS 2 K 25 turns BOURNS 1 K 25 turns DIODE DMUX - TS81102G0 18 TSEV81102G0TPZR3 2108A-BDC-07/02 TSEV81102G0TPZR3 Applying the TSEV81102G0 DMUX The TSEV81102G0 DMUX evaluation board has been designed to be connected with TSEV8388G and TSEV83102G0 ADC evaluation boards. Figure 11. TSEV81102G0 DMUX Evaluation Boards VplusD = 0V 3.3V CLOCK BUFFER s-e or diff. (2 GHz) Vee = -5V FS Vcc = +5V (125 MHz) 8x8b/10b single A[0..9] H[0..9] DEMUX Clkln (1 GHz) 8b/10b diff. Data Bus Data Ready I[0..9] (1 - 2 GHz) 1b diff. Clkln delay DR RefA RefH Analog Input ADC (250 MHz) 1b diff. ECL + ref ECL Rload = 50 Vih = -1.0V Vil = -1.4V Delay adjust control Number of bits (8/10) VplusD = ground Rload = 50 Vtt = -2V Voh = -0.8V Vol = -1.8V Synchronous or Asynchronous Reset 8bits 1 GHz TS8388B 10bits 2 GHz TS83102G0 TTL + ref VplusD = 3.3V Rload 75 Vtt = ground Voh = 2.5V Vol = 0.5V TS81102G0 PECL + ref VplusD = 3.3V Rload = 50 Vtt = 1.3V Voh = 2.5V Vol = 1.5V Please, refer to the specific document "DMUX and ADC APPLICATION NOTES" for more information. ASIC (DC) 8 ref 19 2108A-BDC-07/02 ADC to DMUX Connections The DMUX inputs configuration has been optimized to be connected to the TS8388B ADC. The die in the TBGA package is up. For the ADC, different types of packages can be used such as CBGA with die up or the CQFP68 with die down. The DMUX device being completely symmetrical, both ADC packages can be connected to the TBGA package of the DMUX without crisscrossing the lines (see table below). Table 10. ADC to DMUX Connections ADC Digital Outputs CQFP68 Package D0 D1 D2 D3 D4 D5 D6 D7 - - DMUX Data Inputs TBGA Package I7 I6 I5 I4 I3 I2 I1 I0 18 not connected 19 not connected ADC Digital Outputs CBGA Package D0 D1 D2 D3 D4 D5 D6 D7 - - DMUX Data Inputs TBGA Package I0 I1 I2 I3 I4 I5 I6 I7 18 not connected 19 not connected 20 TSEV81102G0TPZR3 2108A-BDC-07/02 TSEV81102G0TPZR3 Ordering Information Evaluation Board TS EV 81102G0 TP ZR3 Manufacturer prefix(1) Evaluation board prefix Device or family Availability of all the output levels Package of the DMUX: TBGA 240 Note: 1. For availability of the different versions, contact your ATMEL sale office. The board includes the bonded package and the heatsink. 21 2108A-BDC-07/02 Datasheet Status Description Table 11. Datasheet Status Datasheet Status Objective specification This datasheet contains target and goal specifications for discussion with customer and application validation. This datasheet contains target or goal specifications for product development. This datasheet contains preliminary data. Additional data may be published later; could include simulation results. This datasheet contains also characterization results. This datasheet contains final product specification. Validity Before design phase Target specification Valid during the design phase Preliminary specification -site Valid before characterization phase Preliminary specification -site Product specification Limiting Values Valid before the industrialization phase Valid for production purposes Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application Information Where application information is given, it is advisory and does not form part of the specification. Life Support Applications These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Atmel customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Atmel for any damages resulting from such improper use or sale. 22 TSEV81102G0TPZR3 2108A-BDC-07/02 Atmel Headquarters Corporate Headquarters 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 487-2600 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany TEL (49) 71-31-67-0 FAX (49) 71-31-67-2340 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TEL 1(719) 576-3300 FAX 1(719) 540-1759 Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland TEL (41) 26-426-5555 FAX (41) 26-426-5500 Microcontrollers 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France TEL (33) 2-40-18-18-18 FAX (33) 2-40-18-19-60 Biometrics/Imaging/Hi-Rel MPU/ High Speed Converters/RF Datacom Avenue de Rochepleine BP 123 38521 Saint-Egreve Cedex, France TEL (33) 4-76-58-30-00 FAX (33) 4-76-58-34-80 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimhatsui East Kowloon Hong Kong TEL (852) 2721-9778 FAX (852) 2722-1369 ASIC/ASSP/Smart Cards Zone Industrielle 13106 Rousset Cedex, France TEL (33) 4-42-53-60-00 FAX (33) 4-42-53-60-01 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TEL 1(719) 576-3300 FAX 1(719) 540-1759 Scottish Enterprise Technology Park Maxwell Building East Kilbride G75 0QR, Scotland TEL (44) 1355-803-000 FAX (44) 1355-242-743 Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan TEL (81) 3-3523-3551 FAX (81) 3-3523-7581 literature@atmel.com Web Site http://www.atmel.com (c) Atmel Corporation 2002. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Atmel's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel's products are not authorized for use as critical components in life support devices or systems. ATMEL (R) is the registered trademark of Atmel. Other terms and product names may be the trademarks of others. Printed on recycled paper. 2108A-BDC-07/02 0M |
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