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MITSUBISHI ICs (COMMUNICATION)
M64811AGP
1.1GHz/500MHz DUAL PLL FREQUENCY SYNTHESIZER FOR DIGITAL CELLULAR PHONE DESCRIPTION PIN CONFIGURATION (TOP VIEW) The M64811AGP is a 1.1GHz/500MHz band two-system one-chip PLL frequency synthesizer . Using a high performance Bi-CMOS process , the product contains one two-modulus (1/32 and 1/33) prescaler that accepts inputs up to 1.1GHz and another two-modulus (1/16 and 1/17) prescaler that accepts inputs up to 500MHz ,thus helping make the equipment compact . FEATURES
FIN1 GND CPS SI LE SLEEP1 SLEEP2
1 2 3 4 5 6 7
16 15 14 13 12 11 10
PD1 Vcc XIN XOUT XBo LOCK GND
* Operating supply voltage : 2.7V~3.6V FIN2 PD2 8 9 * Operating temperature : -30C~+85C * 2 PLL systems (1.1GHz and 500MHz) are on one chip . PLL1 : 700MHz~1.1GHz PLL2 : 100MHz~500MHz * Low power consumption (Icc=8mA Typ at Vcc=3V) . * Dividing ratio setting ranges : FIN1 for 1.1GHz VCO* * * * * N(VCO1)=1,024~131,071 FIN2 for 500MHz VCO* * * * * N(VCO2)=256~131,071 OSC for Fref * * * * * * * * * * * * * N(Fref)=5~2,047 * Each loop has input pin for sleep mode . Power supplies to 2 loops can be independently turned ON/OFF . Also can be controlled by the serial data . (When SLEEP1 and SLEEP2 is "H" . ) * The PLL standard oscillation circuit can adopt a B-E Colpitts type oscillation circuit to from a stable oscillation circuit. * Current controlled charge pump . (Icp=2mA const.) * Locked condition detecting output If a phase difference smaller than 3 times (t) of the OSC period continues for 15 periods or longer , the condition is judged as locked, and the LOCK terminal goes to "L" . (When , for example , fosc=19.2 MHz , t=156 ns) * PLL lock/unlock status indicate function . (Judged in the system turned on if the other system is turned off . ) * Small package (16pin SSOP, lead pitch : 0.65mm) APPLICATION * Digital cordless phone (CT2) * Digital cellular phone (PDC)
1
GND
10 2
BLOCK DIAGRAM
GND
FIN2
SWALLOW / PROGRAMMABLE COUNTER
PHASE DETECTOR PD2
LPF
8
500MHz 2-MODULUS PRESCALER (1/16, 1/17)
LOCK DETECTOR
9
CHARGE PUMP
SLEEP1 DATA LATCH
6
PLL1 ON/OFF
VCO
SLEEP2
7
PLL2 ON/OFF
XIN OSC
PROGRAMMABLE REFERENCE COUNTER
1.1GHz/500MHz DUAL PLL FREQUENCY SYNTHESIZER FOR DIGITAL CELLULAR PHONE
TCXO
14
XOUT
13
XBo DATA LATCH PHASE DETECTOR
SWALLOW / PROGRAMMABLE COUNTER 1.1GHz 2-MODULUS PRESCALER (1/32, 1/33)
VCC
15
12
FIN1
1
PD1
LPF
SLEEP Control DATA LATCH SHIFT RESISTER LATCH SELECT
LOCK DETECTOR
CHARGE PUMP
16
VCO
SI
4
CPS
3
5
11
MITSUBISHI ICs (COMMUNICATION)
M64811AGP
LE
LOCK
2
MITSUBISHI ICs (COMMUNICATION)
M64811AGP
1.1GHz/500MHz DUAL PLL FREQUENCY SYNTHESIZER FOR DIGITAL CELLULAR PHONE
FUNCTION DESCRIPTION OF PINS
Pin No. 1 2 3 4 5 6 7 8 9 10 11 Pin Identification FIN1 GND CPS SI LE Input from the VCO , Fmax = 1.1GHz . Ground . Clock pulse input . Shift register clock input pin . Shift register data input pin Description
Binary serial data input .
Load enable input . When LE is HIGH , data stored in the shift registers is loaded into the appropriate latch . PLL1 power control . "H" = normal operation , "L"=power down . PLL2 power control . "H" = normal operation , "L"=power down . Input from the VCO , Fmax = 500MHz . Charge pump2 output . Tristate output . High Z when PLL2 power is off . Ground . When loops are locked ********"L" , When one of loops is unlocked********"High Z" . If one loop is sleep mode , the status of the other loop is checked for judgment . Buffer output of oscillator .
SLEEP1 SLEEP2 FIN2 PD2 GND LOCK
12 13 14 15 16
XBo XOUT
Crystal Oscillator input . XIN Vcc PD1 Power supply . Vcc = 2.7~3.6V . Charge pump1 output . Tristate output . High Z when PLL1 power is off .
3
MITSUBISHI ICs (COMMUNICATION)
M64811AGP
1.1GHz/500MHz DUAL PLL FREQUENCY SYNTHESIZER FOR DIGITAL CELLULAR PHONE FUNCTION DESCRIPTION
1.Data Input L S CPS Note 1) Note 2) Note 3) At the leading edge of the CPS input , the status of the SI input is written into the shift register . The bit just before LE becomes "H" is LSB , and SI before MSB becomes invalid . When LE is "H" , the data stored in the shift registers is loaded into the appropriate latch . E
Invalid MSB LSB
I
D1
D2
D19
D20
D21 D22
2.Input Signal Timing
tCR tRH
L S
E I
Valid tsu data th
CPS
tWH tWL
tsu=th=tWH=tWL=0.1smin. tCR=tRH=0.1smin.
3.Bit Configuration of Shift Register
LSB
Shift register Power on/off setting Data latch setting
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
DA
DB
DC
DD
DE MSB
Invalid
*
*
*
H
H
2
0
2
1
2
2
2
3
2
4
2
5
2
6
2
7
2
8
2
9
2
10
Dividing ratio of reference counter for reference frequency * * * L H
MSB
2
2
0
2
1
2
2
2
3
2
4
2
0
2
1
2
2
3
2
4
2
5
2
6
2
7
2
8
2
9
2
10
2
11
Invalid
Dividing ratio of swallow counter * * * H L
Dividing ratio of programable counter for local oscillator 1
MSB
10
2
0
2
1
2
2
2
3
2
0
2
1
2
2
2
3
2
4
2
5
2
6
2
7
2
8
2
9
2
2
11
2
12
Invalid
Dividing ratio of swallow counter
Dividing ratio of programable counter for local oscillator 2
4
MITSUBISHI ICs (COMMUNICATION)
M64811AGP
1.1GHz/500MHz DUAL PLL FREQUENCY SYNTHESIZER FOR DIGITAL CELLULAR PHONE
Note 4)
Power on/off control of PLL system is set by DA , DB , and DF .
External Control Pin
Serial Data DA * 0 0 1 1 0 0 1 1 1 1 1 1 0 0 0 0 DB * 0 1 0 1 0 1 0 1 1 1 0 0 1 1 0 0 DC * * * * * * * * * 1 0 1 0 1 0 1 0 PLL1 OFF OFF OFF OFF OFF ON ON OFF OFF OFF OFF OFF OFF ON ON ON ON
Description PLL2 OFF ON OFF ON OFF OFF OFF OFF OFF OFF OFF ON ON OFF OFF ON ON OSC ON ON ON ON ON ON ON ON ON OFF ON ON ON ON ON ON ON XBo ON ON ON ON ON ON ON ON ON OFF ON OFF ON OFF ON OFF ON
SLEEP1 L L L L L H H H H H H H H H H H H
SLEEP2 L H H H H L L L L H H H H H H H H
ON;Power on , OFF;Power off
Note 5) DD and DE are used to select latched data to be updated.
Data DD DE
Description Unused. Data latched for local oscillator 1 is updated. Data latched for local oscillator 2 is updated. Data latched for reference frequency .
0 0 1 1
0 1 0 1
5
MITSUBISHI ICs (COMMUNICATION)
M64811AGP
1.1GHz/500MHz DUAL PLL FREQUENCY SYNTHESIZER FOR DIGITAL CELLULAR PHONE
Note 6) Dividing ratio of the reference counter for reference frequency is given by 11-bit binary coads . N(fREF1)=5~2047 Note 7) Dividing ratio N(VCO1) of VCO1 for local oscillator1 is given by 5-bit swallow counter and 12-bit programable counter . N(VCO1)=32 x M+A (A6
MITSUBISHI ICs (COMMUNICATION)
M64811AGP
1.1GHz/500MHz DUAL PLL FREQUENCY SYNTHESIZER FOR DIGITAL CELLULAR PHONE
4.Charge Pump and LOCK Detection
Reference frequency(Fref)
Divided output of local oscillator Charge pump output LOCK output
(FVCO/N )
"HiZ" "Source" 1 2 3 "Sink"
15
Note 9)
If the phase of divided local oscillator output (FVCO/N) is behind that of the reference frequency (Fref) , the charge pump output becomes "Source" status , if advancing , "Sink" status .
Note 10) If a phase difference smaller than 3 times of the OSC period continues for 15 periods longer , the LOCK output becomes "L" . ( When , for example , Fosc = 19.2 MHz , t = 156 ns)
Note 11) If one of the power supplies to PLLs is turned off , a judgment is made based on only the condition of the other loop .
Note 12) The LOCK output circuit yields an open drain N-channel transistor output . It should be pulled up to Vcc .
5.Sleep Mode Input
By status of SLEEP1 and SLEEP2 , each PLL can be selected to either sleep mode ( Power supply is turned off . ) or operation mode . If SLEEP input is "H" , the PLL becomes normal operation mode . ( Power supplies to turn ON/OFF can be controlled by the serial data ; submit to note 4 . ) If SLEEP input is "L" , the PLL becomes sleep mode . ( Power supply is turned off . )
7
MITSUBISHI ICs (COMMUNICATION)
M64811AGP
1.1GHz/500MHz DUAL PLL FREQUENCY SYNTHESIZER FOR DIGITAL CELLULAR PHONE INPUT / OUTPUT CIRCUIT DIAGRAM
1 SI,CPSVCC
FIN
3
OSC input
4
Charge Pump output(PD1,PD2)
VDD
XIN XOUT XBo PD
5
LOCK
LOCK
8
MITSUBISHI ICs (COMMUNICATION)
M64811AGP
1.1GHz/500MHz DUAL PLL FREQUENCY SYNTHESIZER FOR DIGITAL CELLULAR PHONE
ABSOLUTE MAXIMUM RATINGS (Ta= -30~85C, unless otherwise specified . )
Symbol Vcc V VO Pd Vopd Topr Tstg
I
Parameter Supply Voltage Input Voltage Output Voltage Power Dissipation Open Drain Voltage Operating Temperature Storage Temperature GND=0V
Test Condition
Ratings Min. -0.3 -0.3 -0.3 Max. 4.5 4.5 4.5 250 -0.3 -30 -40 4.5 85 125
Unit V V V mW V
SI , CPS , LE pin : GND=0V Output pin : GND=0V
Ta=85C( Allowable dissipation of package )
GND=0V
C C
RECOMMENDED OPERATING CONDITIONS (Ta= -30~85C, unless otherwise specified . )
Symbol Vcc FIN1 Operating Frequency FIN2 VIN1 Input Sensitivity VIN2 VXIN Oscillator Sensitivity
@
Parameter Supply Voltage Vcc=2.7~3.6V
Test Condition
Min. 2.7 0.7 100
Limits Typ.
Max. 3.6 1.1 500 2
Unit V GHz MHz dBm
FIN1=1.0~2.0GHz FIN2=100~500MHz Vcc=2.7~3.6V
-10 -16 0.4
-4 1.0 Vp-p
@Recommendation : X'tal (19.2MHz)
ELECTRICAL CHARACTERISTICS (Ta= 25C, unless otherwise specified . )
Symbol I PDSOURCE
Parameter Charge Pump Output (Source) Current Charge Pump Output (Sink) Current
Pin
Test Condition
Min.
Limits Typ. 2.0
Max.
Unit
I PDSINK
PD1 , PD2
Vcc=3.0V , VPD=Vcc/2 -2.0 Vcc=3V , Both PLLs are on . Vcc=3V , Only PLL1 is on . 8.0 5.5 4.5 10
mA
Icc1 Icc2 Supply Current Icc3 Icc4 Vcc
mA
Vcc=3V , Only PLL2 is on . Vcc=3V , Both PLLs are off .
A
HANDLING PRECAUTIONS 1. This IC contains fine structure components to achieve high performance . Therefore , take extra precaution to protect the IC from surge voltage caused by static electricity . 2. If one of two PLLs is not used , please make power supply of that turn off .
9

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