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| HN62W4018M Series 1048576-word x 16-bit CMOS MASK Programmable ROM ADE-203-447(Z) Preliminary Rev. 0.0 Nov. 1, 1995 Description The HN62W4018M is a 16-Mbit CMOS mask-programmable ROM organized as 1,048,576-word by 16bit. Realizing low power consumption, this memory is allowed for battery operation. And a high speed access of 120/150 ns (max) is the most suitable to the system using a high speed micro-computer by 16bit. Features * * Low voltage operation: 3.3 V 0.3 V High speed Normal access time: 120 ns/150 ns (max) Page access time: 40 ns/50 ns (max) Low power consumption Active : 360 mW (max) Standby : 0.72 mW (max) Power down mode : 36 W (max) 8-word page access mode Three-state data output for or-tying LVTTL compatible * * * * Ordering Information Type No. HN62W4018MTA-12 HN62W4018MTA-15 Access time 120 ns 150 ns Package 48-pin plastic TSOP - II (TTP-48D) Note: The specifications of device are subject to change without notice. Please contact your nearest Hitachi's Sales Dept. regarding specifications. HN62W4018M Series Pin Arrangement HN62W4018MTA A0 A1 A2 A3 A4 VDD D0 D1 D2 D3 VSS VDD D4 D5 D6 D7 VSS A5 A6 A7 A8 A9 A10 A11 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 (Top view) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 PWD NC A19 OE CE VSS D15 D14 D13 D12 VSS VDD D11 D10 D9 D8 VDD A18 A17 A16 A15 A14 A13 A12 Pin Description Pin name A3 to A19 A0 to A2 D0 to D15 CE OE PWD NC VDD VSS Function Address inputs Page address inputs Data output Chip enable Output enable Power down input No connection Power supply Ground 2 HN62W4018M Series Block Diagram A19 to A9 A8 to A3 A2 to A0 OE CE PWD Control Logic 3-state output buffer Address buffer X Decoder Memory array Y Decoder Y Gating Page Decoder D0 to D15 Mode Selection Pin Data output Mode Power down Standby Output disable Read (16-bit) PWD L H H H CE x *1 Address input LSB -- -- -- A0 MSB -- -- -- A19 OE x x H L D0-D15 High-Z *2 H L L High-Z High-Z D0 to D15 Notes: 1. x: Don't care. 2. High-Z: High impedance. 3 HN62W4018M Series Absolute Maximum Ratings Parameter Supply voltage All input and output voltage Operating temperatue range Storage temperature range Temperature under bias Note: 1. With respect to V SS Symbol VDD Vin, Vout Topr Tstg Tbias Value -0.3 to +5.5 -0.3 to VDD + 0.3 0 to +70 -55 to +125 -20 to +85 Unit V V C C C Note 1 1 Recommended DC Operating Conditions (VSS = 0 V, Ta = 0 to 70C) Parameter Supply voltage Input voltage Symbol VDD VIH VIL Min 3.0 2.2 -0.3 Typ 3.3 -- -- Max 3.6 VDD + 0.3 0.8 Unit V V V DC Characteristics (VDD = 3.3 V 0.3 V, VSS = 0 V, Ta = 0 to 70C) Parameter Active supply current Standby power supply current Symbol I DD I SB1 I SB2 Power down supply current Input leakage current Output leakage current Output voltage I PWD |IIL| |IOL | VOH VOL Min -- -- -- -- -- -- 2.4 -- Max 100 200 3 10 10 10 -- 0.4 Unit mA A mA A A A V V Test conditions VDD = 3.6 V, IDOUT = 0 mA, tRC = min VDD = 3.6 V, CE VDD - 0.2 V VDD = 3.6 V, CE 2.2 V VDD = 3.6 V, PWD 0.2 V Vin = 0 V to VDD CE = 2.2 V, Vout = 0 V to VDD I OH = -2 mA I OL = 2 mA Capacitance (VDD = 3.3 V 0.3 V, VSS = 0 V, Ta = 25C, Vin = 0 V, f = 1 MHz) Parameter Input capacitance *1 *1 Symbol Cin Cout Min -- -- Max 10 15 Unit pF pF Output capacitance Note: 1. This parameter is sampled and not 100% tested. 4 HN62W4018M Series AC Characteristics (VDD = 3.3 V 0.3 V, VSS = 0 V, Ta = 0 to 70C) * * * * Output load: 1TTL + CL = 100 pF (including jig capacitance) Input pulse level: 0.4 V to 2.4 V Input and output timing reference levels: 1.4 V Input rise and fall time: 5 ns HN62W4018M-12 Parameter Read cycle time Page read cycle time Address access time Page address access time CE access time OE access time Output hold time from address change Output hold time from CE Output hold time from OE Output hold time from PWD CE to output in high-Z OE to output in high-Z CE to output in low-Z OE to output in low-Z Recovery time from PWD Note: Symbol t RC t PC t AA t PA t ACE t OE t DHA t DHC t DHO t DHP t CHZ t OHZ t CLZ t OLZ tR Min 120 40 -- -- -- -- 0 0 0 0 -- -- 5 5 10 Max -- -- 120 40 120 40 -- -- -- -- 40 40 -- -- -- HN62W4018M-15 Min 150 50 -- -- -- -- 0 0 0 0 -- -- 5 5 10 Max -- -- 150 50 150 50 -- -- -- -- 50 50 -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns s 1 1 Note 1. t CHZ and tOHZ are defined as the time at which the output achieves the open circuit conditions and are not referred to output voltage levels. 5 HN62W4018M Series Timing Waveforms Normal Mode t RC Address t AA t ACE CE t CLZ t OE OE t OLZ Dout High-Z Valid data t DHO t OHZ High-Z t DHC t CHZ t DHA Notes: 1. tDHA, t DHC, tDHO: Determined by faster. 2. t AA, tACE , tOE: Determined by slower. 3. t CLZ , t OLZ : Determined by slower. Page Mode A3 to A19 t RC A0 to A2 t PC t PC t PA t AA t DHA t PA t DHA t DHA t DHA Dout Valid data Valid data Valid data Valid data Notes: 1. CE and OE are enable. 6 HN62W4018M Series Power Down Mode CE Address t AA Dout Valid data t DHP PWD High-Z tR Valid data Power Up Sequence VDD 3.0V 0V CE t P 100s t ACE Address t AA Dout Valid data tR 10s PWD Notes: 1. This device is used ATD(Address Transition Detector). Therefore, transfer either CE or address(A19 to A3) after power up to 3.0 V. 2. tP, tR: Determined by slower. 7 HN62W4018M Series Package Dimensions HN62W4018MTA Series (TTP-48D) Unit: mm 19.68 20.00 Max 48 25 1 0.30 0.10 0.94 Max 0.80 0.13 M 24 15.57 0.10 0 - 5 +0.03 -0.05 13.97 0.17 0.05 1.20 Max 0.80 0.10 0.13 0.50 0.10 8 |
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