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V436616Y24V 3.3 VOLT 16M x 64 HIGH PERFORMANCE SDRAM UNBUFFERED SODIMM
PRELIMINARY
s JEDEC-standard 144 pin, Small-Outline, Dual in line Memory Module (SODIMM) s Serial Presence Detect with E2PROM s Nonbuffered s Fully Synchronous, All Signals Registered on Positive Edge of System Clock s Single +3.3V ( 0.3V) Power Supply s All Device Pins are LVTTL Compatible s 8192 Refresh Cycles every 64 ms s Self-Refresh Mode s Internal Pipelined Operation; Column Address can be changed every System Clock s Auto Precharge and Piecharge all Banks by A10 s Data Mask Function by DQM s Mode Register Set Programming s Programmable (CAS Latency:2, 3 Clocks)
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Features
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V436616Y24V Rev. 1.0 January 2002
Description
The V436616Y24V memory module is organized 16,777,216 x 64 bits in a 144 pin SODIMM. The 16M x 64 memory module uses 4 Mosel-Vitelic 16M x 16 SDRAM. The x64 modules are ideal for use in high performance computer systems where increased memory density and fast access times are required.
Speed Grade
133MHz CL2,3 133MHz CL3 100MHz CL2,3
Part Number
V436616Y24VXXG-75PC V436616Y24VXXG-75 V436616Y24VXXG-10PC
Configuration
16M x 64 16M x 64 16M x 64
4M x 16
4M x 16
59
61
143
Pin 2 on Backside
Pin 144 on Backside
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V436616Y24V
Front DQMB1 DQMB5 VDD VDD A0 A3 A1 A4 A2 A5 VSS VSS DQ8 DQ40 DQ9 DQ41 DQ10 DQ42 DQ11 DQ43 VDD VDD DQ12 DQ44 Pin 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 Front DQ13 DQ45 DQ14 DQ46 DQ15 DQ47 VSS VSS NC NC NC NC CLK0 CKE0 VDD VDD RAS CAS WE CKE1 CS0 NC CS1 A12 Pin 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 Back NC CLK1 VSS VSS NC NC NC NC VDD VDD DQ16 DQ48 DQ17 DQ49 DQ18 DQ50 DQ19 DQ51 VSS VSS DQ20 DQ52 DQ21 DQ53 Pin 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 Back DQ22 DQ54 DQ23 DQ55 VDD VDD A6 A7 A8 BA0 VSS VSS A9 BA1 A10 A11 VDD VDD DQMB2 DQMB6 DQMB3 DQMB7 VSS VSS Pin 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 Back DQ24 DQ56 DQ25 DQ57 DQ26 DQ58 DQ27 DQ59 VDD VDD DQ28 DQ60 DQ29 DQ61 DQ30 DQ62 DQ31 DQ63 VSS VSS SDA SCL VDD VDD
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Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Front VSS VSS DQ0 DQ32 DQ1 DQ33 DQ2 DQ34 DQ3 DQ35 VDD VDD DQ4 DQ36 DQ5 DQ37 DQ6 DQ38 DQ7 DQ39 VSS VSS DQMB0 DQMB4 Pin 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
Pin Configurations (Front Side/Back Side)
Note:
1. RAS, CAS, WE CASx, CSx are active low signals.
Pin Names
A0-A12, BA0, BA1 DQ0-DQ63 RAS CAS WE CS0, CS1 DQMB0-DQMB7 CKE0, CKE1 CLK0, CLK1 SDA SCL VDD VSS NC Address, Bank Select Data Inputs/Outputs Row Address Strobes Column Address Strobes Write Enable Chip Select Output Enable Clock Enable Clock Serial Input/Output Serial Clock Power Supply Ground No Connect (Open)
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Block Diagram
CSO WE WE CS UDQM U0 DQMB1 LDQM DQ8-15 DQMB5 WE CS UDQM U2 LDQM DQ40-47
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V
MOSEL VITELIC MANUFACTURED
Part Number Information
4
3
66
16
Y
2
4
V
X
T
G - XX
SPEED 75PC = 133MHz CL3,2 75 = 133MHz CL3 10PC = 100MHz CL3,2 LEAD FINISH G = GOLD
SDRAM 3.3V WIDTH DEPTH 168 PIN Unbuffered DIMM X16 COMPONENT REFRESH RATE 8K
COMPONENT PACKAGE, T = TSOP COMPONENT A=0.17u B=0.14u REV LEVEL LVTTL 4 BANKS
DQMB0
DQ0-7
DQMB4
DQ32-39
DQMB2
WE CS UDQM U1
DQ16-23
DQMB6
WE CS UDQM U3
DQ43-54
DQMB3
LDQM
DQ24-31
DQMB7
LDQM
DQ55-63
C1-C4 VDD VSS A0-A12, BA0, BA1 CKE0 CKEI RAS CAS U0-U7 CLK0 U0-U7 U0-U3 U4-U7 U0-U3 U0-U3 SCL A0 A1 A2 SDA 10 U0, U1 10 U2, U3 SPD
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V436616Y24V
written into the E2PROM device during module production using a serial presence detect protocol (I 2C synchronous 2-wire bus)
E2PROM
A serial presence detect storage device - is assembled onto the module. Information about the module configuration, speed, etc. is
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Byte Number
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CS Latencies 24 25 26 27
V436616Y24V Rev. 1.0 January 2002
Serial Presence Detect Information
SPD-Table for modules:
Hex Value Function Described
Number of SPD bytes Total bytes in Serial PD Memory Type Number of Row Addresses (without BS bits) Number of Column Addresses (for x16 SDRAM) Number of DIMM Banks Module Data Width Module Data Width (continued) Module Interface Levels SDRAM Cycle Time at CL=3 SDRAM Access Time from Clock at CL=3 Dimm Config (Error Det/Corr.) Refresh Rate/Type SDRAM width, Primary Error Checking SDRAM Data Width Minimum Clock Delay from Back to Back Random Column Address Burst Length Supported Number of SDRAM Banks Supported CAS Latencies
SPD Entry Value
128 256 SDRAM 13 9
-75PC
80 08 04 0D 09
-75
80 08 04 0D 09
-10PC
80 08 04 0D 09
1 64 0 LVTTL 7.5 ns/10.0 ns 5.4 ns/6.0 ns none Self-Refresh,7.8 s x16 n/a / x16 tccd = 1 CLK 1, 2, 4, 8 4 CL =2, 3 CS Latency = 0 WL = 0 Non Buffered/Non Reg. Vcc tol 10% 7. 5 ns/10.0 ns
01 40 00 01 75 54 00 82 10 00 01
01 40 00 01 75 54 00 82 10 00 01
01 40 00 01 A0 60 00 82 10 00 01
0F 04 06 01 01 00 0E 75
0F 04 06 01 01 00 0E A0
0F 04 06 01 01 00 0E A0
WE Latencies SDRAM DIMM Module Attributes SDRAM Device Attributes: General Minimum Clock Cycle Time at CAS Latency = 2 Maximum Data Access Time from Clock for CL = 2 Minimum Clock Cycle Time at CL = 1 Maximum Data Access Time from Clock at CL =1 Minimum Row Precharge Time
5.4 ns/6.0 ns
54
60
60
Not Supported Not Supported
00 00
00 00
00 00
15 ns/20 ns
0F
14
14
4
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Byte Number
28 29 30 31 32 33 34 35 36-61 62 63 64 65-71 72 73-90 91-92 93 94 95-98 99-125 126 127 128+ Reserved
SPD-Table for modules: (Continued)
Hex Value Function Described
Minimum Row Active to Row Active Delay tRRD Minimum RAS to CAS Delay tRCD Minimum RAS Pulse Width tRAS Module Bank Density (Per Bank) SDRAM Input Setup Time SDRAM Input Hold Time SDRAM Data Input Setup Time SDRAM Data Input Hold Time Superset Information (May be used in Future) SPD Revision Checksum for Bytes 0 - 62 Manufacturer's JEDEC ID Code Manufacturer's JEDEC ID Code (cont.) Manufacturing Location Module Part Number (ASCII) PCB Identification Code Assembly Manufacturing Date (Year) Assembly Manufacturing Date (Week) Assembly Serial Number 1 = US, 2 = Taiwan V436616Y24V Current PCB Revision Binary Coded year (BCD) Binary Coded week (BCD) byte 95 = LSB, byte 98 = MSB 00 64 00 64 00 64 Mosel Vitelic Revision 2
SPD Entry Value
14 ns/15 ns/16 ns
-75PC
0E
-75
0F
-10PC
10
15 ns/20 ns 42 ns/45 ns 128 Mbyte 1.5 ns 0.8 ns 1.5 ns 0.8 ns
0F 2A 20 15 08 15 08 00 02 E4 40 00
14 2D 20 15 08 15 08 00 02 29 40 00
14 30 20 20 10 20 10 00 12 9A 40 00
Intel Specification for Frequency Supported frequency Unused Storage Location
00
00
00
DC Characteristics
TA = 0C to 70C; VSS = 0 V; VDD, VDDQ = 3.3V 0.3V
Limit Values Symbol
VIH V IL V OH V OL
Parameter
Input High Voltage Input Low Voltage Output High Voltage (IOUT = -4.0 mA) Output Low Voltage (IOUT = 4.0 mA)
Min.
2.0 -0.5 2.4 --
Max.
VCC +0.3 0.8 -- 0.4
Unit
V V V V
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Limit Values
Standby and Refresh Currents1
TA = 0C to 70C, VCC = 3.3V 0.3V
Symbol Parameter
ICC1 Operating Current
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Symbol
II(L) IO(L)
Parameter
Input Leakage Current, any input (0 V < VIN < 3.6 V, all other inputs = 0V) Output leakage current (DQ is disabled, 0V < VOUT < V CC)
Min.
-40
Max.
40
Unit
A A
-40
40
Capacitance
Symbol
CI1 CI2 CICL CI3 CI4 CSC CIO
TA = 0C to 70C; VDD = 3.3V 0.3V, f = 1 MHz
Parameter
Input Capacitance (A0 to A11, RAS, CAS, WE) Input Capacitance (CS0, CSI) Input Capacitance (CLK0-CLK1) Input Capacitance (CKE0, CKEI) Input Capacitance (DQMB0-DQMB7) Input Capacitance (SCL, SA0-2) Input/Output Capacitance
Limit Values (Max.)
65 32 38 65 13 8 10
Unit
pF pF pF pF pF pF pF
Absolute Maximum Ratings
Parameter
Voltage on VDD Supply Relative to V SS Voltage on Input Relative to VSS Operating Temperature Storage Temperature Power Dissipation
Max.
-1 to 4.6 -1 to 4.6 0 to +70 -55 to 125 4
Units
V V C C W
Test Conditions
Burst length = 4, CL = 3 tRC> = tRC(min), tCK> = tCK(min), IO = 0 mA 2 Bank Interleave Operation
-75PC/75
920
-10PC
840
Unit
mA
Note
1,2
ICC2P ICC2N
Precharged Standby Current in Power CKE< = VIL(max), tCK> = tCK(min) Down Mode Precharged Standby Current in Non-Power Down Mode CKE> = VIH(min), tCK> = tCK(min), Input changed once in 3 cycles
8
8
mA
160
140
mA
CS = High
ICC3P
Active Standby Current in Power Down Mode
CKE< = VIL(max), tCK> = tCK(min)
40
40
mA
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Test Conditions -75PC/75
200
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Symbol Parameter
ICC3N ICC4 Active Standby Current in Non-Power CKE> = VIH(min), tCK> = tCK(min), Input Down Mode changed one time Burst Operating Current tRC = Infinite, CL = 3, tCK> = tCK(min), IO = 0 mA 2 Banks Activated tRC>= tRC(min) CKE = <0.2 V Standard L-Version 600 ICC5 ICC6 Auto Refresh Current Self Refresh Current 960 12 6.8 12
-10PC
180
Unit
mA
Note
CS = High
480
mA
1, 2
880
mA mA
1,2 1,2
6.8
AC Characteristics
TA = 0 to 70C; VSS = 0V; VCC = 3.3V 0.3V, tT = 1 ns
Limit Values -75PC # Symbol Parameter Min. Max. Min. -75 Max. -10PC Min. Max. Unit Note
Clock and Clock Enable
1 tCK Clock Cycle Time CAS Latency = 3 CAS Latency = 2 Clock Frequency CAS Latency = 3 CAS Latency = 2 Access Time from Clock CAS Latency = 3 CAS Latency = 2 Clock High Pulse Width Clock Low Pulse Width Transition Tim 7.5 7.5 - - 7.5 10 - - 10 10 - - ns ns
2
tCK
- -
133 133
- -
133 100
- -
100 100
MHz MHz 2, 4
3
tAC
- _ 2.5 2.5 1
5.4 5.4 - - -
- _ 2.5 2.5 1
5.4 6 - - -
- _ 3 3 1
6 6 - - -
ns ns ns ns ns
4 5 6
tCH tCL tT
Setup and Hold Times
7 8 9 10 11 12 tIS tIH tCKS tCKH tRSC tSB Input Setup Time Input Hold Time Input Setup Time CKE Hold Time Mode Register Set-up Time Power Down Mode Entry Time 1.5 0.8 1.5 0.8 15 0 - - - - - 7.5 1.5 0.8 1.5 0.8 15 0 - - - - - 7.5 2 1 2 1 15 0 - - - - - 10 ns ns ns ns ns ns 5 5 5 5
Common Parameters
13 tRCD Row to Column Delay Time 15 - 20 - 20 - ns 6
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AC Characteristics
TA = 0 to 70C; VSS = 0V; VCC = 3.3V 0.3V, tT = 1 ns (Continued)
Limit Values -75PC #
14 15 16 17
-75 Min.
20 45 60 15
-10PC Min.
20 45 70 20
Symbol
tRP tRAS tRC tRRD tCCD
Parameter
Row Precharge Time Row Active Time Row Cycle Time Activate(a) to Activate(b) Command Period CAS(a) to CAS(b) Command Period
Min.
15 42 60 14
Max.
- 100K - -
Max.
- 100K - -
Max.
- 100K - -
Unit
ns ns ns ns
Note
6 6 6 6
18
1
-
1
-
1
-
CLK
Refresh Cycle
19 20 tREF tSREX Refresh Period (8192 cycles) Self Refresh Exit Time 64 10
-- --
64 10
-- --
64 10
-- --
ms ns
Read Cycle
21 22 23 24 tOH tLZ tHZ tDQZ Data Out Hold Time Data Out to Low Impedance Time Data Out to High Impedance Time DQM Data Out Disable Latency 3 1 3 2 - - 7.5 - 3 1 3 2 - - 7.5 - 3 1 3 2 - - 10 - ns ns ns CLK 7 2
Write Cycle
25 26 tWR tDQW Write Recovery Time DQM Write Mask Latency 2 0 - - 2 0 - - 2 0 - - CLK CLK
Notes:
1.The specified values are valid when addresses are changed no more than once during t CK(min.) and when No Operation commands are registered on every rising clock edge during t RC(min). Values are shown per module bank. 2. The specified values are valid when data inputs (DQ's) are stable during t RC(min.). 3. All AC characteristics are shown for device level. An initial pause of 100 s is required after power-up, then a Precharge All Banks command must be given followed by 8 Auto Refresh (CBR) cycles before the Mode Register Set Operation can begin. 4. AC timing tests have VIL = 0.4V and V IH = 2.4V with the timing referenced to the 1.4V crossover point. The transition time is measured between VIH and VIL. All AC measurements assume tT = 1 ns with the AC output load circuit shown. Specific tac and toh parameters are measured with a 50 pF only, without any resistive termination and a input signal of 1V / ns edge rate between 0.8V and 2.0V.
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V436616Y24V
10. 11.
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.
tCH 2.4V CLOCK 0.4V
+ 1.4 V 50 Ohm Z=50 Ohm I/O 50 pF
tCL
tSETUP tHOLD
tT
INPUT
1.4V
tAC tLZ tOH
tAC
I/O 50 pF
1.4V
OUTPUT
Measurement conditions for tac and toh
tHZ
5. If clock rising time is longer than 1 ns, a time (tT/2 -0.5) ns has to be added to this parameter. 6. Rated at 1.5V 7. If tT is longer than 1 ns, a time (tT -1) ns has to be added to this parameter. 8. Any time that the refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh commands must be given to "wake-up" the device. 9. Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after CKE returns high. Self Refresh Exit is not complete until a time period equal to tRC is satisfied once the Self Refresh Exit command is registered. Referenced to the time which the output achieves the open circuit condition, not to output voltage levels. tDAL is equivalent to t DPL + tRP.
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V436616Y24V
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Package Diagram
144 Pin SODIMM
1.00 0.787 1 28 29 143 Pin 2 on Backside 3.3V 2.661 NOTE: 1. All dimensions in inches. Tolerances 0.005 unless otherwise specified. Pin 144 on Backside
V436616Y24V Rev. 1.0 January 2002
0.039
0.140
V43644YO4V(C)TG-10PC-04
10
V436616Y24V
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V436616Y24V Rev. 1.0 January 2002
Module Label Information
Module Density
MOSEL VITELIC
Part Number Criteria of PC100 or PC133 (refer to MVI datasheet) DIMM manufacture date code
V436616Y24XXX-XX 128MB CLX PC133U-XXX-542-A XXXX-XXXXXXX Assembly in Taiwan
CAS Latency 2=CL2 3=CL3
PC133 U -XXX
UNBUFFERED DIMM CL= 3 or 2 (CLK) tRCD= 3 or 2 (CLK) tRP= 3 or 2 (CLK)
54 2
A
Gerber file Intel PC100 x16 Based JEDEC SPD Revision 2
tAC = 5.4 ns
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V436616Y24V
U.S.A.
3910 NORTH FIRST STREET SAN JOSE, CA 95134 PHONE: 408-433-6000 FAX: 408-433-0952
WEST
3910 NORTH FIRST STREET SAN JOSE, CA 95134 PHONE: 408-433-6000 FAX: 408-433-0952
The information in this document is subject to change without notice. MOSEL VITELIC makes no commitment to update or keep current the information contained in this document. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of MOSEL-VITELIC.
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WORLDWIDE OFFICES
TAIWAN
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U.S. SALES OFFICES
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(c) Copyright , MOSEL VITELIC Corp.
Printed in U.S.A.
MOSEL VITELIC subjects its products to normal quality control sampling techniques which are intended to provide an assurance of high quality products suitable for usual commercial applications. MOSEL VITELIC does not do testing appropriate to provide 100% product quality assurance and does not assume any liability for consequential or incidental arising from any use of its products. If such products are to be used in applications in which personal injury might occur from failure, purchaser must do its own quality assurance testing appropriate to such applications.
V436616Y24V Rev. 1.0 January 2002
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