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PCA9545A
4-channel I2C switch with interrupt logic and reset
Rev. 03 -- 3 March 2005 Product data sheet
1. General description
The PCA9545A is a quad bi-directional translating switch controlled via the I2C-bus. The SCL/SDA upstream pair fans out to four downstream pairs, or channels. Any individual SCx/SDx channel or combination of channels can be selected, determined by the contents of the programmable control register. Four interrupt inputs, INT0 to INT3, one for each of the downstream pairs, are provided. One interrupt output, INT, acts as an AND of the four interrupt inputs. An active LOW reset input allows the PCA9545A to recover from a situation where one of the downstream I2C-buses is stuck in a LOW state. Pulling the RESET pin LOW resets the I2C-bus state machine and causes all the channels to be deselected as does the internal Power-on reset function. The pass gates of the switches are constructed such that the VDD pin can be used to limit the maximum high voltage which will be passed by the PCA9545A. This allows the use of different bus voltages on each pair, so that 1.8 V or 2.5 V or 3.3 V parts can communicate with 5 V parts without any additional protection. External pull-up resistors pull the bus up to the desired voltage level for each channel. All I/O pins are 5 V tolerant.
2. Features
s s s s s s s s s s s s s s s s s 1-of-4 bi-directional translating switches I2C-bus interface logic; compatible with SMBus standards 4 active LOW interrupt inputs Active LOW interrupt output Active LOW reset input 2 address pins allowing up to 4 devices on the I2C-bus Channel selection via I2C-bus, in any combination Power-up with all switch channels deselected Low Ron switches Allows voltage level translation between 1.8 V, 2.5 V, 3.3 V and 5 V buses No glitch on power-up Supports hot insertion Low stand-by current Operating power supply voltage range of 2.3 V to 5.5 V 5 V tolerant Inputs 0 kHz to 400 kHz clock frequency ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115, and 1000 V CDM per JESD22-C101 s Latch-up protection exceeds 100 mA per JESD78
Philips Semiconductors
PCA9545A
4-channel I2C switch with interrupt logic and reset
s Three packages offered: SO20, TSSOP20, and HVQFN20
3. Ordering information
Table 1: Ordering information Tamb = -40 C to +85 C Type number PCA9545ABS PCA9545AD PCA9545APW Package Name HVQFN20 SO20 TSSOP20 Description Version plastic thermal enhanced very thin quad flat package; SOT662-1 no leads; 20 terminals; body 5 x 5 x 0.85 mm plastic small outline package; 20 leads; body width 7.5 mm plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT163-1 SOT360-1
Standard packing quantities and other packaging data are available at www.standardproducts.philips.com/packaging.
4. Marking
Table 2: Marking codes Topside mark 9545A PCA9545AD PA9545A Type number PCA9545ABS PCA9545AD PCA9545APW
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Product data sheet
Rev. 03 -- 3 March 2005
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Philips Semiconductors
PCA9545A
4-channel I2C switch with interrupt logic and reset
5. Block diagram
PCA9545A
SC0 SC1 SC2 SC3 SD0 SD1 SD2 SD3
VSS VDD RESET
SWITCH CONTROL LOGIC
POWER-ON RESET
SCL SDA
INPUT FILTER
I2C-BUS CONTROL
A0 A1
INT0 to INT3
INTERRUPT LOGIC
INT
002aab168
Fig 1. Block diagram of PCA9545A
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Product data sheet
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Philips Semiconductors
PCA9545A
4-channel I2C switch with interrupt logic and reset
6. Pinning information
6.1 Pinning
A0 A1 RESET INT0 SD0 SC0 INT1 SD1 SC1
1 2 3 4 5 6 7 8 9
20 VDD 19 SDA 18 SCL 17 INT 16 SC3 15 SD3 14 INT3 13 SC2 12 SD2 11 INT2
002aab165
A0 A1 RESET INT0 SD0 SC0 INT1 SD1 SC1
1 2 3 4 5 6 7 8 9
20 VDD 19 SDA 18 SCL 17 INT 16 SC3 15 SD3 14 INT3 13 SC2 12 SD2 11 INT2
002aab166
PCA9545AD
PCA9545APW
VSS 10
VSS 10
Fig 2. Pin configuration for SO20
20 A1 19 A0 terminal 1 index area
Fig 3. Pin configuration for TSSOP20
17 SDA 16 SCL 15 INT 14 SC3 13 SD3 12 INT3 11 SC2 SD2 10 6 7 8 VSS 9 INT2 18 VDD
RESET INT0 SD0 SC0 INT1
1 2 3 4 5
PCA9545ABS
SD1
SC1
002aab167
Transparent top view
Fig 4. Pin configuration for HVQFN20 (transparent top view)
6.2 Pin description
Table 3: Symbol A0 A1 RESET INT0 SD0 SC0 INT1 SD1
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Pin description Pin SO, TSSOP 1 2 3 4 5 6 7 8 HVQFN 19 20 1 2 3 4 5 6 address input 0 address input 1 active LOW reset input active LOW interrupt input 0 serial data 0 serial clock 0 active LOW interrupt input 1 serial data 1
(c) Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Description
Product data sheet
Rev. 03 -- 3 March 2005
4 of 27
Philips Semiconductors
PCA9545A
4-channel I2C switch with interrupt logic and reset
Pin description ...continued Pin SO, TSSOP HVQFN 7 8 [1] 9 10 11 12 13 14 15 16 17 18 serial clock 1 supply ground active LOW interrupt input 2 serial data 2 serial clock 2 active LOW interrupt input 3 serial data 3 serial clock 3 active LOW interrupt output serial clock line serial data line supply voltage 9 10 11 12 13 14 15 16 17 18 19 20 Description
Table 3: Symbol SC1 VSS INT2 SD2 SC2 INT3 SD3 SC3 INT SCL SDA VDD
[1]
HVQFN package die supply ground is connected to both the VSS pin and the exposed center pad. The VSS pin must be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board-level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board, and for proper heat conduction through the board thermal vias need to be incorporated in the PCB in the thermal pad region.
7. Functional description
Refer to Figure 1 "Block diagram of PCA9545A" on page 3.
7.1 Device address
Following a START condition, the bus master must output the address of the slave it is accessing. The address of the PCA9545A is shown in Figure 5. To conserve power, no internal pull-up resistors are incorporated on the hardware selectable address pins and they must be pulled HIGH or LOW.
1
1
1 fixed
0
0
A1
A0 R/W
hardware selectable
002aab169
Fig 5. Slave address
The last bit of the slave address defines the operation to be performed. When set to logic 1, a read is selected while a logic 0 selects a write operation.
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Product data sheet
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Philips Semiconductors
PCA9545A
4-channel I2C switch with interrupt logic and reset
7.2 Control register
Following the successful acknowledgement of the slave address, the bus master will send a byte to the PCA9545A, which will be stored in the control register. If multiple bytes are received by the PCA9545A, it will save the last byte received. This register can be written and read via the I2C-bus.
interrupt bits (read only) 7 6 5 4 INT INT INT INT 3 2 1 0 3 B3
channel selection bits (read/write) 2 B2 1 B1 0 B0 channel 0 channel 1 channel 2 channel 3 INT0 INT1 INT2 INT3
002aab170
Fig 6. Control register
7.2.1 Control register definition
One or several SCx/SDx downstream pair, or channel, is selected by the contents of the control register. This register is written after the PCA9545A has been addressed. The 4 LSBs of the control byte are used to determine which channel is to be selected. When a channel is selected, the channel will become active after a STOP condition has been placed on the I2C-bus. This ensures that all SCx/SDx lines will be in a HIGH state when the channel is made active, so that no false conditions are generated at the time of connection.
Table 4: INT3 X X X X 0 Control register: Write--channel selection; Read--channel status INT2 X X X X 0 INT1 X X X X 0 INT0 X X X X 0 B3 X X X 0 1 0 B2 X X 0 1 X 0 B1 X 0 1 X X 0 B0 0 1 X X X 0 Command channel 0 disabled channel 0 enabled channel 1 disabled channel 1 enabled channel 2 disabled channel 2 enabled channel 3 disabled channel 3 enabled no channel selected; power-up/reset default state
Remark: Several channels can be enabled at the same time. Example: B3 = 0, B2 = 1, B1 = 1, B0 = 0, means that channel 0 and channel 3 are disabled and channel 1 and channel 2 are enabled. Care should be taken not to exceed the maximum bus capacity.
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Product data sheet
Rev. 03 -- 3 March 2005
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Philips Semiconductors
PCA9545A
4-channel I2C switch with interrupt logic and reset
7.2.2 Interrupt handling
The PCA9545A provides 4 interrupt inputs, one for each channel, and one open-drain interrupt output. When an interrupt is generated by any device, it will be detected by the PCA9545A and the interrupt output will be driven LOW. The channel does not need to be active for detection of the interrupt. A bit is also set in the control register. Bit 4 through bit 7 of the control register corresponds to channel 0 through channel 3 of the PCA9545A, respectively. Therefore, if an interrupt is generated by any device connected to channel 1, the state of the interrupt inputs is loaded into the control register when a read is accomplished. Likewise, an interrupt on any device connected to channel 0 would cause bit 4 of the control register to be set on the read. The master can then address the PCA9545A and read the contents of the control register to determine which channel contains the device generating the interrupt. The master can then reconfigure the PCA9545A to select this channel, and locate the device generating the interrupt and clear it. It should be noted that more than one device can provide an interrupt on a channel, so it is up to the master to ensure that all devices on a channel are interrogated for an interrupt. The interrupt inputs may be used as general purpose inputs if the interrupt function is not required. If unused, interrupt input(s) must be connected to VDD through a pull-up resistor.
Table 5: INT3 X X X 0 1 Control register: Read--interrupt INT2 X X 0 1 X INT1 X 0 1 X X INT0 0 1 X X X B3 X X X X B2 X X X X B1 X X X X B0 X X X X Command no interrupt on channel 0 interrupt on channel 0 no interrupt on channel 1 interrupt on channel 1 no interrupt on channel 2 interrupt on channel 2 no interrupt on channel 3 interrupt on channel 3
Remark: Several interrupts can be active at the same time. Example: INT3 = 0, INT2 = 1, INT1 = 1, INT0 = 0, means that there is no interrupt on channel 0 and channel 3, and there is interrupt on channel 1 and channel 2.
7.3 RESET input
The RESET input is an active LOW signal which may be used to recover from a bus fault condition. By asserting this signal LOW for a minimum of tWL, the PCA9545A will reset its registers and I2C-bus state machine and will deselect all channels. The RESET input must be connected to VDD through a pull-up resistor.
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Product data sheet
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Philips Semiconductors
PCA9545A
4-channel I2C switch with interrupt logic and reset
7.4 Power-On Reset
When power is applied to VDD, an internal Power-On Reset (POR) holds the PCA9545A in a reset condition until VDD has reached VPOR. At this point, the reset condition is released and the PCA9545A registers and I2C-bus state machine are initialized to their default states--all zeroes--causing all the channels to be deselected. Thereafter, VDD must be lowered below 0.2 V to reset the device.
7.5 Voltage translation
The pass gate transistors of the PCA9545A are constructed such that the VDD voltage can be used to limit the maximum voltage that will be passed from one I2C-bus to another.
5.0 Vo(sw) (V) 4.0
(1)
002aaa964
3.0
(2) (3)
2.0
1.0 2.0
2.5
3.0
3.5
4.0
4.5
5.5 5.0 VDD (V)
(1) maximum (2) typical (3) minimum
Fig 7. Pass gate voltage versus supply voltage
Figure 7 shows the voltage characteristics of the pass gate transistors (note that the graph was generated using the data specified in Section 11 "Static characteristics" of this data sheet). In order for the PCA9545A to act as a voltage translator, the Vo(sw) voltage should be equal to, or lower than the lowest bus voltage. For example, if the main bus was running at 5 V, and the downstream buses were 3.3 V and 2.7 V, then Vo(sw) should be equal to or below 2.7 V to effectively clamp the downstream bus voltages. Looking at Figure 7, we see that Vo(sw)(max) will be at 2.7 V when the PCA9545A supply voltage is 3.5 V or lower, so the PCA9545A supply voltage could be set to 3.3 V. Pull-up resistors can then be used to bring the bus voltages to their appropriate levels (see Figure 14). More Information can be found in Application Note AN262: PCA954X family of I2C/SMBus multiplexers and switches.
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Product data sheet
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Philips Semiconductors
PCA9545A
4-channel I2C switch with interrupt logic and reset
8. Characteristics of the I2C-bus
The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy.
8.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as control signals (see Figure 8).
SDA
SCL data line stable; data valid change of data allowed
mba607
Fig 8. Bit transfer
8.2 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition (P) (see Figure 9).
SDA
SDA
SCL S START condition P STOP condition
SCL
mba608
Fig 9. Definition of START and STOP conditions
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Product data sheet
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Philips Semiconductors
PCA9545A
4-channel I2C switch with interrupt logic and reset
8.3 System configuration
A device generating a message is a `transmitter', a device receiving is the `receiver'. The device that controls the message is the `master' and the devices which are controlled by the master are the `slaves' (see Figure 10).
SDA SCL MASTER TRANSMITTER/ RECEIVER SLAVE RECEIVER SLAVE TRANSMITTER/ RECEIVER MASTER TRANSMITTER MASTER TRANSMITTER/ RECEIVER I2C MULTIPLEXER
SLAVE
002aaa966
Fig 10. System configuration
8.4 Acknowledge
The number of data bytes transferred between the START and the STOP conditions from transmitter to receiver is not limited. Each byte of eight bits is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter, whereas the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse; setup and hold times must be taken into account. A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a STOP condition.
data output by transmitter not acknowledge data output by receiver acknowledge SCL from master S START condition 1 2 8 clock pulse for acknowledgement
002aaa987
9
Fig 11. Acknowledgement on the I2C-bus
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Philips Semiconductors
PCA9545A
4-channel I2C switch with interrupt logic and reset
8.5 Bus transactions
Data is transmitted to the PCA9545A control register using the Write mode as shown in Figure 12.
slave address SDA S 1 1 1 0 0 A1 A0 0 A X X X
control register X B3 B2 B1 B0 A P
START condition
R/W
acknowledge from slave
acknowledge from slave STOP condition
002aab172
Fig 12. Write control register
Data is read from PCA9545A using the Read mode as shown in Figure 13.
slave address SDA S 1 1 1 0 0 A1 A0 1 A
control register INT3 INT2 INT1 INT0 B3 B2 B1
last byte
B0
NA
P
START condition
R/W
acknowledge from slave
no acknowledge from master STOP condition
002aab173
Fig 13. Read control register
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Product data sheet
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Philips Semiconductors
PCA9545A
4-channel I2C switch with interrupt logic and reset
9. Application design-in information
VDD = 2.7 V to 5.5 V VDD = 3.3 V V = 2.7 V to 5.5 V see note (1) SDA SCL SDA SCL INT RESET see note (1) I2C/SMBus master SD1 SC1 INT1 V = 2.7 V to 5.5 V channel 1 SD0 SC0 INT0 V = 2.7 V to 5.5 V channel 0
PCA9545A
SD2 SC2 INT2
see note (1) channel 2
V = 2.7 V to 5.5 V see note (1) A1 A0 VSS SD3 SC3 INT3
002aab171
channel 3
(1) If the device generating the interrupt has an open-drain output structure or can be 3-stated, a pull-up resistor is required. If the device generating the interrupt has a totem-pole output structure and cannot be 3-stated, a pull-up resistor is not required. The interrupt inputs should not be left floating.
Fig 14. Typical application
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Product data sheet
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PCA9545A
4-channel I2C switch with interrupt logic and reset
10. Limiting values
Table 6: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to VSS (ground = 0 V). [1] Symbol VDD VI II IO IDD ISS Ptot Tstg Tamb
[1]
Parameter supply voltage input voltage input current output current supply current ground supply current total power dissipation storage temperature operating ambient temperature
Conditions
Min -0.5 -0.5 -60 -40
Max +7.0 +7.0 20 25 100 100 400 +150 +85
Unit V V mA mA mA mA mW C C
The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 C.
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PCA9545A
4-channel I2C switch with interrupt logic and reset
11. Static characteristics
Table 7: Static characteristics VDD = 2.3 V to 3.6 V; VSS = 0 V; Tamb = -40 C to +85 C; unless otherwise specified. See Table 8 on page 15 for VDD = 4.5 V to 5.5 V. [1] Symbol Supply VDD IDD Istb VPOR VIL VIH IOL IL Ci VIL VIH ILI Ci Pass gate Ron on-state resistance VDD = 3.67 V; VO = 0.4 V; IO = 15 mA VDD = 2.3 V to 2.7 V; VO = 0.4 V; IO = 10 mA Vo(sw) switch output voltage Vi(sw) = VDD = 3.3 V; Io(sw) = -100 A Vi(sw) = VDD = 3.0 V to 3.6 V; Io(sw) = -100 A Vi(sw) = VDD = 2.5 V; Io(sw) = -100 A Vi(sw) = VDD = 2.3 V to 2.7 V; Io(sw) = -100 A IL Cio INT output IOL IOH
[1] [2]
Parameter supply voltage supply current standby current power-on reset voltage LOW-level input voltage HIGH-level input voltage LOW-level output current leakage current input capacitance LOW-level input voltage HIGH-level input voltage input leakage current input capacitance
Conditions
Min 2.3
Typ 10 0.1 1.6 7 10 10 1.6 11 16 1.9 1.5 3 -
Max 3.6 30 1 2.1 0.3VDD 6 +1 13 0.3VDD VDD + 0.5 +1 3 30 55 2.8 2.0 +1 5 +10
Unit V A A V V V mA mA A pF V V A pF V V V V A pF mA A
operating mode; VDD = 3.6 V; no load; VI = VDD or VSS; fSCL = 100 kHz standby mode; VDD = 3.6 V; no load; VI = VDD or VSS no load; VI = VDD or VSS
[2]
-0.5 0.7VDD
Input SCL; input/output SDA
VOL = 0.4 V VOL = 0.6 V VI = VDD or VSS VI = VSS
3 6 -1 -0.5 0.7VDD
Select inputs A0, A1, INT0 to INT3, RESET
pin at VDD or VSS VI = VSS
-1 5 7 1.6 1.1 -1 3 -
leakage current input/output capacitance LOW-level output current HIGH-level output current
VI = VDD or VSS VI = VSS VOL = 0.4 V
For operation between published voltage ranges, refer to the worst-case parameter in both ranges. VDD must be lowered to 0.2 V in order to reset part.
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PCA9545A
4-channel I2C switch with interrupt logic and reset
Table 8: Static characteristics VDD = 4.5 V to 5.5 V; VSS = 0 V; Tamb = -40 C to +85 C; unless otherwise specified. See Table 7 on page 14 for VDD = 2.3 V to 3.6 V. [1] Symbol Supply VDD IDD supply voltage supply current operating mode; VDD = 5.5 V; no load; VI = VDD or VSS; fSCL = 100 kHz standby mode; VDD = 5.5 V; no load; VI = VDD or VSS no load; VI = VDD or VSS
[2]
Parameter
Conditions
Min 4.5 -
Typ 25
Max 5.5 100
Unit V A
Istb VPOR VIL VIH IOL IL Ci VIL VIH ILI Ci Pass gate Ron Vo(sw)
standby current power-on reset voltage LOW-level input voltage HIGH-level input voltage LOW-level output current leakage current input capacitance LOW-level input voltage HIGH-level input voltage input leakage current input capacitance on-state resistance switch output voltage
-0.5 0.7VDD
0.3 1.7 10 2 9 3.6 3 -
1 2.1 0.3VDD 6 1 13 0.3VDD VDD + 0.5 +1 5 24 4.5 +1 5 +10
A V V V mA mA A pF V V A pF V V A pF mA A
Input SCL; input/output SDA
VOL = 0.4 V VOL = 0.6 V VI = VSS VI = VSS
3 6 -1 -0.5 0.7VDD
Select inputs A0, A1, INT0 to INT3, RESET
VI = VDD or VSS VI = VSS VDD = 4.5 V to 5.5 V; VO = 0.4 V; IO = 15 mA Vi(sw) = VDD = 5.0 V; Io(sw) = -100 A Vi(sw) = VDD = 4.5 V to 5.5 V; Io(sw) = -100 A
-1 4 2.6 -1 3 -
IL Cio INT output IOL IOH
[1] [2]
leakage current input/output capacitance LOW-level output current HIGH-level output current
VI = VDD or VSS VI = VSS VOL = 0.4 V
For operation between published voltage ranges, refer to the worst-case parameter in both ranges. VDD must be lowered to 0.2 V in order to reset part.
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Philips Semiconductors
PCA9545A
4-channel I2C switch with interrupt logic and reset
12. Dynamic characteristics
Table 9: Symbol Dynamic characteristics Parameter Conditions Standard-mode I2C-bus Min tPD fSCL tBUF tHD;STA propagation delay from SDA to SDn, or SCL to SCn SCL clock frequency bus free time between a STOP and START condition hold time (repeated) START condition. After this period, the first clock pulse is generated. LOW period of the SCL clock HIGH period of the SCL clock setup time for a repeated START condition setup time for STOP condition data hold time data setup time rise time of both SDA and SCL signals fall time of both SDA and SCL signals capacitive load for each bus line pulse width of spikes which must be suppressed by the input filter data valid time data valid Acknowledge HIGH-to-LOW LOW-to-HIGH tVD;ACK INT tv(INTnN-INTN) valid time from INTn to INT signal td(INTnN-INTN) delay time from INTn to INT inactive tw(rej)L tw(rej)H RESET tw(rst)L trst tREC;STA
[1] [2] [3] [4]
[4] [4]
Fast-mode I2C-bus Min 0 1.3 0.6 Max 0.3 [1] 400 -
Unit
Max 0.3 [1] 100 -
0 4.7 4.0
ns kHz s s
tLOW tHIGH tSU;STA tSU;STO tHD;DAT tSU;DAT tr tf Cb tSP tVD;DAT
4.7 4.0 4.7 4.0 0 [2] 250 INTn inputs INTn inputs 1 0.5 4 500 0
3.45 1000 300 400 50 1 0.6 1 4 2 -
1.3 0.6 0.6 0.6 0 [2] 100 20 + 0.1Cb 20 + 0.1Cb 100 1 0.5 4 500 0
[3] [3]
0.9 300 300 400 50 1 0.6 1 4 2 -
s s s s s ns ns s s ns s s s s s s s ns ns ns
LOW-level rejection time HIGH-level rejection time LOW-level reset time reset time (SDA clear) recovery time to START condition
Pass gate propagation delay is calculated from the 20 typical Ron and the 15 pF load capacitance. A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIH(min) of the SCL signal) in order to bridge the undefined region of the falling edge of SCL. Cb = total capacitance of one bus line in pF. Measurements taken with 1 k pull-up resistor and 50 pF load.
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Product data sheet
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Philips Semiconductors
PCA9545A
4-channel I2C switch with interrupt logic and reset
SDA tBUF tLOW SCL tr tf tHD;STA tSP
tHD;STA P S tHD;DAT tHIGH tSU;DAT Sr
tSU;STA
tSU;STO P
002aaa986
Fig 15. Definition of timing on the I2C-bus
START SCL
ACK or read cycle
SDA 30 % trst
RESET
50 % tREC;STA
50 % tw(rst)L
50 %
trst LEDx 50 % LED off
002aab174
Fig 16. Definition of RESET timing
protocol
START condition (S) tSU;STA
bit 7 MSB (A7) tLOW tHIGH
bit 6 (A6)
bit 0 (R/W)
acknowledge (A)
STOP condition (P)
1/f
SCL
SCL tBUF tr tf
SDA
tHD;STA
tSU;DAT
tHD;DAT
tVD;DAT
tVD;ACK
tSU;STO
002aab175
Rise and fall times, refer to VIL and VIH.
Fig 17. I2C-bus timing diagram
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Product data sheet
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Philips Semiconductors
PCA9545A
4-channel I2C switch with interrupt logic and reset
SCL
2
1
0
A
P
70 % 30 %
SDA
INPUT tv(INTnN-INTN) INT
002aab176
50 % td(INTnN-INTN)
Fig 18. Expanded view of read input port register
13. Test information
VDD VDD PULSE GENERATOR VI D.U.T.
RT CL 50 pF RL 500
VO
002aab177
Definitions test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
Fig 19. Test circuitry for switching times
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Product data sheet
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Philips Semiconductors
PCA9545A
4-channel I2C switch with interrupt logic and reset
14. Package outline
SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1
D
E
A X
c y HE vMA
Z 20 11
Q A2 A1 pin 1 index Lp L 1 e bp 10 wM detail X (A 3) A
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 2.65 0.1 A1 0.3 0.1 A2 2.45 2.25 A3 0.25 0.01 bp 0.49 0.36 c 0.32 0.23 D (1) 13.0 12.6 0.51 0.49 E (1) 7.6 7.4 0.30 0.29 e 1.27 0.05 HE 10.65 10.00 L 1.4 Lp 1.1 0.4 Q 1.1 1.0 0.043 0.039 v 0.25 0.01 w 0.25 0.01 y 0.1 Z
(1)
0.9 0.4
0.012 0.096 0.004 0.089
0.019 0.013 0.014 0.009
0.419 0.043 0.055 0.394 0.016
0.035 0.004 0.016
8 o 0
o
Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE VERSION SOT163-1 REFERENCES IEC 075E04 JEDEC MS-013 JEITA EUROPEAN PROJECTION
ISSUE DATE 99-12-27 03-02-19
Fig 20. Package outline SOT163-1 (SO20)
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Product data sheet
Rev. 03 -- 3 March 2005
19 of 27
Philips Semiconductors
PCA9545A
4-channel I2C switch with interrupt logic and reset
TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm
SOT360-1
D
E
A
X
c y HE vMA
Z
20
11
Q A2 pin 1 index A1 (A 3) A
Lp L
1
e bp
10
wM detail X
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 6.6 6.4 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.5 0.2 8 o 0
o
Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT360-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19
Fig 21. Package outline SOT360-1 (TSSOP20)
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Product data sheet
Rev. 03 -- 3 March 2005
20 of 27
Philips Semiconductors
PCA9545A
4-channel I2C switch with interrupt logic and reset
HVQFN20: plastic thermal enhanced very thin quad flat package; no leads; 20 terminals; body 5 x 5 x 0.85 mm
SOT662-1
D
B
A
terminal 1 index area E
A A1 c
detail X
e1 e 6 L 11 b 10 vMCAB wMC y1 C
C y
5
e Eh e2
1
15
terminal 1 index area
20 Dh 0
16
X
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. 1 A1 0.05 0.00 b 0.38 0.23 c 0.2 D(1) 5.1 4.9 Dh 3.25 2.95 E(1) 5.1 4.9 Eh 3.25 2.95 e 0.65 e1 2.6 e2 2.6 L 0.75 0.50 v 0.1 w 0.05 y 0.05 y1 0.1
Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE VERSION SOT662-1 REFERENCES IEC --JEDEC MO-220 JEITA --EUROPEAN PROJECTION ISSUE DATE 01-08-08 02-10-22
Fig 22. Package outline SOT662-1 (HVQFN20)
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Product data sheet
Rev. 03 -- 3 March 2005
21 of 27
Philips Semiconductors
PCA9545A
4-channel I2C switch with interrupt logic and reset
15. Soldering
15.1 Introduction to soldering surface mount packages
This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit Packages (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended.
15.2 Reflow soldering
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 seconds and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 C to 270 C depending on solder paste material. The top-surface temperature of the packages should preferably be kept:
* below 225 C (SnPb process) or below 245 C (Pb-free process)
- for all BGA, HTSSON..T and SSOP..T packages - for packages with a thickness 2.5 mm - for packages with a thickness < 2.5 mm and a volume 350 mm3 so called thick/large packages.
* below 240 C (SnPb process) or below 260 C (Pb-free process) for packages with a
thickness < 2.5 mm and a volume < 350 mm3 so called small/thin packages. Moisture sensitivity precautions, as indicated on packing, must be respected at all times.
15.3 Wave soldering
Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results:
* Use a double-wave soldering method comprising a turbulent wave with high upward
pressure followed by a smooth laminar wave.
* For packages with leads on two sides and a pitch (e):
- larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board;
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Product data sheet
Rev. 03 -- 3 March 2005
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Philips Semiconductors
PCA9545A
4-channel I2C switch with interrupt logic and reset
- smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end.
* For packages with leads on four sides, the footprint must be placed at a 45 angle to
the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 C or 265 C, depending on solder material applied, SnPb or Pb-free respectively. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications.
15.4 Manual soldering
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 seconds to 5 seconds between 270 C and 320 C.
15.5 Package related soldering information
Table 10: Package [1] BGA, HTSSON..T [3], LBGA, LFBGA, SQFP, SSOP..T [3], TFBGA, USON, VFBGA DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP, HSQFP, HSSON, HTQFP, HTSSOP, HVQFN, HVSON, SMS PLCC [5], SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO, VSSOP CWQCCN..L [8], PMFP [9], WQCCN..L [8]
[1] [2]
Suitability of surface mount IC packages for wave and reflow soldering methods Soldering method Wave not suitable not suitable [4] Reflow [2] suitable suitable
suitable not not recommended [5] [6] recommended [7]
suitable suitable suitable not suitable
not suitable
For more detailed information on the BGA packages refer to the (LF)BGA Application Note (AN01026); order a copy from your Philips Semiconductors sales office. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods. These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature exceeding 217 C 10 C measured in the atmosphere of the reflow oven. The package body peak temperature must be kept as low as possible.
[3]
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Product data sheet
Rev. 03 -- 3 March 2005
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Philips Semiconductors
PCA9545A
4-channel I2C switch with interrupt logic and reset
[4]
These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. Wave soldering is suitable for SSOP, TSSOP, VSO and VSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered pre-mounted on flex foil. However, the image sensor package can be mounted by the client on a flex foil by using a hot bar soldering process. The appropriate soldering profile can be provided on request. Hot bar soldering or manual soldering is suitable for PMFP packages.
[5] [6] [7] [8]
[9]
16. Abbreviations
Table 11: Acronym CDM ESD HBM IC LSB MM MSB PCB POR Abbreviations Description Charged Device Model Electro Static Discharge Human Body Model Integrated Circuit Least Significant Bit Machine Model Most Significant Bit Printed-Circuit Board Power-On Reset
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Product data sheet
Rev. 03 -- 3 March 2005
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Philips Semiconductors
PCA9545A
4-channel I2C switch with interrupt logic and reset
17. Revision history
Table 12: Revision history Release date 20050303 Data sheet status Product data sheet Change notice Doc. number 9397 750 14311 Supersedes PCA9545A_2 Document ID PCA9545A_3 Modifications:
* * * * *
The format of this data sheet has been redesigned to comply with the new presentation and information standard of Philips Semiconductors. Section 2 "Features" on page 1: 9th bullet: changed "RDSON" to "Ron" Figure 4 "Pin configuration for HVQFN20 (transparent top view)" on page 4: added pin 1 indicator notch and center pad. Table 3 "Pin description" on page 4: added Table note 1 and its reference at HVQFN pin 8. Section 7.5 "Voltage translation" on page 8: - Figure 7: title changed from "Vpass voltage versus VDD" to "Pass gate voltage versus supply voltage"; within graphic changed "Vpass (V)" to "Vo(sw) (V)" - 2nd paragraph: changed "Vpass" to "Vo(sw)"; changed "Vpass(max)" to "Vo(sw)(max)"
* *
Table 6 "Limiting values" on page 13: remove (old) table note [1], as it is now covered by Section 19 "Definitions" on page 26. Table 7 "Static characteristics" on page 14: - changed symbol "RON" to "Ron"; changed parameter from "switch resistance" to "on-state resistance" - changed symbol "Vpass" to "Vo(sw)" - under Conditions column for Vo(sw): changed "Vswin" to "Vi(sw)"; changed "Iswout" to "Io(sw)" - Added (new) Table note 1.
*
Table 8 "Static characteristics" on page 15: - changed symbol "RON" to "Ron"; changed parameter from "switch resistance" to "on-state resistance" - changed symbol "Vpass" to "Vo(sw)" - under Conditions column for Vo(sw): changed "Vswin" to "Vi(sw)"; changed "Iswout" to "Io(sw)"
*
Table 9 "Dynamic characteristics" on page 16: - changed symbol "tR" to "tr"; changed symbol "tF" to "tf" (also in Figure 15 on page 17) - changed symbols "tVD;DATL" and "tVD;DATH" to "tVD;DAT" and added Conditions indicating HIGH-to-LOW and LOW-to-HIGH transitions - changed symbol "tIV" to "tv(INTnN-INTN)" (also in Figure 18 on page 18) - changed symbol "tIR" to "td(INTn-INTN)" (also in Figure 18 on page 18) - changed symbol "Lpwr" to "tw(rej)L" - changed symbol "Hpwr" to "tw(rej)H" - changed symbol "tWL(rst)" to "tw(rst)L" (also in Figure 16 on page 17)
*
PCA9545A_2 PCA9545A_1
Added Section 16 "Abbreviations". Objective data sheet Objective data sheet 9397 750 13989 9397 750 13309 PCA9545A_1 -
20040929 20040728
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Product data sheet
Rev. 03 -- 3 March 2005
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Philips Semiconductors
PCA9545A
4-channel I2C switch with interrupt logic and reset
18. Data sheet status
Level I II Data sheet status [1] Objective data Preliminary data Product status [2] [3] Development Qualification Definition This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN).
III
Product data
Production
[1] [2] [3]
Please consult the most recently issued data sheet before initiating or completing a design. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
19. Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
20. Disclaimers
Life support -- These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
21. Contact information
For additional information, please visit: http://www.semiconductors.philips.com For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com
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Product data sheet
Rev. 03 -- 3 March 2005
26 of 27
Philips Semiconductors
PCA9545A
4-channel I2C switch with interrupt logic and reset
22. Contents
1 2 3 4 5 6 6.1 6.2 7 7.1 7.2 7.2.1 7.2.2 7.3 7.4 7.5 8 8.1 8.2 8.3 8.4 8.5 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 15.5 16 17 18 19 20 21 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 5 Device address . . . . . . . . . . . . . . . . . . . . . . . . . 5 Control register . . . . . . . . . . . . . . . . . . . . . . . . . 6 Control register definition . . . . . . . . . . . . . . . . . 6 Interrupt handling . . . . . . . . . . . . . . . . . . . . . . . 7 RESET input . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . 8 Voltage translation . . . . . . . . . . . . . . . . . . . . . . 8 Characteristics of the I2C-bus. . . . . . . . . . . . . . 9 Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 START and STOP conditions . . . . . . . . . . . . . . 9 System configuration . . . . . . . . . . . . . . . . . . . 10 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 10 Bus transactions . . . . . . . . . . . . . . . . . . . . . . . 11 Application design-in information . . . . . . . . . 12 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 13 Static characteristics. . . . . . . . . . . . . . . . . . . . 14 Dynamic characteristics . . . . . . . . . . . . . . . . . 16 Test information . . . . . . . . . . . . . . . . . . . . . . . . 18 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 19 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Introduction to soldering surface mount packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 22 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 22 Manual soldering . . . . . . . . . . . . . . . . . . . . . . 23 Package related soldering information . . . . . . 23 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 25 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 26 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Contact information . . . . . . . . . . . . . . . . . . . . 26
(c) Koninklijke Philips Electronics N.V. 2005
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 3 March 2005 Document number: 9397 750 14311
Published in The Netherlands

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