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INDEX PRELIMINARY
MX8325-1
MOTHERBOARD CLOCK GENERATOR
FEATURES
* Clock generator for 486, PentinumTM , and Cryix 6x86 based systems * Support ISA-, VESA-, and PCI- based designs * Support independent PCI bus clock and 1/2 CPU clock, and 48 MHz USB clock * Support 24 MHz clock * Built-in on-chip one 1 to 3, two 1 to 2 buffers, with minimum pin-to-pin output skew below 500ps * Under 0.1% CPU clock period change while switching frequency * Skew-controlled 1/2 CPU and 1X CPU clocks to winthin 500ps * On-chip loop filter components * Smooth and glitch-free switching for programmable clock generators * 28-PIN(300 mil)SOP
.
FUNCTIONAL DESCRIPTON
The MX8325-1 is a CMOS motherboard clock generator used in portable or desktop computers. The chip includes an oscillator circuitry and three PLLs to provide 14.318 MHz, CPUCLK, 1/2 CPUCLK, PCI bus CLK, and 24 MHz clocks. This chip is built with low skew clock drivers that provide the needed buffering for PCI applications. The desired CPUCLK is selected by S0, S1 and S2. This chip provides selectable 75 MHz, 66.6 MHz, 60 MHz, 55 MHz, 33.3 MHz, 50 MHz, 40 MHz, 33.3 MHz, and 25 MHz CPUCLK. It is suitable for 80486DX, 80486DX2, 80486DX4, 80486S series, Pentium-based and Cyrix 6x86 series designs. Independent PCI bus clock and 1/2 CPUCLK make this chip mostly suitable for asychronous PCI or synchronous PCI design.
GENERAL DESCRIPTION
There are three PLLs in the MX8325-1 to support smooth transition and glitch-free CPU clock, 24 MHz and PCI bus clock. It can be suited for synchronous PCI design (1/2 CPU clock) and asynchronous PCI design (PCICLK clock). In addition, the MX8325-1 supports one 1-to-3 and two 1-to-2 buffers for motherboard appilications. The output pin-to-pin clock skews of the buffers are controlled below 500 ps. The only external components are a 14.318 MHz crystal and decoupling capacitors. The frequency select pins (S2, S1 and S0) determine the CPU output frequency, which is shown in next page. The CPU clock offers the feature of smooth and glitchfree frequency transition when the frequency modes are changed. The chip meets the 486 and PentiumTM specifications of subseqent clock period changed under 0.1%. The simultaneous 1X and 1/2 CPU clocks offer controlled skew within 500ps (TPY).
PIN CONFIGURATIONS
28 SOP
14.318MHZ XO XI 33/48 SELECT 24MHZ 33/48MHZ AVDD GND 1/2 CPUCLK BIN0 DVDD BOUT00 BOUT01 BOUT02 1 2 3 4 5 28 27 26 25 24 S2 S1 S0 MS0 CPUCLK BIN1 DVDD AGND BOUT10 BOUT11 BIN2 GND BOUT20 BOUT21
MX8325-1
6 7 8 9 10 11 12 13 14
23 22 21 20 19 18 17 16 15
P/N: PM0385
1
REV. 2.0, AGU. 23, 1996
INDEX
MX8325-1
BLOCK DIAGRAM
XO
OSC
XI
14.318MHZ
S0 S1 S2 MS0
PLL0 1/2
CPUCLK
1/2 CPUCLK
PLL1
33/48 SELECT
33/48MHZ
PLL2
24MHZ
BOUT00
BIN0 BIN1 BIN2
BOUT01 BOUT02 BOUT10 BOUT11 BOUT20 BOUT21
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INDEX
MX8325-1
PIN DESCRIPTION (For MX8355-03)
SYMBOL 14.318MHz XO XI 33/48 SELECT 24 MHz 33/48 MHZ AVDD GND 1/2 CPUCLK BIN0 DVDD BOUT00 BOUT01 BOUT02 BOUT21 BOUT20 DGND BIN2 BOUT11 BOUT10 AGND DVDD BIN1 CPUCLK MS0 S0 S1 S2 PIN TYPE O I I I O O --O I -O O O O O -I O O --I O I I I I PIN NUMBER 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 DESCRIPTION 14.318 MHz output (8mA) X'tal output. No connection when clock input X'tal input or reference clock input 33 MHZ/48 MHZ select pin internal pull-high. 24 MHz clock output (8mA) 33 or 48 MHZ output depends on pin4. Analog power supply Ground 1/2 CPU clock output (12mA) Buffer (0) input, internal pull high Digital power supply Buffer (0) output (0) Buffer (0) output (1) Buffer (0) output (2) Buffer (2) output (1) Buffer (2) output (0) Digital ground Buffer (2) input, internal pull high Buffer (1) output (1) Buffer (1) output (0) Analog ground Digital power supply Buffer (1) input, internal pull high CPU clock output (12mA) CPU clock output mode select pin, internal pull high CPU clock select pin (0), internal pull high (20mA) CPU clock select pin (1), internal pull high (20mA) CPU clock select pin (2), internal pull high (20mA)
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INDEX
MX8325-1
FREQUENCY TABLE
MS0=1, 33/48 SELECT=H S(2:0) 0 1 2 3 4 5 6 7 CPU 66.6 75.0 60.0 55.0 50.0 40.0 33.3 25.0 1/2 CPUCLK 33.3 37.5 30.0 27.5 25 20.0 16.65 12.5 33/48 MHZ 33.3 33.3 33.3 33.3 33.3 33.3 33.3 25.0 MS0=1, 33/48 SELECT=L CPU 66.6 75.0 60.0 55.0 50.0 40.0 33.3 25.0 1/2 CPUCLK 33.3 37.5 30.0 27.5 25 20.0 16.65 12.5 33/48 MHZ 48 48 48 48 48 48 48 48
"1" means High. "0" means Low. The mode (S (2:0)=(0, 0, 1) ) is not supported.
AC/DC CHARACTERISTICS
DC CHARACTERISTICS TA = 0oC to 70oC, VCC = 5V 10%
SYMBOL DVDD, AVDD IDD PARAMETER Supply Voltage Supply Current MIN. 4.5 TYP. 5 35 MAX. 5.5 UNIT V mA No load, running at 50 MHz IIH VOL VOH VIL VIH RPU Input High Current Output Low Voltage Output High Voltage Input LOW Voltage Input High Voltage Pull-up Resistor 2.0 100K 2.4 0.8 5 0.4 uA V V V V Ohms IOL=20mA, VDD=5V IOH=-40mA, VDD=5V for buffers only for buffers only CONDITIONS
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INDEX
MX8325-1
CAPACITANCE TA = 25oC, f = 1.0 MHz (Sampled only)
SYMBOL CIN COUT PARAMETER Input Capacitance Output Capacitance MIN. TYP. 8 8 MAX. UNIT pF pF CONDITIONS
AC CHARACTERISTICS TA = 0oC to 70oC, VCC = 5V 10%
SYMBOL Tr Tf Tsk Dt Tp PARAMETER Output Rise Time 0.8V to 2.0V Output Fall Time 2.0V to 0.8V Clock skew CPU and 1/2 CPU Output Duty Cycle Propagation Delay Bin to Bout 40/60 2 0.5 48/52 3 MIN. TYP. MAX. 1.5 1.5 1 60/40 5 UNIT ns ns ns % ns CONDITIONS 25 pF load 25 pF load 25 pF load 25 pF load 15 pF load Measured at 1.4V Tjis Tskew Fref CPUCLK, 1/2 CPUCLK Out Sigma Buffer Out skew 250 500 500 ps ps 15 pF load Measured at 1.4V Reference Clock Frequency 14.318 14.318 14.318 MHz
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INDEX
MX8325-1
WAVEFORMS
CPUCLK
Tr
Tf
1/2 CPUCLK Tsk
buffer
Vout1
Vin
buffer
Vout2
Vin
Vout1 Tp Vout2 Tskew
ORDERING INFORMATION PLASTIC PACKAGE
PART NO. MX8325-1MC PACKAGE 28-PIN SOP (5V Version)
6
INDEX
MX8325-1
RECOMMENDED EXTERNAL CIRCUIT
VCC AVDD 10 ohm C 10uF
VCC 1.5uH L
DVDD C 10uF
1
28 27 26 25 24
JUMPER
C
10P
2
14.318M 10P
3 4 5
C
MX8325-1
6
23 22 21 20 19 18 17 16 15
AVDD
C
7
0.1uF
8 9 10
DVDD C 0.1uF R 33 ohm R 33 ohm
DVDD C 0.47uF R 33 ohm R 33 ohm R 33 ohm
11 12 13 14
R 33 ohm R 33 ohm
ANALOG GROUND DIGITAL GROUND
Note : 1. Pin26, pin27, pin28, and pin25 (S0, S1, S2, MS0) are with internal pull high resistor. 2. For 5V and 3.3V mixed application (MX8325-1). If DVDD(pin11 and pin22) is connected to 3.3V power source, and AVDD(pin7) is connected to 5V power source, then all outputs are 3.3V level.
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INDEX
MX8325-1
LAYOUT GUIDE
1 2 3 4 5 TO VCC 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
:GROUND PLANE :BLANK
:THROUGH HOLE CONNECTED TO GROUND PLANE :THROUGH HOLE
This is the recommended layout guide for the MX8325-1 to maximize the clock performance. The most important feature is the isolated ground plane of the MX8325-1. The reason it needs an isolated ground plane is explained in the following paragraph. The power supply fluctuation induced from the ripple of switching power supply, and the switching between the heavy circuit activity and little circuit activity on the board will couple into the clock generators and appear as jitters on the clock outputs. To alleviate jitters, special care should be taken on the power source of clock generator to prevent the power source from interacting with the system noise.
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INDEX
MX8325-1
28-PIN PLASTIC SOP (300 mil)
ITEM A B C D E F G H I J K L
NOTE:
MILLIMETERS 17.83 0.66 1.27 0.41 0.20 2.54 2.34 10.31 7.59 1.35 0.25 0.76
INCHES 0.702 0.026 0.050 0.061 0.008 0.1 0.092 0.406 0.299 0.053 0.010 0.030
28
15
1 A
14
H I G F K J
Each lead centerline is located within .25 mm[.01 inch] of its true position [TP] at maximum material condition.
D
C
B
E L
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