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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS85354
DUAL 2:1/1:2 DIFFERENTIAL -TO-LVPECL/ECL MULTIPLEXER
FEATURES
* Dual 2:1/1:2 MUX * 3 LVPECL outputs * 3 differential clock inputs * CLKx pair can accept the following differential input levels: LVPECL, LVDS, CML * Maximum output frequency: 3GHz * Part-to-part skew: 85ps (typical) * Additive jitter, RMS: 0.03ps (typical) * Propagation delay: 330ps (typical) * LVPECL mode operating voltage supply range: VCC = 2.375V to 3.465V, VEE = 0V * ECL mode operating voltage supply range: VCC = 0V, VEE = -3.465V to -2.375V * -40C to 85C ambient operating temperature
GENERAL DESCRIPTION
The ICS85354 is a 2:1/1:2 Multiplexer and a member of the HiPerClockSTM family of high perforHiPerClockSTM mance clock solutions from ICS. The 2:1 Multiplexer allows one of 2 inputs to be selected onto one output pin and the 1:2 MUX switches one input to one of two outputs. This device may be useful for multiplexing multirate Ethernet Phys which have 100Mbit and 1000Mbit transmit/ receive pairs onto an optical SFP module which has a single trasmit/receive pair. Please refer to the Application Block diagram on page 2 of the data sheet.
ICS
The ICS85354 is optimized for applications requiring very high performance and has a maximum operating frequency in excess of 2GHz. The device is packaged in a small, 3mm x 3mm VFQFN package, making it ideal for use on space-constrained boards.
BLOCK DIAGRAM
CLK_SELA
PIN ASSIGNMENT
CLK_SELA nQA VCC QA
CLKA0 nCLKA0 CLKA1 nCLKA1
0
QA nQA
QB0 1 nQB0 2 QB1 3 nQB1 4
16 15 14 13 12 11 10 9 5
CLKB
CLKA0 nCLKA0 CLKA1 nCLKA1
1
6
nCLKB
7
CLK_SELB
8
VEE
CLKB nCLKB
QB0 nQB0
ICS85354
CLK_SELB QB1 nQB1
16-Lead VFQFN 3mm x 3mm x 0.95 package body K Package Top View
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
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REV. B JUNE 8, 2004
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS85354
DUAL 2:1/1:2 DIFFERENTIAL -TO-LVPECL/ECL MULTIPLEXER
A TYPICAL APPLICATION FOR THE ICS85354
Used to connect a multi-rate PHY with the Tx/Rx pins of an SFP Module. Problem Addressed: How to mape the 2 Tx/Rx pairs of the multi-rate PHY to the single Tx/Rx pair on the SFP Module.
MULTI-RATE PHY
100BaseFX Tx Rx Tx Rx
SFP MODULE
1000BaseX
?
Rx
Tx
MODE 1, 100BASEX CONNECTED TO SFP
All lines are differential pairs, but drawn as single-ended to simplify the drawing. Bold red lines signal path. are active connections highlighting the
CLK_SELA = 0
MULTI-RATE PHY
Tx 100BaseFX Rx
CLKA0
SFP MODULE
0
QA
Rx
CLKA1
1
CLKB
QB0
Tx
QB1 CLK_SELB = 0
Tx 1000BaseX Rx
ICS85354
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REV. B JUNE 8, 2004
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS85354
DUAL 2:1/1:2 DIFFERENTIAL -TO-LVPECL/ECL MULTIPLEXER
Bold red lines the signal path. are active connections highlighting
MODE 2, 1000BASEX CONNECTED TO SFP
All lines are differential pairs, but drawn as single-ended to simplify the drawing.
CLK_SELA = 1
MULTI-RATE PHY
Tx 100BaseFX Rx
CLKA0
SFP MODULE
0
QA
Rx
CLKA1
1
QB0
CLKB
Tx
QB1 CLK_SELB = 1
Tx 1000BaseX Rx
ICS85354
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REV. B JUNE 8, 2004
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS85354
DUAL 2:1/1:2 DIFFERENTIAL -TO-LVPECL/ECL MULTIPLEXER
Type Description Differential output pair. LVPECL/ECL interface levels. Differential output pair. LVPECL/ECL interface levels. Pulldown Non-inver ting LVPECL/ECL differential clock input. Pullup/ Inver ting differential LVPECL clock input. VCC/2 default when left floating. Pulldown Clock select pin for QBx outputs. When HIGH, selects QB1, nQB1 Pulldown outputs. When LOW, selects QB0, nQB0 outputs. LVCMOS/LVTTL interface levels. Negative supply pin. Pullup/ Inver ting differential LVPECL clock input. VCC/2 default when left floating. Pulldown Pulldown Non-inver ting LVPECL differential clock input. Pullup/ Inver ting differential LVPECL clock input. VCC/2 default when left floating. Pulldown Pulldown Non-inver ting LVPECL differential clock input.
TABLE 1. PIN DESCRIPTIONS
Number 1, 2 3, 4 5 6 7 8 9 10 11 12 13 Name QB0, nQB0 QB1, nQB1 CLKB nCLKB CLK_SELB VEE nCLKA1 CLKA1 nCLKA0 CLKA0 VCC Output Output Input Input Input Power Input Input Input Input Power
Positive supply pin. Clock select pin for QA outputs. When HIGH, selects QA output. 14 CLK_SELA Input Pulldown When LOW, selects nQA output. LVCMOS/LVTTL interface levels. Differential output pair. LVPECL/ECL interface levels. 15, 16 nQA, QA Output NOTE: Pulldown and Pullup refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol RPULLDOWN RVCC/2 Parameter Input Pulldown Resistor Pullup/Pulldown Resistors Test Conditions Minimum Typical 37.5 37.5 Maximum Units K K
TABLE 3A. CONTROL INPUT FUNCTION TABLE, BANK A
Bank A Control Inputs CLK_SELA 0 1 Outputs QA, nQA Selects CLKA0, nCLKA0 Selects CLKA1, nCLKA1
TABLE 3B. CONTROL INPUT FUNCTION TABLE, BANK B
Bank B Control Inputs CLK_SELB 0 1
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Outputs QB0, nQB0 Follows CLKB input Low QB1, nQB1 Low Follows CLKB input
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REV. B JUNE 8, 2004
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS85354
DUAL 2:1/1:2 DIFFERENTIAL -TO-LVPECL/ECL MULTIPLEXER
4.6V (LVPECL mode, VEE = 0) NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage -4.6V (ECL mode, VCC = 0) -0.5V to VCC + 0.5 V 0.5V to VEE - 0.5V 50mA 100mA -65C to 150C 51.5C/W (0 lfpm) to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Character-
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC Negative Supply Voltage, VEE Inputs, VI (LVPECL mode) Inputs, VI (ECL mode) Outputs, IO Continuous Current Surge Current Storage Temperature, TSTG Package Thermal Impedance, JA
(Junction-to-Ambient)
Operating Temperature Range, TA -40C to +85C
istics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = 2.375V TO 3.465V, VEE = 0V OR VCC = 0V, VEE = -3.465V TO -2.375V
Symbol VCC I EE Parameter Positive Supply Voltage Power Supply Current Test Conditions Minimum 3.135 2.375 Typical 3.3 2.5 38 Maximum 3.465 2.625 Units V V mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = 2.375V TO 3.465V
Symbol VIH VIL IIH IIL Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current CLK_SELx CLK_SELx CLK_SELA, CLK_SELB CLK_SELA, CLK_SELB Test Conditions VCC = 2.5V or 3.3V VCC = 2.5V or 3.3V VCC = VIN = 3.465V, VCC = VIN = 2.625V VCC = 3.465 2.625V, VIN = 0V -150 Minimum 2 0 Typical Maximum VCC + 0.3 0.8 150 Units V V A A
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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS85354
DUAL 2:1/1:2 DIFFERENTIAL -TO-LVPECL/ECL MULTIPLEXER
-40C Min VCC-1.125 VCC-1.895 150 1.2 Typ VCC-1.025 VCC-1.755 800 Max VCC-0.92 VCC-1.62 1200 VCC Min VCC-1.075 VCC-1.875 150 1.2 25C Typ VCC-1.005 VCC-1.78 800 Max VCC-0.93 VCC-1.685 1200 VCC Min VCC-1.005 VCC-1.86 150 1.2 85C Typ VCC-0.97 VCC-1.765 800 Max VCC-0.935 VCC-1.67 1200 VCC
TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = 3.3V, VEE = 0V
Symbol VOH VOL VP P VCMR Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Peak-to-Peak Input Voltage Input High Voltage Common Mode Range; NOTE 2, 3 CLKAx, Input CLKB High Current nCLKAx, nCLKB CLKAx, CLKB Input Low Current nCLKAx, nCLKB Units V V mV V
IIH
150
150
150
A
-10 -150
-10 -150
-10 -150
A A
IIL
Input and output parameters var y 1:1 with VCC. VCC can var y +0.165V to -0.925V. NOTE 1: Outputs terminated with 50 to VCC - 2V. NOTE 2: Common mode voltage is defined as VIH. NOTE 3: For single-ended applications, the maximum input voltage for CLKAx, nCLKAx and CLKB, nCLKB is VCC + 0.3V.
TABLE 4D. ECL DC CHARACTERISTICS, VEE = -3.465V TO -2.375V, VCC = 0V
Symbol VOH VOL VPP VCMR IIH IIL Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Peak-to-Peak Input Voltage Input High Voltage Common Mode Range; NOTE 2, 3 Input CLKAx, CLKB High Current nCLKAx, nCLKB Input Low Current CLKAx, CLKB -40C Min
-1.125 -1.895 150 VEE+1.2V
25C Max
-0.92 -1.62 1200
85C Max
-0.93 -1.685 1200
Typ
-1.025 -1.755 800
Min
-1.075 -1.875 150 VEE+1.2V
Typ
-1.005 -1.78 800
Min
-1.005 -1.86 150 VEE+1.2V
Typ
-0.97 -1.765 800
Max
-0.935 -1.67 1200
Units
V V
mV
V A A A
VCC
150
VCC
150
VCC
150
-10
-10
-10
-150 -150 -150 nCLKAx, nCLKB Input and output parameters vary 1:1 with VCC. NOTE 1: Outputs terminated with 50 to VCC - 2V. NOTE 2: Common mode voltage is defined as VIH. NOTE 3: For single-ended applications, the maximum input voltage for CLKAx, nCLKAx and CLKB, nCLKB is VCC + 0.3V.
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REV. B JUNE 8, 2004
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS85354
DUAL 2:1/1:2 DIFFERENTIAL -TO-LVPECL/ECL MULTIPLEXER
Conditions Minimum Typical 330 85 0.03 55 170 Maximum 3 Units GHz ps ps ps dB ps
TABLE 5. AC CHARACTERISTICS, VCC = 2.375V TO 3.465V, VEE = 0V OR VCC = 0V, VEE = -3.465V TO -2.375V
Symbol fMAX Parameter Output Frequency Propagation Delay; NOTE 1 Par t-to-Par t Skew; NOTE 3, 4 Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter section MUX Isolation Output Rise/Fall Time 20% to 80%
t PD tsk(pp) tjit
tR/tF
All parameters are measured 1GHz unless otherwise noted. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
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REV. B JUNE 8, 2004
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS85354
DUAL 2:1/1:2 DIFFERENTIAL -TO-LVPECL/ECL MULTIPLEXER
PARAMETER MEASUREMENT INFORMATION
2V
VCC
Qx
SCOPE
VCC
LVPECL
nQx
nCLKA0, nCLKA1 nCLKB
V
PP
Cross Points
V
CMR
VEE
CLKA0, CLKA1 CLKB V EE
-0.375V to -1.465V
OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nQx PART 1 Qx nQy PART 2 Qy
nCLKA0, nCLKA1 nCLKB CLKA0, CLKA1 CLKB nQA, nQB0, nQB1 QA, QB0, QB1
tsk(pp)
tPD
PART-TO-PART SKEW
PROPAGATION DELAY
80% Clock Outputs
80% VSW I N G
20% tR tF
20%
OUTPUT RISE/FALL TIME
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REV. B JUNE 8, 2004
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS85354
DUAL 2:1/1:2 DIFFERENTIAL -TO-LVPECL/ECL MULTIPLEXER APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VCC/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio
of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VCC
R1 1K Single Ended Clock Input
CLKx
V_REF
nCLKx
C1 0.1u
R2 1K
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
TERMINATION FOR 3.3V LVPECL OUTPUTS
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 2A and 2B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
3.3V
Zo = 50
125
FOUT FIN
125
Zo = 50
Zo = 50 50 1 Z ((VOH + VOL) / (VCC - 2)) - 2 o 50 VCC - 2V RTT
FOUT
FIN
Zo = 50 84 84
RTT =
FIGURE 2A. LVPECL OUTPUT TERMINATION
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FIGURE 2B. LVPECL OUTPUT TERMINATION
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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS85354
DUAL 2:1/1:2 DIFFERENTIAL -TO-LVPECL/ECL MULTIPLEXER
ground level. The R3 in Figure 3B can be eliminated and the termination is shown in Figure 3C.
TERMINATION FOR 2.5V LVPECL OUTPUT
Figure 3A and Figure 3B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50 to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very close to
2.5V
2.5V
2.5V
VCCO=2.5V
VCCO=2.5V
R1 250
Zo = 50 Ohm
R3 250
Zo = 50 Ohm
+
+
Zo = 50 Ohm
Zo = 50 Ohm
-
2,5V LVPECL Driv er
2,5V LVPECL Driv er
R2 62.5
R4 62.5
R1 50
R2 50
R3 18
FIGURE 3A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
FIGURE 3B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
2.5V
VCCO=2.5V
Zo = 50 Ohm
+
Zo = 50 Ohm
-
2,5V LVPECL Driv er
R1 50
R2 50
FIGURE 3C. 2.5V LVPECL TERMINATION EXAMPLE
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REV. B JUNE 8, 2004
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS85354
DUAL 2:1/1:2 DIFFERENTIAL -TO-LVPECL/ECL MULTIPLEXER
here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 4A, the input termination applies for ICS HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation.
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 4A to 4E show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested
3.3V 3.3V
3.3V 1.8V
Zo = 50 Ohm
Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R2 50
R3 50 LVPECL Zo = 50 Ohm
CLK
nCLK
HiPerClockS Input
HiPerClockS Input
R1 50
R2 50
FIGURE 4A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN ICS HIPERCLOCKS LVHSTL DRIVER
BY
FIGURE 4B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVPECL DRIVER
BY
3.3V 3.3V 3.3V R3 125 Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVPECL R1 84 R2 84 HiPerClockS Input R4 125
3.3V
3.3V
LVDS_Driv er
Zo = 50 Ohm
CLK
R1 100
Zo = 50 Ohm
nCLK
Receiv er
FIGURE 4C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVPECL DRIVER
BY
FIGURE 4D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVDS DRIVER
BY
3.3V
3.3V
3.3V
LVPECL
Zo = 50 Ohm
C1
R3 125
R4 125
CLK
Zo = 50 Ohm
C2
nCLK
HiPerClockS Input
R5 100 - 200
R6 100 - 200
R1 84
R2 84
R5,R6 locate near the driver pin.
FIGURE 4E. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER WITH AC COUPLE
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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS85354
DUAL 2:1/1:2 DIFFERENTIAL -TO-LVPECL/ECL MULTIPLEXER POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS85354. Equations and example calculations are also provided.
1. Power Dissipation. The total power dissipation for the ICS85354 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
* *
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 38mA = 131.7mW Power (outputs)MAX = 27.83mW/Loaded Output pair If all outputs are loaded, the total power is 4 * 27.83mW = 111.3mW
Total Power_MAX (3.465, with all outputs switching) = 131.7mW + 111.3mW = 243mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 0 linear feet per minute and a multi-layer board, the appropriate value is 51.5C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85C with all outputs switching is: 85C + 0.243W * 51.5C/W = 97.5C. This is well below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE JA
FOR
16-PIN VFQFN, FORCED CONVECTION
JA by Velocity (Linear Feet per Minute)
0
Multi-Layer PCB, JEDEC Standard Test Boards 51.5C/W
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3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 5.
VCC
ICS85354
DUAL 2:1/1:2 DIFFERENTIAL -TO-LVPECL/ECL MULTIPLEXER
Q1
VOUT
RL
50
VCC - 2V
FIGURE 5. LVPECL DRIVER CIRCUIT
AND
TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of V - 2V.
CC
*
For logic high, VOUT = V (V
CC_MAX
OH_MAX
=V
CC_MAX
- 1.005V
-V
OH_MAX
) = 1.005 =V - 1.78V
*
For logic low, VOUT = V (V
CC_MAX
OL_MAX
CC_MAX
-V
OL_MAX
) = 1.78V
Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. ))/R ] * (V Pd_H = [(V - (V - 2V))/R ] * (V -V ) = [(2V - (V -V -V )= OH_MAX CC_MAX CC_MAX OH_MAX CC_MAX OH_MAX CC_MAX OH_MAX L L [(2V - 1.005V)/50] * 1.005V = 20mW
Pd_L = [(V
OL_MAX
- (V
CC_MAX
- 2V))/R ] * (V
L
CC_MAX
-V
OL_MAX
) = [(2V - (V
CC_MAX
-V
OL_MAX
))/R ] * (V
L
CC_MAX
-V
OL_MAX
)=
[(2V - 1.78V)/50] * 1.78V = 7.83mW Total Power Dissipation per output pair = Pd_H + Pd_L = 27.83mW
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ICS85354
DUAL 2:1/1:2 DIFFERENTIAL -TO-LVPECL/ECL MULTIPLEXER RELIABILITY INFORMATION
TABLE 7.
JAVS. AIR FLOW TABLE FOR 16 LEAD VFQFN
JA by Velocity (Linear Feet per Minute)
0
Multi-Layer PCB, JEDEC Standard Test Boards
51.5C/W
TRANSISTOR COUNT
The transistor count for ICS85354 is: 210
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Integrated Circuit Systems, Inc.
ICS85354
DUAL 2:1/1:2 DIFFERENTIAL -TO-LVPECL/ECL MULTIPLEXER
16 LEAD VFQFN
PACKAGE OUTLINE - K SUFFIX
FOR
TABLE 8. PACKAGE DIMENSIONS
JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS SYMBOL N A A1 A3 b e ND NE D D2 E E2 L 0.25 0.30 0.25 3.0 1.25 0.50 0.18 0.50 BASIC 4 4 3.0 1.25 0.80 0 0.25 Reference 0.30 MINIMUM 16 1.0 0.05 MAXIMUM
Reference Document: JEDEC Publication 95, MO-220
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Integrated Circuit Systems, Inc.
ICS85354
DUAL 2:1/1:2 DIFFERENTIAL -TO-LVPECL/ECL MULTIPLEXER
Marking 354A 354A Package 16 Lead VFQFN 16 Lead VFQFN on Tape and Reel Count 120 per Tube 3500 Temperature -40C to 85C -40C to 85C
TABLE 9. ORDERING INFORMATION
Part/Order Number ICS85354AK ICS85354AKT
The aforementioned trademark, HiPerClockSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 85354AK
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