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| 25AA256/25LC256 256K SPITM Bus Serial EEPROM Device Selection Table Part Number 25LC256 25AA256 VCC Range 2.5-5.5V 1.8-5.5V Page Size 64 Byte 64 Byte Temp. Ranges I, E I Packages P, SN, ST, MF P, SN, ST, MF Features * Max. clock 10 MHz * Low-power CMOS technology - Max. Write Current: 5 mA at 5.5V, 10 MHz - Read Current: 5 mA at 5.5V, 10 MHz - Standby Current: 1 A at 5.5V * 32,768 x 8-bit organization * 64 byte page * Self-timed ERASE and WRITE cycles (5 ms max.) * Block write protection - Protect none, 1/4, 1/2 or all of array * Built-in write protection - Power-on/off data protection circuitry - Write enable latch - Write-protect pin * Sequential read * High reliability - Endurance: 1,000,000 erase/write cycles - Data retention: > 200 years - ESD protection: > 4000V * Temperature ranges supported; - Industrial (I): -40C to +85C - Automotive (E): -40C to +125C * Standard and Pb-free packages available Description The Microchip Technology Inc. 25AA256/25LC256 (25XX256*) are 256k-bit Serial Electrically Erasable PROMs. The memory is accessed via a simple Serial Peripheral InterfaceTM (SPITM) compatible serial bus. The bus signals required are a clock input (SCK) plus separate data in (SI) and data out (SO) lines. Access to the device is controlled through a Chip Select (CS) input. Communication to the device can be paused via the hold pin (HOLD). While the device is paused, transitions on its inputs will be ignored, with the exception of Chip Select, allowing the host to service higher priority interrupts. The 25XX256 is available in standard packages including 8-lead PDIP and SOIC, and advanced packaging including 8-lead DFN and 8-lead TSSOP. Pb-free (Pure Sn) finish is also available. Package Types (not to scale) TSSOP (ST) CS SO WP VSS 1 2 3 4 8 7 6 5 VCC HOLD SCK SI PDIP/SOIC (P, SN) CS SO WP VSS 1 2 3 4 8 7 6 5 VCC HOLD SCK SI 25LC256 Pin Function Table Name CS SO WP VSS SI SCK HOLD VCC Function Chip Select Input Serial Data Output Write-Protect Ground Serial Data Input Serial Clock Input Hold Input Supply Voltage CS 1 DFN (MF) 8 25LC256 7 6 5 VCC HOLD SCK SI SO 2 WP 3 VSS 4 SPI is a registered trademark of Motorola Corporation. * 25XX256 is used in this document as a generic part number for the 25AA256, 25LC256 devices. 2003 Microchip Technology Inc. Preliminary DS21822C-page 1 25AA256/25LC256 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings () VCC.............................................................................................................................................................................6.5V All inputs and outputs w.r.t. VSS ......................................................................................................... -0.6V to VCC +1.0V Storage temperature .................................................................................................................................-65C to 150C Ambient temperature under bias ...............................................................................................................-40C to 125C ESD protection on all pins ..........................................................................................................................................4 kV NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for an extended period of time may affect device reliability. TABLE 1-1: DC CHARACTERISTICS Industrial (I): TA = -40C to +85C Automotive (E): TA = -40C to +125C Min. .7 VCC -0.3 -0.3 -- -- VCC -0.5 -- -- -- Max. VCC+1 0.3VCC 0.2VCC 0.4 0.2 -- 1 1 7 Units V V V V V V A A pF VCC 2.7V VCC < 2.7V IOL = 2.1 mA IOL = 1.0 mA, VCC < 2.5V IOH = -400 A CS = VCC, VIN = VSS TO VCC CS = VCC, VOUT = VSS TO VCC TA = 25C, CLK = 1.0 MHz, VCC = 5.0V (Note) VCC = 5.5V; FCLK = 10.0 MHz; SO = Open VCC = 2.5V; FCLK = 5.0 MHz; SO = Open VCC = 5.5V VCC = 2.5V CS = VCC = 5.5V, Inputs tied to VCC or VSS, 125C CS = VCC = 5.5V, Inputs tied to VCC or VSS, 85C VCC = 1.8V to 5.5V VCC = 2.5V to 5.5V Test Conditions DC CHARACTERISTICS Param. No. D001 D002 D003 D004 D005 D006 D007 D008 D009 Sym. VIH1 VIL1 VIL2 VOL VOL VOH ILI ILO CINT Characteristic High-level input voltage Low-level input voltage Low-level output voltage High-level output voltage Input leakage current Output leakage current Internal Capacitance (all inputs and outputs) D010 ICC Read Operating Current -- -- 5 2.5 mA mA mA mA A A D011 D012 ICC Write ICCS Standby Current -- -- -- -- 5 3 5 1 Note: This parameter is periodically sampled and not 100% tested. DS21822C-page 2 Preliminary 2003 Microchip Technology Inc. 25AA256/25LC256 TABLE 1-2: AC CHARACTERISTICS Industrial (I): TA = -40C to +85C Automotive (E): TA = -40C to +125C Min. -- -- -- 50 100 150 100 200 250 50 10 20 30 20 40 50 -- -- 50 100 150 50 100 150 50 50 -- -- -- 0 -- -- -- 20 40 80 Max. 10 5 3 -- -- -- -- -- -- -- -- -- -- -- -- -- 2 2 -- -- -- -- -- -- -- -- 50 100 160 -- 40 80 160 -- -- -- Units MHz MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns s s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns VCC = 1.8V to 5.5V VCC = 2.5V to 5.5V Test Conditions 4.5V Vcc 5.5V 2.5V Vcc < 4.5V 1.8V Vcc < 2.5V 4.5V Vcc 5.5V 2.5V Vcc < 4.5V 1.8V Vcc < 2.5V 4.5V Vcc 5.5V 2.5V Vcc < 4.5V 1.8V Vcc < 2.5V -- 4.5V Vcc 5.5V 2.5V Vcc < 4.5V 1.8V Vcc < 2.5V 4.5V Vcc 5.5V 2.5V Vcc < 4.5V 1.8V Vcc < 2.5V (Note 1) (Note 1) 4.5V Vcc 5.5V 2.5V Vcc < 4.5V 1.8V Vcc < 2.5V 4.5V Vcc 5.5V 2.5V Vcc < 4.5V 1.8V Vcc < 2.5V -- -- 4.5V Vcc 5.5V 2.5V Vcc < 4.5V 1.8V Vcc < 2.5V (Note 1) 4.5V Vcc 5.5V(Note 1) 2.5V Vcc 4.5V(Note 1) 1.8V Vcc 2.5V(Note 1) 4.5V Vcc 5.5V 2.5V Vcc < 4.5V 1.8V Vcc < 2.5V AC CHARACTERISTICS Param. Sym. No. 1 FCLK Characteristic Clock Frequency 2 TCSS CS Setup Time 3 TCSH CS Hold Time 4 5 TCSD Tsu CS Disable Time Data Setup Time 6 THD Data Hold Time 7 8 9 TR TF THI CLK Rise Time CLK Fall Time Clock High Time 10 TLO Clock Low Time 11 12 13 TCLD TCLE TV Clock Delay Time Clock Enable Time Output Valid from Clock Low Output Hold Time Output Disable Time 14 15 THO TDIS 16 THS HOLD Setup Time Note 1: This parameter is periodically sampled and not 100% tested. 2: TWC begins on the rising edge of CS after a valid write sequence and ends when the internal write cycle is complete. 3: This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please consult the Total EnduranceTM Model which can be obtained from our web site: www.microchip.com. 2003 Microchip Technology Inc. Preliminary DS21822C-page 3 25AA256/25LC256 TABLE 1-2: AC CHARACTERISTICS (CONTINUED) Industrial (I): TA = -40C to +85C Automotive (E): TA = -40C to +125C Min. 20 40 80 30 60 160 30 60 160 -- 1M Max. -- -- -- -- -- -- -- -- -- 5 -- Units ns ns ns ns ns ns ns ns ns ms VCC = 1.8V to 5.5V VCC = 2.5V to 5.5V Test Conditions 4.5V Vcc 5.5V 2.5V Vcc < 4.5V 1.8V Vcc < 2.5V 4.5V Vcc 5.5V(Note 1) 2.5V Vcc < 4.5V(Note 1) 1.8V Vcc < 2.5V(Note 1) 4.5V Vcc 5.5V 2.5V Vcc < 4.5V 1.8V Vcc < 2.5V (NOTE 2) AC CHARACTERISTICS Param. Sym. No. 17 THH Characteristic HOLD Hold Time 18 THZ HOLD Low to Output High-Z HOLD High to Output Valid Internal Write Cycle Time Endurance 19 THV 20 21 TWC -- E/W (NOTE 3) Cycles Note 1: This parameter is periodically sampled and not 100% tested. 2: TWC begins on the rising edge of CS after a valid write sequence and ends when the internal write cycle is complete. 3: This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please consult the Total EnduranceTM Model which can be obtained from our web site: www.microchip.com. TABLE 1-3: AC Waveform: VLO = 0.2V AC TEST CONDITIONS -- (Note 1) (Note 2) -- 0.5 VCC 0.5 VCC VHI = VCC - 0.2V VHI = 4.0V CL = 100 pF Timing Measurement Reference Level Input Output Note 1: For VCC 4.0V 2: For Vcc > 4.0V DS21822C-page 4 Preliminary 2003 Microchip Technology Inc. 25AA256/25LC256 FIGURE 1-1: CS 16 SCK 18 SO n+2 n+1 n high-impedance 19 n 5 n n-1 n-1 17 16 17 HOLD TIMING don't care SI HOLD n+2 n+1 n FIGURE 1-2: SERIAL INPUT TIMING 4 CS 2 Mode 1,1 SCK Mode 0,0 5 SI 6 LSB in 7 8 3 12 11 MSB in SO high-impedance FIGURE 1-3: SERIAL OUTPUT TIMING CS 9 SCK 13 14 SO MSB out 15 ISB out 10 3 Mode 1,1 Mode 0,0 SI don't care 2003 Microchip Technology Inc. Preliminary DS21822C-page 5 25AA256/25LC256 2.0 2.1 FUNCTIONAL DESCRIPTION Principles of Operation 2.3 Write Sequence The 25XX256 is a 32768 byte Serial EEPROM designed to interface directly with the Serial Peripheral Interface (SPI) port of many of today's popular microcontroller families, including Microchip's PICmicro(R) microcontrollers. It may also interface with microcontrollers that do not have a built-in SPI port by using discrete I/O lines programmed properly in firmware to match the SPI protocol. The 25XX256 contains an 8-bit instruction register. The device is accessed via the SI pin, with data being clocked in on the rising edge of SCK. The CS pin must be low and the HOLD pin must be high for the entire operation. Table 2-1 contains a list of the possible instruction bytes and format for device operation. All instructions, addresses, and data are transferred MSB first, LSB last. Data (SI) is sampled on the first rising edge of SCK after CS goes low. If the clock line is shared with other peripheral devices on the SPI bus, the user can assert the HOLD input and place the 25XX256 in `HOLD' mode. After releasing the HOLD pin, operation will resume from the point when the HOLD was asserted. Prior to any attempt to write data to the 25XX256, the write enable latch must be set by issuing the WREN instruction (Figure 2-4). This is done by setting CS low and then clocking out the proper instruction into the 25XX256. After all eight bits of the instruction are transmitted, the CS must be brought high to set the write enable latch. If the write operation is initiated immediately after the WREN instruction without CS being brought high, the data will not be written to the array because the write enable latch will not have been properly set. Once the write enable latch is set, the user may proceed by setting the CS low, issuing a WRITE instruction, followed by the 16-bit address, with the first MSB of the address being a don't care bit, and then the data to be written. Up to 64 bytes of data can be sent to the device before a write cycle is necessary. The only restriction is that all of the bytes must reside in the same page. Note: Page write operations are limited to writing bytes within a single physical page, regardless of the number of bytes actually being written. Physical page boundaries start at addresses that are integer multiples of the page buffer size (or `page size') and, end at addresses that are integer multiples of page size - 1. If a Page Write command attempts to write across a physical page boundary, the result is that the data wraps around to the beginning of the current page (overwriting data previously stored there), instead of being written to the next page as might be expected. It is therefore necessary for the application software to prevent page write operations that would attempt to cross a page boundary. 2.2 Read Sequence The device is selected by pulling CS low. The 8-bit read instruction is transmitted to the 25XX256 followed by the 16-bit address, with the first MSB of the address being a don't care bit. After the correct read instruction and address are sent, the data stored in the memory at the selected address is shifted out on the SO pin. The data stored in the memory at the next address can be read sequentially by continuing to provide clock pulses. The internal address pointer is automatically incremented to the next higher address after each byte of data is shifted out. When the highest address is reached (7FFFh), the address counter rolls over to address 0000h allowing the read cycle to be continued indefinitely. The read operation is terminated by raising the CS pin (Figure 2-1). For the data to be actually written to the array, the CS must be brought high after the Least Significant bit (D0) of the nth data byte has been clocked in. If CS is brought high at any other time, the write operation will not be completed. Refer to Figure 2-2 and Figure 2-3 for more detailed illustrations on the byte write sequence and the page write sequence respectively. While the write is in progress, the Status register may be read to check the status of the WPEN, WIP, WEL, BP1 and BP0 bits (Figure 2-6). A read attempt of a memory array location will not be possible during a write cycle. When the write cycle is completed, the write enable latch is reset. DS21822C-page 6 Preliminary 2003 Microchip Technology Inc. 25AA256/25LC256 BLOCK DIAGRAM Status Register HV Generator I/O Control Logic Memory Control Logic X Dec EEPROM Array Page Latches SI SO CS SCK HOLD WP VCC VSS Y Decoder Sense Amp. R/W Control TABLE 2-1: INSTRUCTION SET Instruction Format Description Read data from memory array beginning at selected address Write data to memory array beginning at selected address Reset the write enable latch (disable write operations) Set the write enable latch (enable write operations) Read Status register Write Status register Instruction Name READ WRITE WRDI WREN RDSR WRSR 0000 0011 0000 0010 0000 0100 0000 0110 0000 0101 0000 0001 FIGURE 2-1: CS 0 SCK READ SEQUENCE 1 2 3 4 5 6 7 8 9 10 11 21 22 23 24 25 26 27 28 29 30 31 instruction SI 0 0 0 0 0 0 1 16-bit address 1 15 14 13 12 2 1 0 data out 7 6 5 4 3 2 1 0 high-impedance SO 2003 Microchip Technology Inc. Preliminary DS21822C-page 7 25AA256/25LC256 FIGURE 2-2: CS Twc 0 SCK instruction SI 0 0 0 0 0 0 1 16-bit address 0 15 14 13 12 2 1 0 7 6 data byte 5 4 3 2 1 0 1 2 3 4 5 6 7 8 9 10 11 21 22 23 24 25 26 27 28 29 30 31 BYTE WRITE SEQUENCE high-impedance SO FIGURE 2-3: CS 0 SCK 1 PAGE WRITE SEQUENCE 2 3 4 5 6 7 8 9 10 11 16-bit address 21 22 23 24 25 26 27 28 29 30 31 data byte 1 2 1 0 7 6 5 4 3 2 1 0 instruction SI 0 0 0 0 0 01 0 15 14 13 12 CS 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCK data byte 2 SI 7 6 5 4 3 2 1 0 7 6 data byte 3 5 4 3 2 1 0 7 data byte n (64 max) 6 5 4 3 2 1 0 DS21822C-page 8 Preliminary 2003 Microchip Technology Inc. 25AA256/25LC256 2.4 Write Enable (WREN) and Write Disable (WRDI) The following is a list of conditions under which the write enable latch will be reset: * * * * Power-up WRDI instruction successfully executed WRSR instruction successfully executed WRITE instruction successfully executed The 25XX256 contains a write enable latch. See Table 2-4 for the Write-Protect Functionality Matrix. This latch must be set before any write operation will be completed internally. The WREN instruction will set the latch, and the WRDI will reset the latch. FIGURE 2-4: WRITE ENABLE SEQUENCE (WREN) CS 0 SCK 1 2 3 4 5 6 7 SI 0 0 0 0 0 1 1 0 high-impedance SO FIGURE 2-5: WRITE DISABLE SEQUENCE (WRDI) CS 0 SCK 1 2 3 4 5 6 7 SI 0 0 0 0 0 1 0 1 0 high-impedance SO 2003 Microchip Technology Inc. Preliminary DS21822C-page 9 25AA256/25LC256 2.5 Read Status Register Instruction (RDSR) The Write Enable Latch (WEL) bit indicates the status of the write enable latch and is read-only. When set to a `1', the latch allows writes to the array, when set to a `0', the latch prohibits writes to the array. The state of this bit can always be updated via the WREN or WRDI commands regardless of the state of write protection on the Status register. These commands are shown in Figure 2-4 and Figure 2-5. The Block Protection (BP0 and BP1) bits indicate which blocks are currently write-protected. These bits are set by the user issuing the WRSR instruction. These bits are nonvolatile, and are shown in Table 2-3. See Figure 2-6 for the RDSR timing sequence. The Read Status Register instruction (RDSR) provides access to the Status register. The Status register may be read at any time, even during a write cycle. The Status register is formatted as follows: TABLE 2-2: STATUS REGISTER 0 R WIP 7 654 3 2 1 W/R - - - W/R W/R R WPEN X X X BP1 BP0 WEL W/R = writable/readable. R = read-only. The Write-In-Process (WIP) bit indicates whether the 25XX256 is busy with a write operation. When set to a `1', a write is in progress, when set to a `0', no write is in progress. This bit is read-only. FIGURE 2-6: CS READ STATUS REGISTER TIMING SEQUENCE (RDSR) 0 SCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 instruction SI 0 0 0 0 0 1 0 1 high-impedance SO 7 data from Status register 6 5 4 3 2 1 0 DS21822C-page 10 Preliminary 2003 Microchip Technology Inc. 25AA256/25LC256 2.6 Write Status Register Instruction (WRSR) See Figure 2-7 for the WRSR timing sequence. The Write Status Register instruction (WRSR) allows the user to write to the nonvolatile bits in the Status register as shown in Table 2-2. The user is able to select one of four levels of protection for the array by writing to the appropriate bits in the Status register. The array is divided up into four segments. The user has the ability to write-protect none, one, two, or all four of the segments of the array. The partitioning is controlled as shown in Table 2-3. The Write-Protect Enable (WPEN) bit is a nonvolatile bit that is available as an enable bit for the WP pin. The Write-Protect (WP) pin and the Write-Protect Enable (WPEN) bit in the Status register control the programmable hardware write-protect feature. Hardware write protection is enabled when WP pin is low and the WPEN bit is high. Hardware write protection is disabled when either the WP pin is high or the WPEN bit is low. When the chip is hardware write-protected, only writes to nonvolatile bits in the Status register are disabled. See Table 2-4 for a matrix of functionality on the WPEN bit. TABLE 2-3: BP1 ARRAY PROTECTION BP0 Array Addresses Write-Protected none upper 1/4 (6000h - 7FFFh) upper 1/2 (4000h - 7FFFh) all (0000h - 7FFFh) 0 0 1 1 0 1 0 1 FIGURE 2-7: CS WRITE STATUS REGISTER TIMING SEQUENCE (WRSR) 0 SCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 instruction SI 0 0 0 0 0 0 0 1 7 6 data to Status register 5 4 3 2 1 0 high-impedance SO Note: An internal write cycle (TWC) is initiated on the rising edge of CS after a valid write Status Register sequence. 2003 Microchip Technology Inc. Preliminary DS21822C-page 11 25AA256/25LC256 2.7 Data Protection 2.8 Power-On State The following protection has been implemented to prevent inadvertent writes to the array: * The write enable latch is reset on power-up * A write enable instruction must be issued to set the write enable latch * After a byte write, page write or Status register write, the write enable latch is reset * CS must be set high after the proper number of clock cycles to start an internal write cycle * Access to the array during an internal write cycle is ignored and programming is continued The 25XX256 powers on in the following state: * The device is in low-power Standby mode (CS = 1) * The write enable latch is reset * SO is in high-impedance state * A high-to-low-level transition on CS is required to enter active state TABLE 2-4: WEL (SR bit 1) 0 1 1 1 x = don't care WRITE-PROTECT FUNCTIONALITY MATRIX WPEN (SR bit 7) x 0 1 1 WP (pin 3) x x 0 (low) 1 (high) Protected Blocks Protected Protected Protected Protected Unprotected Blocks Protected Writable Writable Writable Status Register Protected Writable Protected Writable DS21822C-page 12 Preliminary 2003 Microchip Technology Inc. 25AA256/25LC256 3.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table 3-1. The WP pin function is blocked when the WPEN bit in the Status register is low. This allows the user to install the 25XX256 in a system with WP pin grounded and still be able to write to the Status register. The WP pin functions will be enabled when the WPEN bit is set high. TABLE 3-1: Name CS SO WP VSS SI SCK HOLD VCC PIN FUNCTION TABLE Pin Number 1 2 3 4 5 6 7 8 Function Chip Select Input Serial Data Output Write-Protect Pin Ground Serial Data Input Serial Clock Input Hold Input Supply Voltage 3.4 Serial Input (SI) The SI pin is used to transfer data into the device. It receives instructions, addresses and data. Data is latched on the rising edge of the serial clock. 3.5 Serial Clock (SCK) The SCK is used to synchronize the communication between a master and the 25XX256. Instructions, addresses or data present on the SI pin are latched on the rising edge of the clock input, while data on the SO pin is updated after the falling edge of the clock input. 3.1 Chip Select (CS) 3.6 Hold (HOLD) A low level on this pin selects the device. A high level deselects the device and forces it into Standby mode. However, a programming cycle which is already initiated or in progress will be completed, regardless of the CS input signal. If CS is brought high during a program cycle, the device will go into Standby mode as soon as the programming cycle is complete. When the device is deselected, SO goes to the high-impedance state, allowing multiple parts to share the same SPI bus. A low-to-high transition on CS after a valid write sequence initiates an internal write cycle. After powerup, a low level on CS is required prior to any sequence being initiated. 3.2 Serial Output (SO) The SO pin is used to transfer data out of the 25XX256. During a read cycle, data is shifted out on this pin after the falling edge of the serial clock. The HOLD pin is used to suspend transmission to the 25XX256 while in the middle of a serial sequence without having to retransmit the entire sequence again. It must be held high any time this function is not being used. Once the device is selected and a serial sequence is underway, the HOLD pin may be pulled low to pause further serial communication without resetting the serial sequence. The HOLD pin must be brought low while SCK is low, otherwise the HOLD function will not be invoked until the next SCK high-tolow transition. The 25XX256 must remain selected during this sequence. The SI, SCK and SO pins are in a high-impedance state during the time the device is paused and transitions on these pins will be ignored. To resume serial communication, HOLD must be brought high while the SCK pin is low, otherwise serial communication will not resume. Lowering the HOLD line at any time will tri-state the SO line. 3.3 Write-Protect (WP) This pin is used in conjunction with the WPEN bit in the Status register to prohibit writes to the nonvolatile bits in the Status register. When WP is low and WPEN is high, writing to the nonvolatile bits in the Status register is disabled. All other operations function normally. When WP is high, all functions, including writes to the nonvolatile bits in the Status register, operate normally. If the WPEN bit is set, WP low during a Status register write sequence will disable writing to the Status register. If an internal write cycle has already begun, WP going low will have no effect on the write. 2003 Microchip Technology Inc. Preliminary DS21822C-page 13 25AA256/25LC256 4.0 4.1 PACKAGING INFORMATION Package Marking Information 8-Lead DFN XXXXXXX T/XXXXX YYWW NNN Example: 25LC256 I/MF 0328 1L7 8-Lead PDIP XXXXXXXX T/XXXNNN YYWW Example: 25AA256 I/P 1L7 0328 8-Lead SOIC Example: XXXXXXXX T/XXYYWW NNN 25LC256 I/SN 0328 1L7 8-Lead TSSOP XXXX TYWW NNN Example: 5LE I328 1L7 TSSOP 1st Line Marking Codes Device 25AA256 25LC256 std mark 5AE 5LE Pb-free mark NAE NLE Legend: XX...X T Blank YY WW NNN Part number Temperature (I, E) Commercial Year code (last 2 digits of calendar year) except TSSOP which uses only the last 1 digit Week code (week of January 1 is week `01') Alphanumeric traceability code Note: Custom marking available. DS21822C-page 14 Preliminary 2003 Microchip Technology Inc. 25AA256/25LC256 8-Lead Plastic Dual Flat No Lead Package (MF) 6x5 mm Body (DFN-S) E E1 n L B p R D1 D D2 1 2 TOP VIEW EXPOSED METAL PADS E2 BOTTOM VIEW PIN 1 ID A2 A3 A A1 Units Dimension Limits Number of Pins Pitch Overall Height Molded Package Thickness Standoff Base Thickness Overall Length Molded Package Length Exposed Pad Length Overall Width Molded Package Width Exposed Pad Width Lead Width Lead Length Tie Bar Width Mold Draft Angle Top *Controlling Parameter n p A A2 A1 A3 E E1 E2 D D1 D2 B L R .085 .014 .020 .152 .000 MIN INCHES NOM 8 .050 BSC .033 .026 .0004 .008 REF. .194 BSC .184 BSC .158 .236 BSC .226 BSC .091 .016 .024 .014 12 .097 .019 .030 .163 .039 .031 .002 MAX MIN MILLIMETERS* NOM 8 1.27 BSC 0.85 0.65 0.00 0.01 0.20 REF. 4.92 BSC 4.67 BSC 3.85 4.00 5.99 BSC 5.74 BSC 2.16 0.35 0.50 2.31 0.40 0.60 .356 12 2.46 0.47 0.75 4.15 1.00 0.80 0.05 MAX Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC equivalent: pending Drawing No. C04-113 2003 Microchip Technology Inc. Preliminary DS21822C-page 15 25AA256/25LC256 8-Lead Plastic Dual In-line (P) - 300 mil (PDIP) E1 D 2 n 1 E A A2 c L A1 eB B1 p B Number of Pins Pitch Top to Seating Plane Molded Package Thickness Base to Seating Plane Shoulder to Shoulder Width Molded Package Width Overall Length Tip to Seating Plane Lead Thickness Upper Lead Width Lower Lead Width Overall Row Spacing Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic Units Dimension Limits n p A A2 A1 E E1 D L c B1 B eB MIN INCHES* NOM 8 .100 .155 .130 .313 .250 .373 .130 .012 .058 .018 .370 10 10 MAX MIN .140 .115 .015 .300 .240 .360 .125 .008 .045 .014 .310 5 5 .170 .145 .325 .260 .385 .135 .015 .070 .022 .430 15 15 MILLIMETERS NOM 8 2.54 3.56 3.94 2.92 3.30 0.38 7.62 7.94 6.10 6.35 9.14 9.46 3.18 3.30 0.20 0.29 1.14 1.46 0.36 0.46 7.87 9.40 5 10 5 10 MAX 4.32 3.68 8.26 6.60 9.78 3.43 0.38 1.78 0.56 10.92 15 15 Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-018 DS21822C-page 16 Preliminary 2003 Microchip Technology Inc. 25AA256/25LC256 8-Lead Plastic Small Outline (SN) - Narrow, 150 mil (SOIC) E E1 p D 2 B n 1 h 45 c A A2 L A1 Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Chamfer Distance Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic Units Dimension Limits n p A A2 A1 E E1 D h L c B MIN .053 .052 .004 .228 .146 .189 .010 .019 0 .008 .013 0 0 INCHES* NOM 8 .050 .061 .056 .007 .237 .154 .193 .015 .025 4 .009 .017 12 12 MAX MIN .069 .061 .010 .244 .157 .197 .020 .030 8 .010 .020 15 15 MILLIMETERS NOM 8 1.27 1.35 1.55 1.32 1.42 0.10 0.18 5.79 6.02 3.71 3.91 4.80 4.90 0.25 0.38 0.48 0.62 0 4 0.20 0.23 0.33 0.42 0 12 0 12 MAX 1.75 1.55 0.25 6.20 3.99 5.00 0.51 0.76 8 0.25 0.51 15 15 Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-057 2003 Microchip Technology Inc. Preliminary DS21822C-page 17 25AA256/25LC256 8-Lead Plastic Thin Shrink Small Outline (ST) - 4.4 mm (TSSOP) E E1 p D 2 1 n B A c L A1 A2 Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Molded Package Length Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic Units Dimension Limits n p A A2 A1 E E1 D L c B MIN INCHES NOM 8 .026 MAX MIN .033 .002 .246 .169 .114 .020 0 .004 .007 0 0 .035 .004 .251 .173 .118 .024 4 .006 .010 5 5 .043 .037 .006 .256 .177 .122 .028 8 .008 .012 10 10 MILLIMETERS* NOM MAX 8 0.65 1.10 0.85 0.90 0.95 0.05 0.10 0.15 6.25 6.38 6.50 4.30 4.40 4.50 2.90 3.00 3.10 0.50 0.60 0.70 0 4 8 0.09 0.15 0.20 0.19 0.25 0.30 0 5 10 0 5 10 Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005" (0.127mm) per side. JEDEC Equivalent: MO-153 Drawing No. C04-086 DS21822C-page 18 Preliminary 2003 Microchip Technology Inc. 25AA256/25LC256 APPENDIX A: Revision C Corrections to Section 1.0, Electrical Characteristics. REVISION HISTORY 2003 Microchip Technology Inc. Preliminary DS21822C-page 19 25AA256/25LC256 NOTES: DS21822C-page 20 Preliminary 2003 Microchip Technology Inc. 25AA256/25LC256 ON-LINE SUPPORT Microchip provides on-line support on the Microchip World Wide Web site. The web site is used by Microchip as a means to make files and information easily available to customers. To view the site, the user must have access to the Internet and a web browser, such as Netscape(R) or Microsoft(R) Internet Explorer. Files are also available for FTP download from our FTP site. SYSTEMS INFORMATION AND UPGRADE HOT LINE The Systems Information and Upgrade Line provides system users a listing of the latest versions of all of Microchip's development systems software products. Plus, this line provides information on how customers can receive the most current upgrade kits.The Hot Line Numbers are: 1-800-755-2345 for U.S. and most of Canada, and 1-480-792-7302 for the rest of the world. 042003 Connecting to the Microchip Internet Web Site The Microchip web site is available at the following URL: www.microchip.com The file transfer site is available by using an FTP service to connect to: ftp://ftp.microchip.com The web site and file transfer site provide a variety of services. Users may download files for the latest Development Tools, Data Sheets, Application Notes, User's Guides, Articles and Sample Programs. A variety of Microchip specific business information is also available, including listings of Microchip sales offices, distributors and factory representatives. Other data available for consideration is: * Latest Microchip Press Releases * Technical Support Section with Frequently Asked Questions * Design Tips * Device Errata * Job Postings * Microchip Consultant Program Member Listing * Links to other useful web sites related to Microchip Products * Conferences for products, Development Systems, technical information and more * Listing of seminars and events 2003 Microchip Technology Inc. Preliminary DS21822C-page 21 25AA256/25LC256 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. To: RE: Technical Publications Manager Reader Response Total Pages Sent ________ From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ Application (optional): Would you like a reply? Y N Literature Number: DS21822C FAX: (______) _________ - _________ Device: 25AA256/25LC256 Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS21822C-page 22 Preliminary 2003 Microchip Technology Inc. 25AA256/25LC256 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device X Tape & Reel - X Temp Range /XX Package X Lead Finish Examples: a) 25AA256-I/STG = 256k-bit, 1.8V Serial EEPROM, Industrial temp., TSSOP package, Pb-free 25AA256T-I/SN = 256k-bit, 1.8V Serial EEPROM, Industrial temp., Tape & Reel, SOIC package 25AA256T-I/ST = 256k-bit, 1.8V Serial EEPROM, Industrial temp., Tape & Reel, TSSOP package 25LC256-I/STG = 256k-bit, 2.5V Serial EEPROM, Industrial temp., TSSOP package, Pb-free 25LC256-I/P = 256k-bit, 2.5V Serial EEPROM, Industrial temp., P-DIP package 25LC256T-E/ST = 256k-bit, 2.5V Serial EEPROM, Extended temp., Tape & Reel, TSSOP package b) Device 25AA256 25LC256 Blank T I E = = = = 256k-bit, 1.8V, 64-Byte Page, SPI Serial EEPROM 256k-bit, 2.5V, 64-Byte Page, SPI Serial EEPROM Standard packaging (tube) Tape & Reel -40C to+85C -40C to+125C e) Package MF P SN ST = = = = Micro Lead Frame (6 x 5 mm body), 8-lead Plastic DIP (300 mil body), 8-lead Plastic SOIC (150 mil body), 8-lead TSSOP, 8-lead f) c) Tape & Reel Temperature Range d) Lead Finish Blank G = = Standard 63% / 37% Sn/Pb Matte Tin (Pure Sn) Sales and Support Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. 2. 3. Your local Microchip sales office The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277 The Microchip Worldwide Site (www.microchip.com) Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. New Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products. 2003 Microchip Technology Inc. Preliminary DS21822C-page 23 25AA256/25LC256 NOTES: DS21822C-page 24 Preliminary 2003 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: * * Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." * * * Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, MPLAB, PIC, PICmicro, PICSTART, PRO MATE and PowerSmart are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, microID, MXDEV, MXLAB, PICMASTER, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Application Maestro, dsPICDEM, dsPICDEM.net, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, microPort, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPIC, Select Mode, SmartSensor, SmartShunt, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. Serialized Quick Turn Programming (SQTP) is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2003, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999 and Mountain View, California in March 2002. The Company's quality system processes and procedures are QS-9000 compliant for its PICmicro(R) 8-bit MCUs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, non-volatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001 certified. 2003 Microchip Technology Inc. Preliminary DS21822C-page 25 WORLDWIDE SALES AND SERVICE AMERICAS Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: 480-792-7627 Web Address: http://www.microchip.com ASIA/PACIFIC Australia Suite 22, 41 Rawson Street Epping 2121, NSW Australia Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 Korea 168-1, Youngbo Bldg. 3 Floor Samsung-Dong, Kangnam-Ku Seoul, Korea 135-882 Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 Singapore 200 Middle Road #07-02 Prime Centre Singapore, 188980 Tel: 65-6334-8870 Fax: 65-6334-8850 China - Beijing Unit 915 Bei Hai Wan Tai Bldg. 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B505A, Fullhope Plaza, No. 12 Hong Kong Central Rd. Qingdao 266071, China Tel: 86-532-5027355 Fax: 86-532-5027205 Netherlands P. A. De Biesbosch 14 NL-5152 SC Drunen, Netherlands Tel: 31-416-690399 Fax: 31-416-690340 Toronto 6285 Northam Drive, Suite 108 Mississauga, Ontario L4V 1X5, Canada Tel: 905-673-0699 Fax: 905-673-6509 India Divyasree Chambers 1 Floor, Wing A (A3/A4) No. 11, O'Shaugnessey Road Bangalore, 560 025, India Tel: 91-80-2290061 Fax: 91-80-2290062 United Kingdom 505 Eskdale Road Winnersh Triangle Wokingham Berkshire, England RG41 5TU Tel: 44-118-921-5869 Fax: 44-118-921-5820 07/28/03 Japan Benex S-1 6F 3-18-20, Shinyokohama Kohoku-Ku, Yokohama-shi Kanagawa, 222-0033, Japan Tel: 81-45-471- 6166 Fax: 81-45-471-6122 DS21822C-page 26 Preliminary 2003 Microchip Technology Inc. |
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