![]() |
|
If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
Datasheet File OCR Text: |
STS1C1S250 N-CHANNEL 250V - 0.9 - 0.75A SO-8 P-CHANNEL 250V - 2.1 - 0.6A SO-8 MESH OVERLAY POWER MOSFET TYPE STS1C1S250(N-Channel) STS1C1S250(P-Channel) s s s s VDSS 250 V 250 V RDS(on) <1.4 <2.8 ID 0.80 A 0.60 A TYPICAL RDS(on) (N-Channel) = 0.9 TYPICAL RDS(on) (P-Channel) = 2.1 GATE-SOURCE ZENER DIODE STANDARD OUTLINE FOR EASY AUTOMATED SURFACE MOUNT ASSEMBLY SO-8 DESCRIPTION This complementary pair uses the Company's proprietary high voltage MESH OVERLAYTM process based on advanced strip layout and efficient edge termination. Designed for high volume manufacturing capability, it is ideal in lighting converters such as CFL supplied from 120V mains. INTERNAL SCHEMATIC DIAGRAM s APPLICATIONS LIGHTING ABSOLUTE MAXIMUM RATINGS Symbol VDS VDGR VGS ID ID IDM (1) PTOT Tstg Tj October 2003 Parameter Drain-source Voltage (VGS = 0) Drain-gate Voltage (RGS = 20 k) Gate- source Voltage Drain Current (continuous) at TC = 25C Drain Current (continuous) at TC = 100C Drain Current (pulsed) Total Dissipation at TC = 25C Single Operation Total Dissipation at TC = 25C Dual Operation Storage Temperature Max. Operating Junction Temperature 0.75 0.47 3 1.6 2 -65 to 150 150 250 250 25 0.60 0.38 2.4 Value N-CHANNEL P-CHANNEL 250 250 V V V A A A W C C 1/10 Unit (1)Pulse width limited by safe operating area STS1C1S250 THERMAL DATA Rthj-amb (2) Thermal Resistance Junction-ambient Max (Single Operating) (Dual Operating) (2) Mounted on 0.5 in pad of 2oz. copper. 62.5 78 C/W ELECTRICAL CHARACTERISTICS (TCASE = 25 C UNLESS OTHERWISE SPECIFIED) OFF Symbol V(BR)DSS Parameter Drain-source Breakdown Voltage Test Conditions N-CHANNEL ID = 250 A, VGS = 0 P-CHANNEL ID = 250 A, VGS = 0 VDS = Max Rating VDS = Max Rating, TC = 125 C n-ch p-ch n-ch p-ch n-ch p-ch n-ch p-ch Min. 250 250 1 1 10 10 10 10 Typ. Max. Unit V V A A A A A A IDSS Zero Gate Voltage Drain Current (VGS = 0) IGSS Gate-body Leakage Current (VDS = 0) VGS = 20V ON (1) Symbol VGS(th) Parameter Gate Threshold Voltage Test Conditions N-CHANNEL VDS = VGS, ID = 250A P-CHANNEL VDS = VGS, ID = 250A N-CHANNEL VGS = 10V, ID = 0.40A P-CHANNEL VGS = 10V, ID = 0.30A n-ch p-ch n-ch p-ch Min. 2 2 Typ. 3 3 0.9 2.1 Max. 4 4 1.4 2.8 Unit V V RDS(on) Static Drain-source On Resistance DYNAMIC Symbol Ciss Coss Crss Rg Parameter Input Capacitance Output Capacitance Reverse Transfer Capacitance Gate Input Resistance f=1 MHz Gate DC Bias=0 Test Signal Level=20mV Open Drain Test Conditions N-CHANNEL VDS = 25V, f = 1 MHz, VGS = 0 P-CHANNEL VDS = 25V, f = 1 MHz, VGS = 0 n-ch p-ch n-ch p-ch n-ch p-ch n-ch p-ch Min. Typ. 325 260 51 52 24 25.5 6 6 Max. Unit pF pF pF pF pF pF (3) Pulsed: Pulse duration = 300 s, duty cycle 1.5 %. 2/10 STS1C1S250 ELECTRICAL CHARACTERISTICS (CONTINUED) SWITCHING ON Symbol td(on) Parameter Turn-on Delay Time Test Conditions N-CHANNEL VDD = 125V, ID = 1.5A RG = 4.7 VGS = 10V P-CHANNEL VDD = 125V, ID = 1.5A RG = 4.7 VGS = 10V (Resistive, see Figure 3) N-CHANNEL VDD =200V, ID=1.5A, VGS = 10V P-CHANNEL VDD = 200V, ID= 1.5A, VGS = 10V n-ch p-ch Min. Typ. 9 12 Max. Unit ns ns tr Rise Time n-ch p-ch n-ch p-ch n-ch p-ch n-ch p-ch 11 22 15 16 1.9 1.4 7 7.6 20 21 ns ns nC nC nC nC nC nC Qg Qgs Qgd Total Gate Charge Gate-Source Charge Gate-Drain Charge SWITCHING OFF Symbol td(off) Parameter Turn-off Delay Time Test Conditions N-CHANNEL VDD = 125V, ID = 1.5A, RG = 4.7, VGS = 10V P-CHANNEL VDD = 200V, ID = 1.5A, RG = 4.7, VGS = 10V (see test circuit, Figure 5) Test Conditions n-ch p-ch n-ch p-ch ISD = 3A, VGS = 0 ISD = 3A, VGS = 0 N-CHANNEL ISD = 0.8A, di/dt = 100A/s, VDD = 50V, Tj = 150C P-CHANNEL ISD = 0.60A, di/dt = 100A/s, VDD = 40V, Tj = 150C (see test circuit, Figure 5) Test Conditions Igs= 500 A (Open Drain) n-ch p-ch n-ch p-ch n-ch p-ch n-ch p-ch 127 143 450 806 7 11 n-ch p-ch n-ch p-ch Min. Typ. 31 29.5 11 7 Max. Unit ns ns ns ns tf Fall Time SOURCE DRAIN DIODE Symbol ISD ISDM (4) VSD (5) trr Qrr IRRM Parameter Source-drain Current Source-drain Current (pulsed) Forward On Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Curren Min. Typ. Max. 0.75 0.6 3 2.4 1.5 1.5 Unit A A A A V V ns ns nC nC A A GATE-SOURCE ZENER DIODE Symbol BVGSO Parameter Gate-Source Breakdown Voltage Min. 25 Typ. Max. Unit V (4) Pulsed: Pulse duration = 300 s, duty cycle 1.5 %. (5) Pulse width limited by safe operating area PROTECTION FEATURES OF GATE-TO-SOURCE ZENER DIODES The built-in back-to-back Zener diodes have specifically been designed to enhance not only the device's ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be applied from gate to source. In this respect the Zener voltage is appropriate to achieve an efficient and cost-effective intervention to protect the device's integrity. These integrated Zener diodes thus avoid the usage of external components. 3/10 STS1C1S250 Safe Operating Area n-ch Thermal Impedance for Complementary pair Output Characteristics n-ch Transfer Characteristics n-ch Transconductance n-ch Static Drain-source On Resistance n-ch 4/10 STS1C1S250 Gate Charge vs Gate-source Voltage n-ch Capacitance Variations n-ch Norm. Gate Thereshold Voltage vs Temp n-ch Norm. On Resistance vs Temperature n-ch Source-drainDiodeForwardCharacteristicsn-ch Normalized BVDSS vs Temperature n-ch 5/10 STS1C1S250 Safe Operating Area p-ch Thermal Impedance for Complementary pair Output Characteristics p-ch Transfer Characteristics p-ch Transconductance p-ch Static Drain-source On Resistance p-ch 6/10 STS1C1S250 Gate Charge vs Gate-source Voltage p-ch Capacitance Variations p-ch Norm. Gate Thereshold Voltage vs Temp p-ch NormalizedOnResistancevsTemperaturep-ch Source-drainDiodeForwardCharacteristicsp-ch Normalized BVDSS vs Temperature p-ch 7/10 STS1C1S250 Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform Fig. 3: Switching Times Test Circuit For Resistive Load Fig. 4: Gate Charge test Circuit Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times 8/10 STS1C1S250 SO-8 MECHANICAL DATA DIM. MIN. A a1 a2 a3 b b1 C c1 D E e e3 F L M S 3.8 0.4 4.8 5.8 1.27 3.81 4.0 1.27 0.6 8 (max.) 0.14 0.015 5.0 6.2 0.65 0.35 0.19 0.25 0.1 mm TYP. MAX. 1.75 0.25 1.65 0.85 0.48 0.25 0.5 45 (typ.) 0.188 0.228 0.050 0.150 0.157 0.050 0.023 0.196 0.244 0.025 0.013 0.007 0.010 0.003 MIN. inch TYP. MAX. 0.068 0.009 0.064 0.033 0.018 0.010 0.019 0016023 9/10 STS1C1S250 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. (c) The ST logo is a registered trademark of STMicroelectronics (c) 2003 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. (c) http://www.st.com 10/10 |
Price & Availability of STS1C1S250
![]() |
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
[Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |