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| Infineon Technologies preliminary ICE1PD265G Power Factor Controller + Cool- MOS: BoostSET IC for High Power Factor and low THD =IC for sinusoidal line-current consumption =Controller and CoolMOS within one package =P-DSO-16-10 =Power factor achieves nearly 1 = Controls boost converter as active harmonic filter for low THD Start up with very low current consumption =Zero current detector for discontinuous operation mode Output overvoltage protection =Output undervoltage lockout =Internal start up timer =Totem pole output with active shut down =Internal leading edge blanking LEB =Very low comparator and multiplier offsets for universal input applications =High sophisticated amplifier minimizes distortion inteferences caused by MOSFET switching The ICE1PD265G IC controls a boost converter in a way that sinusoidal current is taken from the single phase line supply and stabilized DC voltage is available at the output. CoolMOS and controller are placed together in one package. This active harmonic filter limits the harmonic currents resulting from the capacitor pulsed charge currents during rectification. The power factor which descibes the ratio between active and apparent power is almost one. Line voltage fluctuations can be compensated very efficiently AC RF-Filter and Rectifier DC Output Voltage Controller ICE CoolMOS 1PD265G GND Type ICE1PD265G Ordering Code Package P-DSO-16-10 Infineon Tech PCI Group 10.09.01 1 Infineon Technologies preliminary ICE1PD265G Pin Connections Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Symbol GND VSENSE VAOUT MULTIN n.c. DRAIN DRAIN DRAIN DRAIN DRAIN DRAIN n.c. ISENSE VCC DETIN GND Current sense input + Source Positive voltage supply Zero current detector input Ground Do not touch DRAIN pins on application board: 650V Function Ground Voltage amplifier inverting input Voltage amplifier output Multiplier input 3 VAOUT 1 GND 2 VSENSE P-DSO-16-10 16 GND 15 DETIN 14 VCC 13 ISENSE 12 n.c. 11 DRAIN 10 DRAIN 9 DRAIN 650V Drain 650V Drain 650V Drain 650V Drain 650V Drain 650V Drain 4 MULTIN 5 n.c. 6 DRAIN 7 DRAIN 8 DRAIN Pin Description Pin1,16 GND (Ground) The GND pins are internally connected via the lead frame Pin 2 VSENSE (voltage amplifier inverting input) VSENSE is connected via a resistive divider to the boost converter output. With a capacitor connected to VAOUT the internal error amplifier acts as an integrator. Pin 3 VAOUT (voltage amplifier output) VAOUT is connected internally to the first multiplier input. To prevent overshoot the input voltage is clamped internally at 5V. Input voltage less then 2.2V shuts the gate driver down. If the current flowing into this pin is exceeding an internal threshold the multiplier output voltage is reduced to prevent the MOSFET from overvoltage damage. Pin 4 MULTIN (multipier input) MULTIN is the second multiplier input and is connected via a resistive divider to the rectifier output voltage. Pin 5, 12 not connected Pin 6,7,8,9,10,11 DRAIN (drain connection of internal CoolMOS) The DRAIN pins are internally connected via the leadframe. Be aware of 650V input voltage! Infineon Tech PCI Group 10.09.01 2 Infineon Technologies preliminary ICE1PD265G Pin 13 ISENSE (current sense input and CoolMOS source) Controller current sense input and CoolMOS source are internaly connected via bonds. ISENSE should be connected to an external sense resistor controlling the CoolMOS source current. The input is internally clamped at -0.3V to prevent negative input voltage interaction. A leading edge blanking circuitry suppresses voltage spiks when turning the MOSFET on. Pin 14 Vcc (Positive voltage supply) If Vcc exceeds the turn-on threshold the IC is switched on. When Vcc falls below the turn-off threshold it is switched off and power consumption is very low. An auxilliary winding is charging a capacitor which provides the supply current. A second 100nF ceramic capacitor should be added to Vcc to absorbe supply current spikes required to charge the MOSFET gate capacitance. Pin 15 DETIN (Zero current detector input) DETIN is connected to an auxiliary winding monitoring the zero crossing of the inductor current. Block Diagram VCC GND DETIN DRAIN 20V + 10V 12.5V - clamp detin Reference Voltage 1.0 V + UVLO Detector 1.5 V- Restart Timer tres=150 us Cool MOS 0.2V - Enable + 2.2V - tdVA=2us Inhibit time delay RS Flip-Flop 10 Inhibit + Gate Drive 2.5V + Voltage Amp - Multiplier multout 1V OVR tdsd=70n s Current Comp + + - uvlo active shut down 10p 20k tLEB=150ns clamp VA LEB VSENSE VAOUT MULTIN ISENSE Infineon Tech PCI Group 10.09.01 3 Infineon Technologies preliminary ICE1PD265G Functional Description Introduction Conventional electronic ballasts and switching power supplies are designed with a bridge rectifier and a bulk capacitor. Their disadvantage is that the circuit draws power from the line when the instantaneous AC voltage exceeds the capacitors voltage. This occurs near the line voltage peak and causes a high charge current spike with following characteristics: The apparent power is higher than the real power that means low power factor condition, the current spikes are non sinusoidal with a high content of harmonics causing line noise, the rectified voltage depends on load condition and requires a large bulk capacitor, special efforts in noise suppression are necessary. With the ICE1PD265G preconverter a sinusoidal current is achieved which varies in direct instantaneous proportional to the input voltage half sine wave and so provides a power factor near 1. This is due to the appearence of almost any complex load like a resistive one at the AC line. The harmonic distortions are reduced and comply with the IEC555 standard requirements. IC Description The ICE1PD265G contains a wide bandwidth voltage amplifier used in a feedback loop, an overvoltage regulator, an one quadrant multiplier with a wide linear operating range, a current sense comparator, a zero current detector, a PWM and logic circuitry, a totem-pole MOSFET driver, an internal trimmed voltage reference, a restart timer, an undervoltage lockout circuitry and last not least a CoolMOS transistor. Voltage Amplifier With an external capacitor between VSENSE and VAOUT the voltage amplifier forms an integrator. The integrator monitors the average output voltage over several line cycles. Typically the integrators bandwidth is set below 20 Hz in order to suppress the 100 Hz ripple of the rectified line voltage. The voltage amplifier is internally compensated and has a gain bandwidth of 3 MHz and a phase margin of 80 degrees. The non-inverting input is biased internally at 2.5V. The output is directly connected to the multiplier input. The gate drive is disabled when VSENSE voltage is less than 0.2 V or VAOUT voltage is less than 2.2 V. If the MOSFET is placed nearby the controller switching inteferences have to be taken into account. The output of the voltage amplifier is designed in a way to minimize these inteferences. Overvoltage Regulator Because of the integrators low bandwidth fast changes of the output voltage can't be regulated whithin an adequate time. Fast output changes occure during initial start-up, sudden load removal, or output arcing. While the integrators differential input voltage remains zero during this fast changes a peak current is flowing through the external capacitor into pin VAOUT. If this current exceeds an internal defined margin the overvoltage regulator circuitry reduces the multiplier output voltage. As a result the on time of the MOSFET is reduced. Infineon Tech PCI Group 10.09.01 4 Infineon Technologies preliminary ICE1PD265G Multiplier The one quadrant multiplier regulates the gate driver with respect of the DC output voltage and the AC half wave rectified input voltage. Both inputs are designed to achieve good linearity over a wide dynamic range to represent an AC line free from distortion. Special efforts are made to assure universal line applications with respect to a 90 to 270 V AC range. The multiplier output is internally clamped at 1.0V. So the MOSFET is protected against critical operating during start up. Current sense comparator, LEB and RS Flip-Flop An external sense resistor transferes the source current of the MOSFET into a sense voltage.The multiplier output voltage is compared with this sense voltage. To protect the current comparator input from negative pulses a current source is inserted which sends current out of the ISENSE pin every time when ISENSE is falling below ground potential. The switch-on current peak of the MOSFET is blanked out via a resistor-capacitor circuit with a blanking time of typically 220ns. Therefore better THD is achieved at low load conditions. The RS Flip-Flop ensures that only one single switch-on and switch-off pulse appears at the gate drive output during a given cycle (double pulse suppression). Zero Current Detector The zero current detector senses the inductor current via an auxiliary winding and ensures that the next on-time of the MOSFET is initiated immediately when the inductor current has reached zero. This diminishes the revers recovery losses of the boost converter diode. The MOSFET is switched off when the voltage drop of the shunt resistor reaches the voltage level of the multipler output. So the boost current waveform has a triangular shape and there are no deadtime gaps between the cycles. This leads to a continuous AC line current limiting the peak current to twice of the average current. To prevent false tripping the zero current detector is designed as a Schmitt-Trigger with a hysteresis of 0.5V. An internal 5V clamp protects the input from overvoltage breadkdown, a 0.6V clamp prevents substrate injection. An external resistor has to be used in series with the auxiliary winding to limit the current through the clamps. Restart Timer If the MOS is off for more than 150us a restart impulse is generated by the restart timer. Infineon Tech PCI Group 10.09.01 5 Infineon Technologies preliminary ICE1PD265G Undervoltage Lockout An undervoltage lockout circuitry switches the IC on when Vcc reaches the upper threshold VCCH and switches the IC off when Vcc is falling below the lower threshold VCCL. During start up the supply current is less then 100uA. An internal voltage clamp has been added to protect the IC from Vcc overvoltage condition. When using this clamp special care must be taken on power dissipation. Start up current is provided by an external start up resistor which is connected from the AC line to the input supply voltage Vcc and a storage capacitor which is connected from Vcc to ground. Be aware that this capacitor is discharged befor the IC is plugged into the application board. Otherwise the IC can be destroyed due to the high capacitor voltage. Bootstrap power supply is created with the previous mentioned auxiliary winding and a diode (see application circuit). CoolMOS The CoolMOS is designed for very low RDSon=to reduce power dissipation. Infineon Tech PCI Group 10.09.01 6 Infineon Technologies preliminary ICE1PD265G Signal Diagrams IVAOUT IOVR DETIN DRAIN LEB VISENSE multout Icoil Infineon Tech PCI Group 10.09.01 7 Infineon Technologies preliminary ICE1PD265G Absolute maximum ratings Parameter Supply + Zener Current Supply Voltage Voltage at Pin 2,4,13 Current into Pin 3 IVAOUT -10 Current into Pin 15 Voltage at Pin 6- 11 Continuous Drain Current Avalanche Energy ESD Protection Storage Temperature Operating Junction Temperature Thermal Resistance Junction-Ambient Tstg TJ RthJA -50 -25 IDETIN -10 VDRAIN ID EAr 650 3.2 2 0.2 2000 150 150 120 A A mJ V C C K/W P-DSO-16-10 10 Symbol Icc+Iz VCC Min -0.3 -0.3 Max 20 Vz 6.5 30 Unit mA V V mA mA mA mA Remark Vz=Zener Voltage Icc+Iz=20mA VAOUT=4V,VSENSE=2.8V VAOUT=0V,VSENSE=2.3V t<1ms DETIN > 6V DETIN< 0.4V TJ=115C TC=25C TC=100C repetitive MIL STD 883C method 3015.6, 100pF,1500 Infineon Tech PCI Group 10.09.01 8 Infineon Technologies preliminary ICE1PD265G Characteristics Unless otherwise stated, -40C Zener Voltage Start-up supply current Operating supply current Vcc Turn-ON threshold Vcc Turn-OFF threshold Vcc Hysteresis Symbol min. typ. max. Unit Test Condition Vz ICCL ICCH VCC ON VCC OFF VCCHY 18 20 20 4 22 100 6 13 10.5 V uA mA V V Icc+Iz=18mA Vcc=10V Output low 12 9.5 12.5 10 2.5 Voltage Amplifier Voltage feedback Input Threshold Line regulation Open Loop Voltage Gain1) Unity Gain Bandwidth1) Phase Margin1) Bias current VSENSE Enable Threshold Inhibit Threshold Voltage Inhibit Time Delay Output Current Source Output Current Sink Upper Clamp Voltage Lower Clamp Voltage VFB VFBLR GV BW M IBVSENSE VVSENSEE VVAOUTI tdVA IVAOUTH IVAOUTL VVAOUTH VVAOUTL -1.0 2.45 2.5 2 100 5 80 -0.3 0.2 2.2 3 -6 30 5.4 1.1 2.55 5 V mV dB MHz Degr uA V V us mA mA V V VISENSE= -0.1V VISENSE= -0.1V VAOUT=0V VSENSE=2.3V,t<1ms VAOUT=4V VSENSE=2.8V, t<1ms VSENSE=2.3V, I= -0.2mA VSENSE=2.8V, I=0.5mA Pin1 connected with Pin2 VCC=12V to 16V Overvoltage Regulator Threshold Current IOVR 35 40 45 uA Tj=25C 1) not tested, guaranteed by design Infineon Tech PCI Group 10.09.01 9 Infineon Technologies preliminary ICE1PD265G Parameter Current Comparator Input Bias Current Input Offset Voltage Symbol min. typ. max. Unit Test Condition IBISENSE VISENSEO VISENSEO -1 150 20 0.95 1.0 0.05 100 220 1.05 uA mV mV V V ns ns IOVR=50uA VMULTIN=0V, VAOUT=2.4V VMULTIN=0V, VAOUT>2.8V Max Threshold Voltage Threshold at OVR Shut Down Delay Leading Edge Blanking VISENSEM VISENOVR tdISG tLEB Detector Upper threshold voltage Lower threshold voltage Hysteresis Input current Input clamp voltage High state Low state VDETINU VDETINL VDETINHY IBDETIN VDETINHC VDETINLC -1 5 0.5 1.5 1 0.5 V V V uA IDETIN=5mA IDETIN=-5mA Multiplier Input bias current Dynamic voltage range MULTIN Dynamic voltage range VAOUT Multiplier Gain IBMULTIN VMULTIN -1 0 to 4 VFB to VFB+1. 5 uA V VVAOUT=2.75V VMULTIN=1V V V VVAOUT<3V VVAOUT>3.5V VVAOUT Klow Khigh 0.18 0.56 Restart Timer restart time tRES 150 us Infineon Tech PCI Group 10.09.01 10 Infineon Technologies preliminary ICE1PD265G Parameter CoolMOS Drain source breakdown voltage Drain source on-resistance Zero gate voltage drain current Output capacitance 1) Rise time Fall time Symbol min. typ. max. Unit Test Condition VBRDSS RDSon 600 650 1.1 0.5 150 30 50 1.4 3.8 1 70 V V Ohm Ohm uA uA pF ns ns TJ=25C TJ=115C Tj=25C Tj=150C UGS=0V, Tj=25 UGS=0V, Tj=150 VDS=25V, f=1MHz IDSS COSS trise tfall 1) not tested, guaranteed by design Infineon Tech PCI Group 10.09.01 11 Infineon Technologies preliminary ICE1PD265G Electrical Diagrams Diagram 1: Icc versus Vcc 5 4,5 13 4 3,5 3 2,5 2 1,5 1 8 0,5 0 0 5 10 Vcc/V 15 20 7 -40 0 40 80 120 160 VCC OFF VCC ON 12 VCC ON 14 Diagram 2: VCCON/OFF versus Temperature Vcc / V Icc / mA 11 10 VCC OFF 9 Tj / C Diagram 3: Iccl versus Vcc 50 45 40 35 30 25 20 15 10 5 0 0 2 4 6 8 10 12 14 16 ICCL / uA 50 45 40 35 30 25 20 15 10 5 0 -40 Diagram 4: ICCL versus Temperature, VCC=9V Iccl / uA 0 40 Tj / C 80 120 160 Vcc / V Infineon Tech PCI Group 10.09.01 12 Infineon Technologies preliminary ICE1PD265G Diagram 5: VFB vers. Temperature (pin1 connected to pin2) 2,55 2,54 2,53 2,52 80 2,51 VFB / V 100 GV/dB 120 Diagram 6: Voltage Amplifier Open loop gain and Phase Phi/deg 180 160 Gv 140 120 100 2,5 2,49 2,48 2,47 60 Phi 40 80 60 40 20 20 0 0,01 0 1000 10000 2,46 2,45 -40 0 40 80 120 160 Tj / C 0,1 1 10 f/kHz 100 Diagram 7: Overvoltage Regulator VISENSE vers. Threshold Voltage 1,2 VVAOUT = 3.5V VMULTIN = 3.0V 1 43 42 0,8 VISENSE / V 41 IOVR/uA 0,6 40 39 0,4 38 37 0,2 36 0 35 37 39 41 43 45 Iovp / uA 35 -40 44 45 Diagram 8: IOVR versus Temperature 0 40 Tj/C 80 120 160 Infineon Tech PCI Group 10.09.01 13 Infineon Technologies preliminary ICE1PD265G Diagram 9: max Threshold Voltage VISENSEM vs. Temperature 1,05 1,04 Diagram 10: Leading edge blanking (min on-time) vs. Temp. 300 250 1,03 1,02 VISENSEM/V LEB / ns 1,01 1 0,99 100 0,98 0,97 0,96 0,95 -40 0 40 Tj/C 80 120 160 0 -40 0 40 Tj / C 80 120 160 50 200 150 Diagram 11: Current Sense Threshold VISENSE versus VMULTIN 1 0,9 0,8 0,7 3.5V 4.5V 4.0V 1 0,9 0,8 0,7 Diagram 12: Current sense threshold VISENSE versus VVAOUT Vmultin=4.0 3.0 2.0 1.5 VISENSE / V 3.25V 0,5 0,4 0,3 0,2 0,1 0 0 1 2 3 4 VVAOUT=2.75V 3.0V VISENSE / V 0,6 0,6 0,5 0,4 0,3 0,2 0,1 0 2,5 3 3,5 4 4,5 0.25 1.0 0.5 VMULTIN / V VVAOUT / V Infineon Tech PCI Group 10.09.01 14 Infineon Technologies preliminary ICE1PD265G Diagram 13: Restart time versus temperature 250 800 Diagram 14: VBRDSS vs. Temperature 700 200 600 VBRDSS / V -40 0 40 Tj / C 80 120 160 150 trst / us 500 400 100 300 200 50 100 0 0 -40 0 40 Tj/C 80 120 160 3 Diagram 15: RDSon vs. Temperature 2,5 2 RDSon / Ohm 1,5 1 0,5 0 -40 0 40 Tj/C 80 120 160 Infineon Tech PCI Group 10.09.01 15 Infineon Technologies preliminary ICE1PD265G Application circuit: RDSON=1.1 Ohm Pout=80W, Vin= 180 - 270V AC Pout=34W, Vin= 90 - 270 V AC RF filter Vin and 90-270V rectifier AC D5 1N4937 Vout R12 270 R9 33k R8 100k D6 MUR115 C10 47uF C9 100n 16 15 14 13 12 11 10 9 C8 47uF ICE1PD265 1 2 3 C1 1u 4 5 6 7 8 R4 R6 R11 R7 5.1k C2 1u R7 C4 10n R5 GND Infineon Tech PCI Group 10.09.01 16 |
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