 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| DM7442A BCD to Decimal Decoder August 1986 Revised February 2000 DM7442A BCD to Decimal Decoder General Description These BCD-to-decimal decoders consist of eight inverters and ten, four-input NAND gates. The inverters are connected in pairs to make BCD input data available for decoding by the NAND gates. Full decoding of input logic ensures that all outputs remain off for all invalid (10-15) input conditions. Features s Diode clamped inputs s Also for application as 4-line-to-16-line decoders; 3-line-to-8-line decoders s All outputs are high for invalid input conditions s Typical power dissipation 140 mW s Typical propagation delay 17 ns Ordering Code: Order Number DM7442AN Package Number N16E Package Description 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Connection Diagram (c) 2000 Fairchild Semiconductor Corporation DS006516 www.fairchildsemi.com DM7442A Function Table No. D 0 1 2 3 4 5 6 7 8 9 I N V A L I D H = HIGH Level L = LOW Level BCD Input C L L L L H H H H L L L L H H H H B L L H H L L H H L L H H L L H H A L H L H L H L H L H L H L H L H 0 L H H H H H H H H H H H H H H H 1 H L H H H H H H H H H H H H H H 2 H H L H H H H H H H H H H H H H 3 H H H L H H H H H H H H H H H H L L L L L L L L H H H H H H H H Decimal Output 4 H H H H L H H H H H H H H H H H 5 H H H H H L H H H H H H H H H H 6 H H H H H H L H H H H H H H H H 7 H H H H H H H L H H H H H H H H 8 H H H H H H H H L H H H H H H H 9 H H H H H H H H H L H H H H H H Logic Diagram www.fairchildsemi.com 2 DM7442A Absolute Maximum Ratings(Note 1) Supply Voltage Input Voltage Operating Free Air Temperature Range Storage Temperature Range 7V 5.5V 0C to +70C -65C to +150C Note 1: The "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The "Recommended Operating Conditions" table will define the conditions for actual device operation. Recommended Operating Conditions Symbol VCC VIH VIL IOH IOL TA Parameter Supply Voltage HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Current LOW Level Output Current Free Air Operating Temperature 0 Min 4.75 2 0.8 -0.8 16 70 Nom 5 Max 5.25 Units V V V mA mA C Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted) Symbol VI VOH VOL II IIH IIL IOS ICC Parameter Input Clamp Voltage HIGH Level Output Voltage LOW Level Output Voltage Input Current @ Max Input Voltage HIGH Level Input Current LOW Level Input Current Short Circuit Output Current Supply Current Conditions VCC = Min, II = -12 mA VCC = Min, IOH = Max VIL = Max, VIH = Min VCC = Min, IOL = Max VIH = Min, VIL = Max VCC = Max, VI = 5.5V VCC = Max, VI = 2.4V VCC = Max, VI = 0.4V VCC = Max (Note 3) VCC = Max (Note 4) -18 28 1 40 -1.6 -55 56 mA A mA mA mA 0.2 0.4 V 2.4 3.4 Min Typ (Note 2) Max -1.5 Units V V Note 2: All typicals are at VCC = 5V, TA = 25C. Note 3: Not more than one output should be shorted at a time. Note 4: ICC is measured with all outputs open and all inputs grounded. Switching Characteristics at VCC = 5V and TA = 25C Symbol tPHL Parameter Propagation Delay Time HIGH-to-LOW Level Output from A, B, C or D through 2 Levels of Logic tPHL Propagation Delay Time HIGH-to-LOW Level Output from A, B, C or D through 3 Levels of Logic tPLH Propagation Delay Time LOW-to-HIGH Level Output from A, B, C or D through 2 Levels of Logic tPLH Propagation Delay Time LOW-to-HIGH Level Output from A, B, C or D through 3 Levels of Logic 30 ns 25 ns 30 ns CL = 15 pF RL = 400 25 ns Conditions Min Max Units 3 www.fairchildsemi.com DM7442A BCD to Decimal Decoder Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N16E Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 4 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com |
Price & Availability of DM7442
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |