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MITSUBISHI
M56693FP/GP
Bi-CMOS & DMOS 32BIT SERIAL-INPUT LATCHED DRIVER
DESCRIPTION
The M56693 is a semiconductor integrated circuit that has a builtin, 32-bit shift register and a latch of CMOS structure with serial input and serial/parallel output, and a 32-bit totem-pole-type parallel output driver of high pressure proof DMOS structure. Employed are BI-CMOS and high pressure proof DMOS processing technology.
PIN CONFIGURATION (TOP VIEW)
33 HVO22
32 HVO21
31 HVO20
30 HVO19
29 HVO18
28 HVO17
27 HVO16
26 HVO15
25 HVO14
24 HVO13 27 HVO13
FEATURES
q Serial input-serial/parallel output q Cascade connections possible through serial output q Latch circuit included for each stage q Driver supply voltage: VH=120V q Operating temperature: -20 - 75C
APPLICATION
Vacuum Fluorescent Display ANODE DRIVER
HVO23 HVO24 HVO25 HVO26 HVO27 HVO28 HVO29 HVO30 HVO31 HVO32 PGND
23 HVO12 22 HVO11 21 HVO10 20 HVO 9 19 HVO 8 18 HVO 7 17 HVO 6 16 HVO 5 15 HVO 4 14 HVO 3 13 HVO 2 12 HVO 1 26 HVO12 25 N.C 24 N.C 23 HVO11 22 HVO10 21 HVO 9 20 HVO 8 19 HVO 7 18 N.C 17 HVO 6 16 HVO 5 15 HVO 4 14 HVO 3 13 HVO 2 11
34 35 36 37 38 39 40 41 42 43 44
M56693FP
FUNCTION
The M56693 comprises a 32-bit D type flip-flop with a 32 latches connected to its output. In accordance with truth table 1, inputting data to SIN and clock pulse to CLK allows SIN signal to be put into the internal shift register when the clock changes from "H" to "L", and simultaneously shift register data to be shifted sequentially. Serial output SOUT is used by connecting to the next stage
Outline 44P6N-A (FP)
36 HVO22
35 HVO21
34 HVO20
33 HVO19
32 HVO18
31 HVO17
30 HVO16
29 HVO15
M56693 SIN when more than one M56693 is used to expand bits in the series. In accordance with truth table 2, parallel output allows the latch to pass data through if LAT input is turned to "H", and data to be retained if LAT is turned to "L". Driver output HVOn allows data from the latch to be output if BLK input is turned to "L", and "L" to be output if BLK input is turned to "H", irrespective of data from the latch.
N.C N.C HVO23 HVO24 HVO25 HVO26 HVO27 HVO28 HVO29 HVO30 HVO31 HVO32
37 38 39 40 41 42 43 44 45 46 47 48
M56693GP
28 HVO14
10
CLK 6 LAT 7 BLK 8 SIN 9 VH 10 PGND 11 CLK LAT BLK SIN VH PGND
1
2
3
4
VH SOUT VDD N.C LGND
5
PGND 1 VH 2 SOUT 3 VDD 4 LGND 5
Outline 48P6D-A (GP)
N.C: no connection
HVO 1 12
6
7
8
9
MITSUBISHI
M56693FP/GP
Bi-CMOS & DMOS 32BIT SERIAL-INPUT LATCHED DRIVER
BLOCK DIAGRAM (Note : Pin No. in paretheses are of M56693GP)
HVO 1
(12)
Output protect circuit
HVO 2
(13) 13
HVO 3
(14) 14
HVO30
41 (46)
HVO31
42 (47)
HVO32
43 (48) 1 10
12
VH
(2)(10)
VDD
(4)
3
11
PGND
44 (1)(11) 8
BLK
(8)
Q LD LAT
(7) 7
Q LD
Q LD
Q LD
Q LD
Q LD
5
LGND
(5)
SIN
(9)
9
DQ T
DQ T
DQ T
DQ T
DQ T
DQ T
2 SOUT (3) 4
CLK
(6)
6
N.C
(18)(24)(25) (37)(38)
TRUTH TABLE Truth table 1. Shift register section
CLK H or L Shift register operation DATA is shifted. No changes.
Truth table 2. Latch and driver sections
Dn X H L X LAT X H H L BLK H L L L HVOn Output all "L" H L Latch's data output. Dn=nth bit DFF retention data HVOn=nth bit driver output L="L" level H="H" level X="L" level or "H" level
MITSUBISHI
M56693FP/GP
Bi-CMOS & DMOS 32BIT SERIAL-INPUT LATCHED DRIVER
PIN FUNCTION DESCRIPTION
Pin name VDD LGND VH PGND CLK SIN SOUT LAT BLK HVO1 - 32 Function Logic stage supply voltage Logic stage ground Output stage supply voltage Output stage ground Clock input for the internal shift resister. The data enter the internal shift resisters and the data in the shift registers will be shifted in order by High to Low change of the clock. Serial data input Serial data output Latch input. When the LATCH is set to "H", the data in the shift resister will enter the each latch circuit. When the LATCH input is set to "L", the data will be held. Enable input for output control. When the BLK input is set to "L", data in the latch circuit will appear at outputs. When the BLK input is set to "H", all outputs will be set to "L". Output driver (push-pull)
ABSOLUTE MAXIMUM RATINGS (Ta=25C, unless otherwise noted)
Symbol VDD VH VI VO VHVO Pd Tstg Parameter Logic stage supply voltage Output stage supply voltage Logic inputs voltage Logic outputs voltage Outputs voltage Power dissipation range Storage temperature range Conditions Ratings -0.3 - 7 -0.3 - 120 -0.3 - VDD+0.3 -0.3 - VDD+0.3 -0.3 - VH 940 -55 - 150 Unit V V V V V mW C
Data output High supply voltage output pin Ta 25C
RECOMMENDED OPERATING CONDITIONS
Symbol VDD VH Topr Parameter Supply voltage Supply voltage Operating temperature Conditions Ratings 4.5 - 5.5 10 - 110 -20 - 75 Unit V V C
ELECTRICAL CHARACTERISTICS (VDD=5V, VH=110V and Ta=25C, unless otherwise noted)
Symbol IDD IH IIH IIL VHVOH VHVOL VOH VOL IHVOH IHVOL VTH VTL Parameter Supply current 1 Supply current 2 "H" input current "L" input current Driver output voltage Logic output voltage "H" output current "L" output current Output protect operating voltage Test conditions No load Output all "L", no load Output all "H", no load VIH=5V VIL = 0V IHVOH = -0.5mA IHVOL = 0.5mA IOH = -0.1mA IOL = 0.1mA High supply voltage output pin High supply voltage output pin Input pin SIN, LAT, CLK BLK 100 4.5 Min. Limits Typ. 1 0 2 0 0 -20 106 0.7 4.95 0.04 -1 1 3.4 3.1 Max. 2 50 4 2 -2 -100 2 0.4 -3 3 Unit mA A mA A A A V V mA mA V V
MITSUBISHI
M56693FP/GP
Bi-CMOS & DMOS 32BIT SERIAL-INPUT LATCHED DRIVER
SWITCHING CHARACTERISTICS (VDD=5V, VH=110V and Ta=25C, unless otherwise noted)
Symbol fCLK tPLH(SO) tPHL(SO) tPLH(OUT) tPHL(OUT) trout tfout Parameter Clock frequency Logic output propagation time Driver output propagation time Driver output rise and fall time Test conditions Duty = 45 - 55% CL = 15pF 120 100 1 0.16 1.3 0.35 Min. Limits Typ. Max. 8 300 300 2 1 2.5 2 Unit MHz ns ns s s s s
RO = 220K CO = 50pF
TEST CIRCUIT
input VDD VH (1) Pulse generator characteristics tr20ns tf20ns (2) Capacitance CL includes connection floating capacitance and probe input capacitance. : RO=220K : CO=50pF
SOUT PG DUT CL HVOn 50
CO
RO
TIMING WAVEFORM
1/fmax CLK
50% 50% 50%
SIN
50%
50%
tsu tfso SOUT
90% 50% 10% 10%
th trso
90% 50%
tPHL(SO) tPLH(SO) BLK
50%
50%
trOUT HVOn
10% 90% 50%
tfOUT
90% 50% 10%
tPLH(OUT)
tPHL(OUT)
MITSUBISHI
M56693FP/GP
Bi-CMOS & DMOS 32BIT SERIAL-INPUT LATCHED DRIVER
TYPICAL CHARACTERISTICS
Thermal derating
1.0 0.94 IOH(mA) Power dissipation Pd (W) 10
Driver output VON-IOH
Ta=+75C
8
Ta=+25C Ta=-20C
0.5
"H" output current
6
4
2
0
0 0 25 50 75 100 0 2 4 6 8 10 Temperature Ta (C) "H" output voltage VON (V)
Duty cycle vs Permissible output current
10 9 1 - 13 14 16 10 9
Duty cycle vs Permissible output current
1-8 9
IOH (mA)
7 6 5 4 3 2 1 0 0 20 40 60 80 100 24 32
IOH (mA)
8
8 7 6 5 4 3 2 1 0 0 20 40 60 80 100 24 32 16
Output current
Duty cycle (%) Note * Ta=25C * Repeated frequency >100Hz * Figure in the circle represents the number of concurrently operating output circuits. * Current value denotes a numerical value per circuit.
Output current
Duty cycle (%) Note * Ta=75C * Repeated frequency >100Hz * Figure in the circle represents the number of concurrently operating output circuits. * Current value denotes a numerical value per circuit.
Note 1. VDD=5V and VH=110V, unless otherwise noted 2. Thermal derating characteristics represent those of an individual IC unit. 3. Allowable duty cycle output current characteristics represent that when a standard substrate is mounted. (Standard substrate: 70x70x1.6mm glass epoxy)

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