View ICS951411_291541.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Integrated Circuit Systems, Inc.
ICS951411
System Clock Chip for ATI RS400 P4TM-based Systems
Recommended Application: ATI RS400 systems using Intel P4TM processors Output Features: * 6 - Pairs of SRC/PCI-Express clocks * 2 - Pairs of ATIG (SRC/PCI Express*) clocks * 3 - Pairs of Intel P4 clocks * 3 - 14.318 MHz REF clocks * 1 - 48MHz USB clock * 1 - 33 MHz PCI clock seed Key Specifications: * CPU outputs cycle-cycle jitter < 85ps * SRC output cycle-cycle jitter <125ps * PCI outputs cycle-cycle jitter < 250ps * +/- 300ppm frequency accuracy on CPU & SRC clocks Features/Benefits: * 2- Programmable Clock Request pins for SRC clocks * Supports CK410 or CK409 frequency table mapping * Spread Spectrum for EMI reduction * Outputs may be disabled via SMBus * External crystal load capacitors for maximum frequency accuracy
Functionality - (CK410# = 0) CPU SRC PCI FS_C1 FS_B1 FS_A1 MHz MHz MHz 0 266.66 100.00 33.33 0 1 133.33 100.00 33.33 0 0 200.00 100.00 33.33 1 1 166.66 100.00 33.33 0 333.33 100.00 33.33 0 1 100.00 100.00 33.33 1 0 400.00 100.00 33.33 1 RESERVED 1 Functionality - (CK410# = 1) FS_C1 CPU Byte6 FS_B1 FS_A1 MHz bit5 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 1 100.00 200.00 133.33 166.67 200.00 400.00 266.67 333.33 SRC MHz 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 PCI MHz 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33
Pin Configuration
REF MHz 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 USB MHz 48.000 48.000 48.000 48.000 48.000 48.000 48.000 48.000
0
1
14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318
48.000 48.000 48.000 48.000 48.000 48.000 48.000 48.000
1. FS_C, FS_B and FS_A are low-threshold inputs. Please see the VIL_FS and VIH_FS specifications in the Input/Supply/Common Output Parameters Table for correct values.
Note: Pins preceeded by '**' have a 120 Kohm Internal Pull Down resistor Pins preceeded by '*' have a 120 Kohm Internal Pull Up resistor
56-pin SSOP & TSSOP
0891E--03/07/05
*Other names and brands may be claimed as the property of others.
ICS951411
REF MHz
USB MHz
X1 X2 VDD48 USB_48MHz GND VTT_PWRGD#/PD SCLK SDATA **FS_C **CLKREQA# **CLKREQB# SRCCLKT7 SRCCLKC7 VDDSRC GNDSRC SRCCLKT6 SRCCLKC6 SRCCLKT5 SRCCLKC5 GNDSRC VDDSRC SRCCLKT4 SRCCLKC4 SRCCLKT3 SRCCLKC3 GNDSRC ATIGCLKT1 ATIGCLKC1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
VDDREF GND **FS_A/REF0 **FS_B/REF1 **TEST_SEL/REF2 VDDPCI **CK410#/PCICLK0 GNDPCI *CPU_STOP# CPUCLKT0 CPUCLKC0 VDDCPU GNDCPU CPUCLKT1 CPUCLKC1 CPUCLKT2_ITP CPUCLKC2_ITP VDDA GNDA IREF GNDSRC VDDSRC SRCCLKT0 SRCCLKC0 VDDATI GNDATI ATIGCLKT0 ATIGCLKC0
Integrated Circuit Systems, Inc.
ICS951411
Pin Description
PIN # 1 2 3 4 5 6 7 8 9 10 PIN NAME X1 X2 VDD48 USB_48MHz GND VTT_PWRGD#/PD SCLK SDATA **FS_C **CLKREQA# PIN TYPE IN OUT PWR OUT PWR IN IN I/O IN IN DESCRIPTION Crystal input, Nominally 14.318MHz. Crystal output, Nominally 14.318MHz Power pin for the 48MHz output.3.3V 48.00MHz USB clock Ground pin. Vtt_PwrGd# is an active low input used to determine when latched inputs are ready to be sampled. PD is an asynchronous active high input pin used to put the device into a low power state. The internal clocks, PLLs and the crystal oscillator are stopped. Clock pin of SMBus circuitry, 5V tolerant. Data pin for SMBus circuitry, 5V tolerant. Frequency select latch input pin Output enable for PCI Express (SRC) outputs. SMBus selects which outputs are controlled. 0 = enabled, 1 = tri-stated Output enable for PCI Express (SRC) outputs. SMBus selects which outputs are controlled. 0 = enabled, 1 = tri-stated True clock of differential SRC clock pair. Complement clock of differential SRC clock pair. Supply for SRC clocks, 3.3V nominal Ground pin for the SRC outputs True clock of differential SRC clock pair. Complement clock of differential SRC clock pair. True clock of differential SRC clock pair. Complement clock of differential SRC clock pair. Ground pin for the SRC outputs Supply for SRC clocks, 3.3V nominal True clock of differential SRC clock pair. Complement clock of differential SRC clock pair. True clock of differential SRC clock pair. Complement clock of differential SRC clock pair. Ground pin for the SRC outputs True clock of differential SRC clock pair. Complementary clock of differential SRC clock pair.
11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
**CLKREQB# SRCCLKT7 SRCCLKC7 VDDSRC GNDSRC SRCCLKT6 SRCCLKC6 SRCCLKT5 SRCCLKC5 GNDSRC VDDSRC SRCCLKT4 SRCCLKC4 SRCCLKT3 SRCCLKC3 GNDSRC ATIGCLKT1 ATIGCLKC1
IN OUT OUT PWR PWR OUT OUT OUT OUT PWR PWR OUT OUT OUT OUT PWR OUT OUT
0891E--03/07/05
2
Integrated Circuit Systems, Inc.
ICS951411
Pin Description (Continued)
PIN # 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 PIN NAME ATIGCLKC0 ATIGCLKT0 GNDATI VDDATI SRCCLKC0 SRCCLKT0 VDDSRC GNDSRC IREF GNDA VDDA CPUCLKC2_ITP CPUCLKT2_ITP CPUCLKC1 CPUCLKT1 GNDCPU VDDCPU CPUCLKC0 CPUCLKT0 *CPU_STOP# GNDPCI **CK410#/PCICLK0 VDDPCI **TEST_SEL/REF2 **FS_B/REF1 **FS_A/REF0 GND VDDREF PIN TYPE OUT OUT PWR PWR OUT OUT PWR PWR DESCRIPTION Complementary clock of differential SRC clock pair. True clock of differential SRC clock pair. Ground for ATI Gclocks, nominal 3.3V Power supply ATI Gclocks, nominal 3.3V Complement clock of differential SRC clock pair. True clock of differential SRC clock pair. Supply for SRC clocks, 3.3V nominal Ground pin for the SRC outputs
This pin establishes the reference current for the differential current-mode OUT output pairs. This pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the standard value. PWR Ground pin for the PLL core. PWR 3.3V power for the PLL core. Complementary clock of differential pair CPU outputs. These are current mode OUT outputs. External resistors are required for voltage bias. True clock of differential pair CPU outputs. These are current mode outputs. OUT External resistors are required for voltage bias. Complementary clock of differential pair CPU outputs. These are current mode OUT outputs. External resistors are required for voltage bias. True clock of differential pair CPU outputs. These are current mode outputs. OUT External resistors are required for voltage bias. PWR Ground pin for the CPU outputs PWR Supply for CPU clocks, 3.3V nominal Complementary clock of differential pair CPU outputs. These are current mode OUT outputs. External resistors are required for voltage bias. True clock of differential pair CPU outputs. These are current mode outputs. OUT External resistors are required for voltage bias. IN Stops all CPUCLK, except those set to be free running clocks PWR Ground pin for the PCI outputs FS Table select latch input pin / 3.3V PCI clock output. I/O 0 = CK410 FS Table, 1 = CK409 FS Table PWR Power supply for PCI clocks, nominal 3.3V I/O I/O I/O PWR PWR TEST_SEL: latched input to select TEST MODE / 14.318 MHz reference clock. 1 = All outputs are CK410 REF/N test mode 0 = All outputs behave normally. Frequency select latch input pin / 14.318 MHz reference clock. Frequency select latch input pin / 14.318 MHz reference clock. Ground pin. Ref, XTAL power supply, nominal 3.3V
0891E--03/07/05
3
Integrated Circuit Systems, Inc.
ICS951411
General Description
ICS951411 provides a single-chip clocking solution for the ATI RS400-based systems using the latest Intel P4 processors. ICS951411 is driven with a 14.318MHz crystal. It generates CPU outputs up to 400MHz and also provides highly accurate SRC clocks for PCI Express support. Two Clock Request pins are provided for Express-CardTM support.
Block Diagram
REF(2:0)
X1 X2 XTAL OSC. FIXED PLL DIVIDER
USB_48MHz
PCICLK0 ATIGCLK(1:0)
MAIN PLL
DIVIDERS
SRCCLK(7:3,0)
CPUCLK(2:0)
CK410# FS(C:A) CLKREQA# CLKREQB# CPU_STOP# VTT_PWRGD#/PD SDATA SCLK
CONTROL LOGIC
IREF
Power Groups
Pin Number VDD GND 56 55 51 49 45 44 14, 21, 35 15, 20, 26, 36 32 31 39 38 3 5 Description Xtal, REF PCICLK output CPUCLK Outputs SRCCLK outputs ATIGCLK outputs Analog, CPU PLL USB_48MHz output
0891E--03/07/05
4
Integrated Circuit Systems, Inc.
ICS951411
General SMBus serial interface information for the ICS951411 How to Write:
Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = X ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + X -1 (see Note 2) * ICS clock will acknowledge each byte one at a time * Controller (host) sends a Stop bit * * * * * * * *
How to Read:
* * * * * * * * * * * * * * Controller (host) will send start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the data byte count = X ICS clock sends Byte N + X -1 ICS clock sends Byte 0 through byte X (if X(H) was written to byte 8). Controller (host) will need to acknowledge each byte Controllor (host) will send a not acknowledge bit Controller (host) will send a stop bit
Index Block Write Operation
Controller (Host) starT bit T Slave Address D2(H) WR WRite Beginning Byte = N ACK Data Byte Count = X ACK Beginning Byte N ACK X Byte ICS (Slave/Receiver)
Index Block Read Operation
Controller (Host) T starT bit Slave Address D2(H) WR WRite Beginning Byte = N ACK RT Repeat starT Slave Address D3(H) RD ReaD ACK Data Byte Count = X ACK Beginning Byte N ACK X Byte ICS (Slave/Receiver)
ACK
ACK
Byte N + X - 1 ACK P stoP bit
Byte N + X - 1 N P Not acknowledge stoP bit
0891E--03/07/05
5
Integrated Circuit Systems, Inc.
ICS951411
Table1: CPU Frequency Selection Table Bit 4 Bit 3 Bit2 Bit1 Bit0 CPU FS4 CPU FS3 FSC FSB FSA (CK410#) (SS_EN) 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 1 0 0 0 1 1 1 0 1 0 0 0 0 1 0 0 1 0 1 0 1 0 0 1 0 1 1 0 1 1 0 0 0 1 1 0 1 0 1 1 1 0 0 1 1 1 1 1 0 0 0 0 1 0 0 0 1 1 0 0 1 0 1 0 0 1 1 1 0 1 0 0 1 0 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1 0 0 0 1 1 0 0 1 1 1 0 1 0 1 1 0 1 1 1 1 1 0 0 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1
CPU (MHz) 266.6667 133.3333 200.0000 166.6668 333.3335 100.0000 400.0000 266.6667 133.3333 200.0000 166.6668 333.3335 100.0000 400.0000 100.0000 133.3333 200.0000 166.6668 200.0000 266.6667 400.0000 333.3335 100.0000 133.3333 200.0000 166.6668 200.0000 266.6667 400.0000 333.3335
PCI33 (MHz)
Spread %
33.3333 33.3333 33.3333 33.3334 No Spread 33.3334 33.3333 33.3333 Reserved 33.3333 33.3333 33.3333 -0.5% 33.3334 33.3334 33.3333 33.3333 Reserved 33.3333 33.3333 33.3333 33.3334 No Spread 33.3333 33.3333 33.3333 33.3334 33.3333 33.3333 33.3333 33.3334 -0.5% 33.3333 33.3333 33.3333 33.3334
C K 4 1 0
C K 4 0 9
0891E--03/07/05
6
Integrated Circuit Systems, Inc.
ICS951411
Table2: SRC & ATIG Frequency Selection Table SRC FS4 SRC Bit2 Bit1 Bit0 (SS_EN) FS3 FS2 FS1 FS0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 SRC(7:3,0), Spread SRC ATIG(1:0) % OverClock (MHz) 100.00 100.00 100.00 100.00 101.00 101.00 101.00 101.00 102.00 102.00 102.00 102.00 104.00 104.00 104.00 104.00 100.00 100.00 100.00 100.00 101.00 101.00 101.00 101.00 102.00 102.00 102.00 102.00 104.00 104.00 104.00 104.00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0.5% -0.5% -0.5% -0.5% -0.5% -0.5% -0.5% -0.5% -0.5% -0.5% -0.5% -0.5% -0.5% -0.5% -0.5% -0.5% 1.00 1.00 1.00 1.00 1.01 1.01 1.01 1.01 1.02 1.02 1.02 1.02 1.04 1.04 1.04 1.04 1.00 1.00 1.00 1.00 1.01 1.01 1.01 1.01 1.02 1.02 1.02 1.02 1.04 1.04 1.04 1.04
0891E--03/07/05
7
Integrated Circuit Systems, Inc.
ICS951411
SMBus Table: Frequency Select Register Byte 0 Pin # Name Bit 7 FS Source
Control Function Latched Input or SMBus Frequency Select
Type RW
0 Latched Inputs
1 SMBus
PWD 0 0 X Latched 0 Latched Latched Latched
Bit 6 SS_EN Spread Enable RW OFF ON Bit 5 Reserved Reserved RW Reserved Reserved Bit 4 CK410# CPU Freq Select Bit 4 RW Bit 3 CPU FS3 CPU SS_EN RW See Table 1: CPU Bit 2 CPU FS_C CPU Freq Select Bit 2 RW Frequency Selection Table RW Bit 1 CPU FS_B CPU Freq Select Bit 1 Bit 0 CPU FS_A CPU Freq Select Bit 0 RW NOTE: Byte 0 bit 6 and Byte 0 bit 3 must BOTH be '1' to enable spread for the PCI $ CPU clocks. Byte 5 bit 4 must be set to 1 to enable spread for the SRC & ATIGCLKS. SMBus Table: Output Control Register Byte 1 Pin # Name 50 Bit 7 PCICLK0 41,40 Bit 6 CPUCLK2 4 Bit 5 USB_48MHz 54 Bit 4 REF0 53 Bit 3 REF1 52 Bit 2 REF2 47,46 Bit 1 CPUCLK0 43,42 Bit 0 CPUCLK1
Control Function Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable
Type RW RW RW RW RW RW RW RW
0 Disable Disable Disable Disable Disable Disable Disable Disable
1 Enable Enable Enable Enable Enable Enable Enable Enable
PWD 1 1 1 1 1 1 1 1
SMBus Table: CLKREQB# Output Control Register Byte 2 0 Pin # Name Control Function Type CLKREQB# Controls Does not 12,13 Bit 7 REQBSRC7 RW SRC7 control CLKREQB# Controls Does not 16,17 Bit 6 REQBSRC6 RW SRC6 control CLKREQB# Controls Does not 18,19 Bit 5 REQBSRC5 RW SRC5 control CLKREQB# Controls Does not 22,23 Bit 4 REQBSRC4 RW SRC4 control CLKREQB# Controls Does not 24,25 Bit 3 REQBSRC3 RW SRC3 control Bit 2 Reserved Reserved RW Reserved Bit 1 Reserved Reserved RW Reserved CLKREQB# Controls Does not 34,33 Bit 0 REQBSRC0 RW SRC0 control NOTE: CPU0_Stop_En (Byte2, bit 2) only exists in devices with REV ID = 2 or higher
1 Controls Controls Controls Controls Controls Reserved Reserved Controls
PWD 0 0 0 0 0 X X 0
0891E--03/07/05
8
Integrated Circuit Systems, Inc.
ICS951411
SMBus Table: SRCCLK(7:3,0), CLKREQA# Output Control Register Byte 3 Pin # Name Control Function Type SRCCLK7 RW 12,13 Bit 7 Master Output control. RW 16,17 SRCCLK6 Bit 6 Enables or disables 18,19 SRCCLK5 RW Bit 5 output, regardless of 22,23 SRCCLK4 RW Bit 4 CLKREQ# inputs. 24,25 SRCCLK3 RW Bit 3 34,33 SRCCLK0 RW Bit 2 CLKREQA# Controls 24,25 REQASRC3 RW Bit 1 SRC3 CLKREQA# Controls 34,33 REQASRC0 RW Bit 0 SRC0 SMBus Table: SRCCLK(3,0), ATIGCLK Output Control Register Byte 4 Pin # Name Control Function CLKREQA# Controls 12,13 REQASRC7 Bit 7 SRC7 CLKREQA# Controls 16,17 REQASRC6 Bit 6 SRC6 CLKREQA# Controls 18,19 REQASRC5 Bit 5 SRC5 CLKREQA# Controls 22,23 REQASRC4 Bit 4 SRC4 Output Enable 27,28 ATIGCLK1 Bit 3 These outputs cannot be controlled by CLKREQ# 30,29 ATIGCLK0 Bit 2 pins. Bit 1 Bit 0 CPU, SRC, ATIG 4 Differential Output Disable Mode USB_48Str Hi-Z or driven when disabled
0 Disable Disable Disable Disable Disable Disable Does not control Does not control
1 Enable Enable Enable Enable Enable Enable Controls Controls
PWD 1 1 1 1 1 1 0 0
Type RW RW RW RW RW RW RW
0 Does not control Does not control Does not control Does not control Disabled Disabled Driven 1X
1 Controls Controls Controls Controls Enabled Enabled Hi-Z 2X
PWD 0 0 0 0 1 1 0 1
48MHz Strength Control RW
Note: Do NOT simultaneously select CLKREQA# and CLKREQB# to control an SRC output. Behavior of the device is undefined under these conditions. SMBus Table: Output Drive and ATIG Frequency Control Register Pin # Name Control Function Type Byte 5 0 1 52 REF2Str REF2 Strength Control RW 1X 2X Bit 7 Free-Run Stoppable 41,40 0 = CPU is free-run CPU2_Stop_En RW Bit 6 Free-Run Stoppable 43,42 CPU1_Stop_En 1 = CPU is stopped by RW Bit 5 SRCFS4 Freq Select Bit 4 RW Bit 4 (SS_EN) (SS_EN) See Table 2 SRC SRCFS3 Freq Select Bit 3 RW Bit 3 Frequency Selection SRCFS2 Freq Select Bit 2 RW Bit 2 SRCFS1 Freq Select Bit 1 RW Bit 1 SRCFS0 Freq Select Bit 0 RW Bit 0 NOTE: CPU(1:2)_Stop_En (Byte5, bit 6:5) only exist in devices with REV ID = 2 or higher
0891E--03/07/05
PWD 1 1 1 0 0 0 0 0
9
Integrated Circuit Systems, Inc.
ICS951411
SMBus Table: Device ID Register Byte 6 Pin # Name Bit 7 DevID 7 Bit 6 DevID 6 Bit 5 DevID 5 Bit 4 DevID 4 Bit 3 DevID 3 Bit 2 DevID 2 Bit 1 DevID 1 Bit 0 DevID 0 SMBus Table: Vendor ID Register Byte 7 Pin # Name Bit 7 RID3 Bit 6 RID2 Bit 5 RID1 Bit 4 RID0 Bit 3 VID3 Bit 2 VID2 Bit 1 VID1 Bit 0 VID0 SMBus Table: Byte Count Register Byte 8 Pin # Name Bit 7 BC7 Bit 6 BC6 Bit 5 BC5 Bit 4 BC4 Bit 3 BC3 Bit 2 BC2 Bit 1 BC1 Bit 0 BC0 Bytes 9 through 21 are reserved
Control Function Device ID MSB Device ID 6 Device ID 5 Device ID4 Device ID3 Device ID2 Device ID1 Device ID LSB
Type R R R R R R R R
0 -
1 -
PWD 0 0 0 1 0 0 1 1
Control Function Revision ID Starts at 0 hex for A revsion. VENDOR ID (0001 = ICS)
Type R R R R R R R R
0 -
1 -
PWD X X X X 0 0 0 1
Type 0 1 RW RW RW Writing to this register will Byte Count Programming RW configure how many bytes b(7:0) RW will be read back, default RW is 9 bytes. RW RW
Control Function
PWD 0 0 0 0 1 0 0 1
Test Clarification Table
Comments HW TEST_SEL/REF2 HW PIN <0.8V >2.0V OUTPUT NORMAL HI-Z
1. Power-up w/ TEST_SEL/REF2 > 2.0V to enter test mode. 2. Cycle power to disable test mode
0891E--03/07/05
10
Integrated Circuit Systems, Inc.
ICS951411
Absolute Max
Symbol VDD_A VDD_In Ts Tambient Tcase ESD prot Parameter 3.3V Core Supply Voltage 3.3V Logic Input Supply Voltage Storage Temperature Ambient Operating Temp Case Temperature Input ESD protection human body model Min GND - 0.5 -65 0 Max VDD + 0.5V VDD + 0.5V 150 70 115 Units V V C C C V
2000
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5% PARAMETER Input High Voltage Input Low Voltage Input High Current Input Low Current IIL2 Low Threshold InputHigh Voltage Low Threshold InputLow Voltage Operating Current Powerdown Current Input Frequency Pin Inductance Input Capacitance VIH_FS VIL_FS IDD3.3OP IDD3.3PD Fi Lpin CIN COUT CINX TSTAB SYMBOL VIH VIL IIH IIL1 CONDITIONS 3.3 V +/-5% 3.3 V +/-5% VIN = VDD VIN = 0 V; Inputs with no pull-up resistors VIN = 0 V; Inputs with pull-up resistors 3.3 V +/-5% 3.3 V +/-5% all outputs driven all diff pairs driven all differential pairs tri-stated VDD = 3.3 V Logic Inputs Output pin capacitance X1 & X2 pins From VDD Power-Up or deassertion of PD# to 1st clock Triangular Modulation CPU output enable after PD# de-assertion PD# fall time of PD# rise time of MIN 2 VSS - 0.3 -5 -5 -200 0.7 VSS - 0.3 VDD + 0.3 0.35 400 70 12 14.31818 7 5 6 5 1.8 30 33 300 TYP MAX VDD + 0.3 0.8 5 UNITS Notes V V uA uA uA V V mA mA mA MHz nH pF pF pF ms kHz us ns ns V V mA ns ns 1 1 1 1 1 1 1 1 1 1 3 1 1 1 1 1,2 1 1 1 2 1 1 1 1 1
Clk Stabilization Modulation Frequency Tdrive_PD#
Tfall_Pd# 5 Trise_Pd# 5 VDD 2.7 5.5 SMBus Voltage @ IPULLUP VOL 0.4 Low-level Output Voltage Current sinking at IPULLUP 4 VOL = 0.4 V (Max VIL - 0.15) to SCLK/SDATA TRI2C 1000 (Min VIH + 0.15) Clock/Data Rise Time (Min VIH + 0.15) to SCLK/SDATA TFI2C 300 (Max VIL - 0.15) Clock/Data Fall Time 1 Guaranteed by design and characterization, not 100% tested in production. 2 See timing diagrams for timing requirements. 3 Input frequency should be measured at the REFOUT pin and tuned to ideal 14.31818MHz to meet ppm frequency accuracy on PLL outputs.
0891E--03/07/05
11
Integrated Circuit Systems, Inc.
ICS951411
Electrical Characteristics - CPU 0.7V Current Mode Differential Pair
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2, RP=49.9, REF = 475 PARAMETER Current Source Output Impedance Voltage High Voltage Low Max Voltage Min Voltage Crossing Voltage (abs) Crossing Voltage (var) Long Accuracy SYMBOL Zo VHigh VLow Vovs Vuds Vcross(abs) d-Vcross ppm CONDITIONS VO = Vx Statistical measurement on single ended signal using oscilloscope math function. Measurement on single ended signal using absolute value. Variation of crossing over all edges see Tperiod min-max values 400MHz nominal 400MHz spread 333.33MHz nominal 333.33MHz spread 266.66MHz nominal 266.66MHz spread 200MHz nominal 200MHz spread 166.66MHz nominal 166.66MHz spread 133.33MHz nominal 133.33MHz spread 100.00MHz nominal 100.00MHz spread 400MHz nominal/spread 333.33MHz nominal/spread 266.66MHz nominal/spread 200MHz nominal/spread 166.66MHz nominal/spread 133.33MHz nominal/spread 100.00MHz nominal/spread VOL = 0.175V, VOH = 0.525V VOH = 0.525V VOL = 0.175V MIN 3000 660 -150 -300 250 850 mV 150 1150 550 140 -300 2.4993 2.4993 2.9991 2.9991 3.7489 3.7489 4.9985 4.9985 5.9982 5.9982 7.4978 7.4978 9.9970 9.9970 2.4143 2.9141 3.6639 4.8735 5.8732 7.3728 9.8720 175 175 300 2.5008 2.5133 3.0009 3.016 3.7511 3.77 5.0015 5.0266 6.0018 6.0320 7.5023 7.5400 10.0030 10.0533 mV mV mV ppm ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ps ps ps ps 1,3 1 1 1 1 1,2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1 1 1 1 1 1 1 1 1 TYP MAX UNITS NOTES 1 1,3
Average period
Tperiod
Absolute min period
Tabsmin
Rise Time Fall Time Rise Time Variation Fall Time Variation Duty Cycle
tr tf d-tr d-tf dt3
700 700 125 125
Measurement from differential 45 55 % wavefrom CPU(1:0), VT = 50% tsk3 100 ps Skew CPU(1:0) to CPU2_ITP, tsk4 150 ps Skew VT = 50% Measurement from differential tjcyc-cyc 125 ps Jitter, Cycle to cycle wavefrom (CPU2_ITP) Measurement from differential tjcyc-cyc 85 ps Jitter, Cycle to cycle wavefrom, (CPU(1:0)) 1 Guaranteed by design and characterization, not 100% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz 3 IREF = VDD/(3xRR). For RR = 475 (1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50.
0891E--03/07/05
12
Integrated Circuit Systems, Inc.
ICS951411
Electrical Characteristics - SRC 0.7V Current Mode Differential Pair
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2, RP=49.9, REF = 475 PARAMETER Current Source Output Impedance Voltage High Voltage Low Max Voltage Min Voltage Crossing Voltage (abs) Crossing Voltage (var) Long Accuracy Average period Absolute min period Rise Time Fall Time Rise Time Variation Fall Time Variation Duty Cycle SYMBOL Zo VHigh VLow Vovs Vuds Vcross(abs) d-Vcross ppm Tperiod Tabsmin tr tf d-tr d-tf dt3 CONDITIONS VO = Vx Statistical measurement on single ended signal Measurement on single ended signal using MIN 3000 660 -150 -300 250 Variation of crossing over all edges see Tperiod min-max -300 values 100.00MHz nominal 9.9970 9.9970 100.00MHz spread 100.00MHz 9.8720 nominal/spread VOL = 0.175V, 175 VOH = 0.525V VOH = 0.525V 175 VOL = 0.175V 350 12 550 140 300 10.0030 10.0533 850 150 1150 TYP MAX UNITS Notes mV mV mV mV ppm ns ns ns 700 700 30 30 125 125 ps ps ps ps 1 1,3 1,3 1 1 1 1 1,2 2 2 1,2 1 1 1 1
Measurement from 45 55 % 1 differential wavefrom VT = 50% tsk3 250 ps 1 Skew Measurement from tjcyc-cyc Jitter, Cycle to cycle 125 ps 1 differential wavefrom 1 Guaranteed by design and characterization, not 100% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz 3 IREF = VDD/(3xRR). For RR = 475 (1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50.
0891E--03/07/05
13
Integrated Circuit Systems, Inc.
ICS951411
Electrical Characteristics - PCICLK/PCICLK_F
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER Long Accuracy Clock period Output High Voltage Output Low Voltage Output High Current Output Low Current Edge Rate Edge Rate Rise Time Fall Time Duty Cycle Jitter
1 2
SYMBOL ppm Tperiod VOH VOL IOH IOL
CONDITIONS see Tperiod min-max values 33.33MHz output nominal 33.33MHz output spread IOH = -1 mA IOL = 1 mA V OH @MIN = 1.0 V VOH@ MAX = 3.135 V VOL @ MIN = 1.95 V VOL @ MAX = 0.4 V Rising edge rate Falling edge rate VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V
MIN -300 29.9910 29.9910 2.4 -33
TYP
MAX 300 30.0090 30.1598 0.55 -33
UNITS Notes ppm ns ns V V mA mA mA mA V/ns V/ns ns ns % ps 1,2 2 2 1 1 1 1 1 1 1 1 1 1 1 1
30 1 1 0.5 0.5 45 38 4 4 2 2 55 250
tr1 tf1 dt1 tjcyc-cyc
Guaranteed by design and characterization, not 100% tested in production. All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz
Electrical Characteristics - 48MHz, USB
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER Long Accuracy Clock period Output High Voltage Output Low Voltage Output High Current Output Low Current Edge Rate Edge Rate Rise Time Fall Time Duty Cycle Jitter, Cycle to cycle
1 2
SYMBOL ppm Tperiod VOH VOL IOH IOL
CONDITIONS see Tperiod min-max values 48.00MHz output nominal IOH = -1 mA IOL = 1 mA V OH @ MIN = 1.0 V VOH@ MAX = 3.135 V VOL @MIN = 1.95 V VOL @ MAX = 0.4 V Rising edge rate Falling edge rate VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V
MIN -100 20.8313 2.4 -33
TYP
MAX 100 20.8354 0.55 -33
UNITS Notes ppm ns V V mA mA mA mA V/ns V/ns ns ns % ps 1,2 2 1 1 1 1 1 1 1 1 1 1 1 1
30 1 1 1 1 45 38 2 2 2 2 55 175
tr1 tf1 dt1 tjcyc-cyc
Guaranteed by design and characterization, not 100% tested in production. All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz
0891E--03/07/05
14
Integrated Circuit Systems, Inc.
ICS951411
Electrical Characteristics - REF-14.318MHz
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER Long Accuracy Clock period Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Skew Duty Cycle Jitter
1
SYMBOL ppm Tperiod VOH VOL IOH IOL tr1 tf1 tsk1 dt1 tjcyc-cyc
CONDITIONS
MIN
TYP
MAX 300 69.8550 0.4 -23 27 2 2 500 55 1000
UNITS Notes ppm ns V V mA mA ns ns ps % ps 1 1 1 1 1 1 1 1,2 2 1,2 1
see Tperiod min-max values -300 14.318MHz output nominal 69.8270 IOH = -1 mA 2.4 IOL = 1 mA VOH @MIN = 1.0 V, -29 VOH@MAX = 3.135 V VOL @MIN = 1.95 V, VOL 29 @MAX = 0.4 V VOL = 0.4 V, VOH = 2.4 V 1 VOH = 2.4 V, VOL = 0.4 V 1 VT = 1.5 V VT = 1.5 V 45 VT = 1.5 V
Guaranteed by design and characterization, not 100% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz
0891E--03/07/05
15
Integrated Circuit Systems, Inc.
ICS951411
SRC Reference Clock Common Recommendations for Differential Routing Dimension or Value L1 length, Route as non -coupled 50 ohm trace. 0.5 max L2 length, Route as non -coupled 50 ohm trace. 0.2 max L3 length, Route as non -coupled 50 ohm trace. 0.2 max Rs 33 Rt 49.9 Down Device Differential Routing L4 length, Route as coupled microstrip 100 ohm differential trace. L4 length, Route as coup led stripline 100 ohm differential trace. Differential Routing to PCI Express Connector L4 length, Route as coupled microstrip 100 ohm differential trace. L4 length, Rout e as coupled stripline 100 ohm differential trace. Dimension or Value 2 min to 16 max 1.8 min to 14.4 max
Unit inch inch inch ohm ohm Unit inch inch
Figure 2, 3 2, 3 2, 3 2, 3 2, 3 Figure 2 2
Dimension or Value 0.25 to 14 max 0.225 min to 12.6 max
Unit inch inch
Figure 3 3
L1 Rs L1'
L2 L4 L2' Rs Rt Rt PCI Ex REF_CLK Test Load L4'
Fig.1
HSCL Output Buffer
L3'
L3
L1 Rs L1'
L2 L4 L2' Rs Rt Rt PCI Ex Board Down Device REF_CLK Input L4'
Fig.2
HSCL Output Buffer
L3'
L3
L1 Rs L1'
L2 L4 L4' L2' Rs Rt Rt PCI Ex Add In Board REF_CLK Input
Fig.3
HSCL Output Buffer
L3'
L3
0891E--03/07/05
16
Integrated Circuit Systems, Inc.
ICS951411
Shared Pin Operation Input/Output Pins
The I/O pins designated by (input/output) on the ICS951416 serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads. To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic 1) power supply or the GND (logic 0) voltage potential. A 10 Kilohm (10K) resistor is used to provide both the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. Figure 1 shows a means of implementing this function when a switch or 2 pin header is used. With no jumper is installed the pin will be pulled high. With the jumper in place the pin will be pulled low. If programmability is not necessary, than only a single resistor is necessary. The programming resistors should be located close to the series termination resistor to minimize the current loop area. It is more important to locate the series termination resistor close to the driver than the programming resistor.
Programming Header Via to Gnd Device Pad
Via to VDD 2K W
8.2K W Clock trace to load Series Term. Res.
Fig. 1
0891E--03/07/05
17
Integrated Circuit Systems, Inc.
ICS951411
N
c
56-Lead, 300 mil Body, 25 mil, SSOP SYMBOL A A1 b c D E E1 e h L N a VARIATIONS In Millimeters COMMON DIMENSIONS MIN MAX 2.41 2.80 0.20 0.40 0.20 0.34 0.13 0.25 SEE VARIATIONS 10.03 10.68 7.40 7.60 0.635 BASIC 0.38 0.64 0.50 1.02 SEE VARIATIONS 0 8 In Inches COMMON DIMENSIONS MIN MAX .095 .110 .008 .016 .008 .0135 .005 .010 SEE VARIATIONS .395 .420 .291 .299 0.025 BASIC .015 .025 .020 .040 SEE VARIATIONS 0 8
L
INDEX AREA
E1
E
12 D h x 45
A A1
-Ce
b SEATING PLANE .10 (.004) C
N 56
D mm. MIN 18.31 MAX 18.55 MIN .720
D (inch) MAX .730
Reference Doc.: JEDEC Publication 95, MO-118
10-0034
Ordering Information
ICS951411yFLFT
Example:
ICS XXXX y F LF T
Designation for tape and reel packaging Annealed Lead Free (optional) Package Type F = SSOP Revision Designator (will not correlate with datasheet revision) Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device
0891E--03/07/05
18
Integrated Circuit Systems, Inc.
ICS951411
N
c
L
INDEX AREA
E1
E
12 D
a
A2 A1
A
56-Lead 6.10 mm. Body, 0.50 mm. Pitch TSSOP (240 mil) (20 mil) In Millimeters In Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX A -1.20 -.047 A1 0.05 0.15 .002 .006 A2 0.80 1.05 .032 .041 b 0.17 0.27 .007 .011 c 0.09 0.20 .0035 .008 D SEE VARIATIONS SEE VARIATIONS E 8.10 BASIC 0.319 BASIC E1 6.00 6.20 .236 .244 e 0.50 BASIC 0.020 BASIC L 0.45 0.75 .018 .030 N SEE VARIATIONS SEE VARIATIONS a 0 8 0 8 aaa -0.10 -.004 VARIATIONS N 56
10-0039
-Ce
b SEATING PLANE
aaa C
D mm. MIN MAX 13.90 14.10
D (inch) MIN .547 MAX .555
Reference Doc.: JEDEC Publicat ion 95, M O-153
Ordering Information
ICS951411yGLFT
Example:
ICS XXXX y G LF T
Designation for tape and reel packaging Annealed Lead Free (optional) Package Type G = TSSOP Revision Designator (will not correlate with datasheet revision) Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device
0891E--03/07/05
19

▲Up To Search▲

Price & Availability of ICS951411

	To Download ICS951411 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .