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E2A0035-16-X0
Semiconductor MSM6882-3/6882-5
Semiconductor 2400/1200 bps Single Chip MSK Modem
ThisMSM6882-3/6882-5 version: Jan. 1998 Previous version: Nov. 1996
GENERAL DESCRIPTION
The MSM6882-3/6882-5 is a single chip MSK (Minimum Shift Keying) modem which is fabricated by Oki's low power consumption CMOS silicon gate technology. The demodulator receives the data to be transmitted (SD) synchronized with the transmit timing clock (ST) generated by the on-chip clock generator. The signal, which is modulated by MSK method, is output. The demodulator converts the received MSK signal to the received data (RD) by means of a delay detection technique after limiting the band of the received MSK signal. This signal is input to the digital PLL and the re-generated timing clock (RT) is output from the demodulator, synchronized with the RD.
FEATURES
* Signal power supply:+3.6 V (MSM6882-3) +5 V (MSM6882-5) * On-chip SCF (Switched Capacitor Filter) * The transmit filter can be also used as voice splatter filter. * The receive timing re-generator has two different lock-in time performance options to be chosen from. * Bit rate 2400/1200 bps * CCIR Rec. 623 * The modulation method can be selected from COS-FFSK and SIN-FFSK. * Built-in crystal oscillation circuit. * Package options: 22-pin plastic DIP (DIP22-P-400-2.54) (Product name: MSM6882-3RS) (Product name: MSM6882-5RS) 24-pin plastic SOP (SOP24-P-430-1.27-K) (Product name: MSM6882-3GS-K) (Product name: MSM6882-5GS-K)
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Semiconductor
MSM6882-3/6882-5
BLOCK DIAGRAM
ST SD PRE SIN Modulator 1 0 0 RC LPF Transmit LPF FT 1 RC LPF AO
ME BR TI Mixer PRE LPF
LIM
Receive BPF
0 1
RC LPF
AI
CF RT Timing Re-generator RD CT VDD Signal Ground GND SG PDF * Delay Detector SH
MCS X1 X2 * Post Detection Filter
Clock Generator
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PIN CONFIGURATION (TOP VIEW)
X1 1 X2 2 MCS 3 ME 4 SD 5 ST 6 SIN 7 PRE 8 BR 9 SG 10 GND 11
22 VDD 21 FT 20 CT
X1 1 X2 2 MCS 3 ME 4
24 VDD 23 FT 22 CT 21 CF 20 RT 19 (NC) 18 RD 17 CDO 16 CDT 15 AI 14 AO 13 TI
19 CF 18 RT 17 RD 16 CDO 15 CDT 14 AI 13 AO 12 TI
SD 5 ST 6 SIN 7 PRE 8 BR 9 SG 10 GND 11 GND 12
22-Pin Plastic DIP
24-Pin Plastic SOP
NC : No connect pin
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MSM6882-3/6882-5
PIN DESCRIPTION
Name X1 X2 Description Crystal connection pins. A 3.6864 MHz or 7.3728 MHz crystal shall be connected. When an external clock is applied for MSM6882's oscillation source, it has to be input to X2. In this case, X2 has to be AC-coupled by the capacitor of 200 pF. X1 shall be left open. Master clock selection. MCS MCS 0 1 Crystal or External Clock 3.6864 MHz 7.3728 MHz
ME
Modulator enable. When a "high" is input on this pin, MSK modulator output is connected to the input of transmit LPF. When a "low" is input on this pin, TI is connected to the input of transmit LPF. Send data input. The data on this pin is synchronized with the rising edge of ST and input to MSK modulator as an actual transmit data.
SD
SD ST MSK Modulated Data
ST
This timing signal is used to latch serial input data on the SD pin. The frequency of ST coincides with the transmission bit rate. Modulation method selection. Data put on this pin selects either SINE FAST FSK or COSINE FAST FSK. Data (2400 bps) 0 1 0 0 1 1
SIN Sine Fast FSK Cosine Fast FSK Preamble or data transmission selection. When a "low" is input on this pin, the data put on the SD pin is output on the AO pin. When a "high" is input on this pin, the data put on the SD pin is neglected and preamble data is output. Data put on PRE is latched on the rising edge of ST. Preamble means to modulate as 010101...pattern.
PRE
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Name Baud rate selection. Master Clock (MHz) BR 7.3728 3.6864 3.6864 MCS 1 1 0 1 1 BR 1 0 0 1 0
Description Carrier Freq. (Hz) Mark 1200 1200 1200 600 600 Space 2400 1800 1800 1200 900
Bit Rate (bps) 2400 1200 1200 1200 600
SG
Built-in analog signal ground. The DC voltage is approximately half of VDD, so the analog interfaces signals of AI, AO, and TI with peripheral circuits which must be implemented by AC-coupling. To make this voltage source impedance lower and ensure the device performance of this device, more than 0.1 mF bypass capacitors should be connected from SG to GND and from SG to VDD. Ground. (0 V) Voice signal input. The signal input to this pin can be sent out to AO through the transmit LPF, the characteristics of which, gives the splatter filter for voice band signal. When this function is used, digital "0" must be input to ME. TI is biased to SG through internal resistor. Transmit analog signal output. The data put on ME and FT can set the status of AO as follows. FT "1" "1" "0" "0" ME "1" "0" "1" "0" Transmit LPF Power On Power Down State of AO MSK Signal Voice Signal The Output of Receive BPF No-signal (SG level)
GND
TI
TI AO SD Modulator
Power down Transmit LPF SG + - AO
Receive BPF
AI
The state when FT and ME = "0" is shown above. When the input digital data on FT changes to "1" from "0", AO remains to be connected to SG during about 2 ms and after that, and AO is switched to transmit LPF. This delay time prevents AO from outputting meaningless signal during transient time from power down to on of LPF.
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Name AI CDT CDO RD
Description Receive analog signal input. AI is biased internally to SG with about 100 kW same as TI. Device test. This pin should be connected to GND. Device test. This pin should be opened. Demodulated serial data output. This data is synchronized with the re-generated timing clock RT. Receive data timing clock output. This signal is re-generated by internal digital PLL. Synchronizing to negative edge of RT, RD is output.
RT
RT RD Receive data timing clock is re-generated by digital PLL of which phase correcting speed can be selected with CF. When a digital "1" is put on CF and phase difference between receive data timing and RT is more than 22.5 degree, phase correcting speed is high. In this case, as the phase difference enters within 22.5 degrees, that speed changes to low immediately. When digital "0" is input to CF, phase correcting speed of PLL remains low regardless of the phase difference. Usually, CF is connected to digital "1". PLL's lock-in characteristics can be selected with CT. When digital "1" is put on CT, PLL requires max. 50 bit alternative data pattern. On the other hand, when digital "0" is input to CT, PLL can be locked in below 18-bit data.
CF
CT
CF 1 1
CT 0 1
MIN -- --
TYP -- --
MAX 18 50
UNIT bit
FT
Control signal for the internal connection of AO. Refer to column AO. When digital "0" is input to this pin, transmit LPF enters in power down mode, but the output buffer operational amplifier remains active. In this case, AO is at SG level. Power supply. MSM6882-3: 3.6 V MSM6882-5: 5 V This device is sensitive to supply noise as switched capacitor techniques are utilized. A bypass capacitor of more than 2.2 mF between VDD and GND is indispensable to ensure the performance.
VDD
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MSM6882-3/6882-5
ABSOLUTE MAXIMUM RATINGS
Parameter Power Supply Voltage Input Voltage *1 Operating Temperature Storage Temperature Symbol VDD VI Top TSTG Condition Ta = 25C With respect to GND -- -- Rating -0.3 to 7.0 -0.3 to VDD + 0.3 -25 to 70 -55 to 150 Unit V C
*1 MCS, ME, SD, SIN, PRE, BR, TI, AI, CDT, CF, CT, FT
RECOMMENDED OPERATING CONDITIONS
Parameter Power Supply Voltage Operating Temperature Crystal Resonant Frequency Data Speed C1 C2 C3 C4 C5 C6 Oscillation Frequency Frequency Deviation
Crystal
Symbol VDD GND Top fX' TAL TS -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Condition With respect to GND -- -- MCS = "1" MCS = "0" MCS = "1", BR = "1" BR = "0" -- -- -- RLX 40 kW -- -- -- 25 5C At -30C to +70C -- -- -- 25 5C At -30C to +70C -- -- *1 *2
Min. 3.0 4.5 -- -25 7.3721 3.6860 -- -- -- -- -- -- -- -- -- -100 -100 -- -- -- -100 -100 -- --
Typ. 3.6 5 0 25 7.3728 3.6864 2400 1200 2.2 0.1 0.047 0.047 0.047 0.1 7.3728 -- -- -- 16 3.6864 -- -- -- 16
Max. 4.0 5.5 -- 70 7.3735 3.6868 -- -- -- -- -- -- -- -- -- +100 +100 50 -- -- +100 +100 100 --
Unit V C MHz bit/sec
mF
MHz ppm
Temperature Characteristics Equivalent Series Resistance Load Capacitance Oscillation Frequency Frequency Deviation Temperature Characteristics Equivalent Series Resistance Load Capacitance
W pF MHz ppm
Crystal
W pF
*1 MSM6882-3 *2 MSM6882-5
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ELECTRICAL CHARACTERISTICS
DC Characteristics
Parameter Symbol IDD Power Supply Current *1 IDDS Input Leakage Current *2 IIL IIH VIL Input Voltage *2 VIH VOL1 VOH1 *1 IOL = 10 mA/1.6 mA IOH = 10 mA/400 mA Condition Normal Operating Mode FT = "1" Power Down Mode FT = "0" VIN = 0 V VIN = VDD *1 (MSM6882-3: VDD = 3 V to 4 V, Ta = -25C to 70C) (MSM6882-5: VDD = 5 V 0.5 V, Ta = -25C to 70C) Min. -- -- -- -- -10 -10 0 1.8 2.2 0 0.8VDD Typ. 4 5.5 3.5 5.0 -- -- -- -- -- -- Max. 8 11 7 10 10 10 0.6 0.8 VDD 0.3 0.4 VDD V mA mA Unit
Output Voltage
*1 *3
*1 Upper is specified for the MSM6882-3, lower for the MSM6882-5 *2 MCS, ME, SD, SIN, PRE, BR, CF, CT, FT *3 ST, RD, RT Digital Interface Characteristics
Parameter Input Data Set-up Time Input Data Hold Time Output Data Delay Time Symbol tS tH tD Condition See Fig.1 See Fig.2 Min. 300 300 -300 Typ. -- -- -- Max. -- -- 300 Unit ns ns ns
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Semiconductor Analog Interface Characteristics Transmit signal output (AO)
Parameter 1200 bps 2400 bps Carrier Level Output Amplitude Output Resistance Output Load Resistance Output Load Capacitance Output DC Voltage *1 *1 Symbol fM1 fS1 fM2 fS2 VOX VOPP ROX RLX CLX VOSX FT = "1" ME = "1" Condition BR = "0" BR = "1" SD = "1" SD = "0" SD = "1" SD = "0" FT = "1" ME = "1" FT = "1" ME = "0" -- -- -- --
MSM6882-3/6882-5
(MSM6882-3: VDD = 3 V to 4 V, Ta = -25C to 70C) (MSM6882-5: VDD = 5 V 0.5 V, Ta = -25C to 70C) Min. 1199 1799 1199 2399 -7 -3 1.4 2.2 -- 40 -- 0.48VDD Typ. 1200 1800 1200 2400 -3 0 2.0 3.0 50 -- -- 0.50VDD Max. 1201 1801 1201 2401 -1 2 -- -- -- -- 40 0.52VDD dBm *2 Vp-p W kW pF V Hz Unit
Carrier Frequency
RL 40 kW CL 40 pF
Voice signal input (TI)
Parameter Voltage Gain Input Signal Level Input Resistance *1 Symbol GT VTI RTI Condition VAO/VTI -- fTI 4 kHz FT = "1" ME = "0" Min. -2 -- 40 Typ. 0 -- 100 Max. +2 -4 0 300 Unit dB dBm *2 kW
Built-in signal ground (SG)
Parameter DC Voltage Symbol VSG Condition Without DC Load Min. Typ. Max. 0.52VDD Unit V
0.48VDD 0.50VDD
Receive signal input (AI)
Parameter Input Resistance Receive Signal Level 1200 bps Bit Error Rate 2400 bps BER Symbol RAI VIR1 VIR2 -- Condition fAI 4 kHz BR = "0" BR = "1" 7 dB S/N at AI SIN = "1" S/N 11 dB 10 dB 14 dB Min. 40 -30 -24 -- -- -- -- Typ. 100 -- -- 2 2 10-3 10-3 2 10-5 2 10-5 Max. 300 0 0 -- -- -- -- Unit kW dBm *2
*1 Upper is specified for the MSM6882-3, lower for the MSM6882-5 *2 0 dBm = 0.775 Vrms
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Semiconductor Re-generated receive data timing clock output (RT)
Parameter Data Bit Number for PLL' Lock-in Symbol NPLL1 NPLL2 CF = "1" Condition CT= "0" CT= "1" *3 Min. -- --
MSM6882-3/6882-5
Typ. -- --
Max. 18 50
Unit bit
*3 Data bit number to lock-in within 22.5 degree
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Semiconductor
MSM6882-3/6882-5
TIMING DIAGRAM
ST
50%
SD, PRE tS tH
50%
Figure 1 Input Data Timing
RT
50%
RD tD
50%
Figure 2 Output Data Timing
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Semiconductor
MSM6882-3/6882-5
BUILT-IN FILTER FREQUENCY CHARACTERISTICS
GAIN (dB) 1 0 -10 -20 -30 -40 -50 -60 Transmit Low-Pass Filter -70 2 3 4 5 6 7 8
FREQ (kHz) 9 10
GAIN (dB) 0.5 0 -10 -20 -30 -40 -50 -60 Receive Band-Pass Filter -70 1 1.5 2 2.5 3 3.5
FREQ (kHz) 4
Note:
When BR = "1", frequency converter circuit (MIXER) is prepared before the receive BPF. Therefore, 1200 Hz input signal is converted to 3600 Hz at BPF output for example.
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APPLICATION CIRCUIT
VDD Crystal 7.3728 MHz 1 X1 2 X2 3 MCS 4 ME 5 SD 6 ST 7 SIN 8 PRE 9 BR C6 VDD C2 10 SG 11 GND V DD 22 FT 21 CT 20 CF 19 RT 18 RD 17 CDO 16 CDT 15 AI 14 AO 13 TI 12 C3 C4 C5 C1
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PACKAGE DIMENSIONS
(Unit : mm)
DIP22-P-400-2.54
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 1.90 TYP.
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Semiconductor
MSM6882-3/6882-5
(Unit : mm)
SOP24-P-430-1.27-K
Mirror finish
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 0.58 TYP.
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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