View TC55NEM216AFTN55_283745.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

TC55NEM216AFTN55,70
TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
262,144-WORD BY 16-BIT FULL CMOS STATIC RAM DESCRIPTION
The TC55NEM216AFTN is a 4,194,304-bit static random access memory (SRAM) organized as 262,144 words by 16 bits. Fabricated using Toshiba's CMOS Silicon gate process technology, this device operates from a single 5V 10% power supply. Advanced circuit technology provides both high speed and low power at an operating current of 3 mA/MHz (typ) and a minimum cycle time of 55 ns. It is automatically placed in low-power mode at 1 A standby current (typ) when chip enable ( CE ) is asserted high. There are two control inputs. CE is used to select the device and for data retention control, and output enable ( OE ) provides fast memory access. Data byte control pin ( LB , UB ) provides lower and upper byte access. This device is well suited to various microprocessor system applications where high speed, low power and battery backup are required. And, with a guaranteed operating extreme temperature range of -40 to 85C, the TC55NEM216AFTN can be used in environments exhibiting extreme temperature conditions. The TC55NEM216AFTN is available in a plastic 54-pin thin-small-outline package (TSOP).
FEATURES
* * * * * * * Low-power dissipation Operating: 15 mW/MHz (typical) Single power supply voltage of 5 V 10% Power down features using CE Data retention supply voltage of 2.0 to 5.5 V Direct TTL compatibility for all inputs and outputs Wide operating temperature range of -40 to 85C Standby Current (maximum): 20 A * Access Times (maximum):
TC55NEM216AFTN 55 Access Time
CE Access Time OE Access Time
70 70 ns 70 ns 35 ns
55 ns 55 ns 30 ns
*
Package: TSOP II54-P-400-0.80
(Weight:
g typ)
PIN ASSIGNMENT (TOP VIEW)
54 PIN TSOP
NC A3 A2 A1 A0 I/O16 I/O15 VDD GND I/O14 I/O13 UB CE OP R/W I/O12 I/O11 GND VDD I/O10 I/O9 NC A17 A16 A15 A14 A13 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 A4 A5 A6 A7 NC I/O1 I/O2 VDD GND I/O3 I/O4 LB OE OP NC I/O5 I/O6 GND VDD I/O7 I/O8 A8 A9 A10 A11 A12 NC
PIN NAMES
A0~A17
CE
Address Inputs Chip Enable Read/Write Control Output Enable Data Byte Control Data Inputs/Outputs Power (+5 V) Ground No Connection Option
R/W
OE
LB , UB I/O1~I/O16 VDD GND NC OP*
*: OP pin must be open or connected to GND.
2002-07-04
1/11
TC55NEM216AFTN55,70
BLOCK DIAGRAM
CE A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A17 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 I/O16 VDD GND MEMORY CELL ARRAY 2,048 x 128 x 16 (4,194,304)
ROW ADDRESS BUFFER
ROW ADDRESS REGISTER
ROW ADDRESS DECODER
SENSE AMP DATA OUTPUT BUFFER CE A0 A1 A2 A3 A4 A5 A16 DATA INPUT BUFFER
COLUMN ADDRESS DECODER COLUMN ADDRESS REGISTER COLUMN ADDRESS BUFFER
CLOCK GENERATOR
CE
CE LB
UB
R/W
OE
DATA OUTPUT BUFFER
DATA INPUT BUFFER
2002-07-04
2/11
TC55NEM216AFTN55,70
OPERATING MODE
MODE
CE OE
R/W H H H L L L H H H * *
LB L H L L H L L H L * H
UB
I/O1~I/O8 Output High-Z Output Input High-Z Input High-Z High-Z High-Z High-Z High-Z
I/O9~I/O16 Output Output High-Z Input Input High-Z High-Z High-Z High-Z High-Z High-Z
POWER IDDO IDDO IDDO IDDO IDDO IDDO IDDO IDDO IDDO IDDS IDDS
L Read L L L Write L L L Output Deselect L L Standby * = don't care H = logic high L = logic low H *
L L L * * * H H H * *
L L H L L H L L H * H
MAXIMUM RATINGS
SYMBOL VDD VIN VI/O PD Tsolder Tstg Topr Power Supply Voltage Input Voltage Input/Output Voltage Power Dissipation Soldering Temperature (10s) Storage Temperature Operating Temperature RATING VALUE -0.3~7.0 -0.3*~7.0 -0.5~VDD + 0.5 0.6 260 -55~150 -40~85 UNIT V V V W C C C
*: -2.0 V when measured at a pulse width of 20ns
DC RECOMMENDED OPERATING CONDITIONS (Ta = -40 to 85C)
SYMBOL VDD VIH VIL VDH PARAMETER Power Supply Voltage Input High Voltage Input Low Voltage Data Retention Supply Voltage MIN 4.5 2.2 -0.3* 2.0 TYP 5.0 MAX 5.5 VDD + 0.3 0.6 5.5 UNIT V V V V
*: -2.0 V when measured at a pulse width of 20ns
2002-07-04
3/11
TC55NEM216AFTN55,70
DC CHARACTERISTICS (Ta = -40 to 85C, VDD = 5 V 10%)
SYMBOL IIL IOH IOL ILO PARAMETER Input Leakage Current Output High Current Output Low Current Output Leakage Current VIN = 0 V~VDD VOH = 2.4 V VOL = 0.4 V
CE = VIH or LB = UB = VIH or R/W = VIL or OE = VIH, VOUT = 0 V~VDD CE = VIL and R/W = VIH, LB = UB = VIL, IOUT = 0 mA, Other Input = VIH/VIL CE = 0.2 V and R/W = VDD - 0.2 V, LB = UB = 0.2 V, IOUT = 0 mA, Other Input = VDD - 0.2 V/0.2 V
TEST CONDITION
MIN -1.0 2.1 MIN tcycle 1 s MIN tcycle 1 s
TYP
MAX 1.0 1.0 35
UNIT A mA mA A

8
lDDO1 Operating Current lDDO2
mA 30 mA 3 1 3 3 20 A mA
IDDS1 Standby Current IDDS2
1) CE = VIH 2) LB = UB = VIH Ta = 25C 1) CE = VDD - 0.2 V 2) LB = UB = VDD - 0.2 V, CE = 0.2 V Ta = -40~40C Ta = -40~85C

CAPACITANCE (Ta = 25C, f = 1 MHz)
SYMBOL CIN COUT Note: PARAMETER Input Capacitance Output Capacitance VIN = GND VOUT = GND TEST CONDITION MAX 10 10 UNIT pF pF
This parameter is periodically sampled and is not 100% tested.
2002-07-04
4/11
TC55NEM216AFTN55,70
(Ta = -40 to 85C, VDD = 5 V 10%) READ CYCLE
TC55NEM216AFTN SYMBOL PARAMETER MIN tRC tACC tCO tOE tBA tCOE tOEE tBE tOD tODO tBD tOH Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Access Time Data Byte Control Access Time Chip Enable Low to Output Active Output Enable Low to Output Active Data Byte Control Low to Output Active Chip Enable High to Output High-Z Output Enable High to Output High-Z Data Byte Control High to Output High-Z Output Data Hold Time 55 5 0 5 10 55 MAX 55 55 30 55 25 25 25 MIN 70 5 0 5 10 70 MAX 70 70 35 70 30 30 30 ns UNIT
AC CHARACTERISTICS AND OPERATING CONDITIONS
WRITE CYCLE
TC55NEM216AFTN SYMBOL PARAMETER MIN tWC tWP tCW tBW tAS tWR tODW tOEW tDS tDH Note: Write Cycle Time Write Pulse Width Chip Enable to End of Write Data Byte Control to End of Write Address Setup Time Write Recovery Time R/W Low to Output High-Z R/W High to Output Active Data Setup Time Data Hold Time 55 40 45 45 0 0 0 25 0 55 MAX 25 MIN 70 50 55 55 0 0 0 30 0 70 MAX 30 ns UNIT
tOD, tODO, tBD and tODW are specified in time when an output becomes high impedance, and are not judged depending on an output voltage level.
AC TEST CONDITIONS
PARAMETER Input pulse level t R, t F Timing measurements Reference level Output load TEST CONDITION 0.4 V, 2.4 V 5 ns 1.5 V 1.5 V 100 pF + 1 TTL Gate
2002-07-04
5/11
TC55NEM216AFTN55,70
TIMING DIAGRAMS
READ CYCLE
(See Note 1)
tRC Address A0~A17 tACC tCO
CE
tOH
tOE
OE
tOD
tBA
UB , LB
tODO
DOUT I/O1~16
tBE tOEE Hi-Z tCOE
tBD VALID DATA OUT Hi-Z
WRITE CYCLE 1 (R/W CONTROLLED)
(See Note 4)
tWC Address A0~A17 tAS R/W tCW
CE
tWP
tWR
tBW
UB , LB
tODW DOUT I/O1~16 (See Note 2) Hi-Z tDS DIN I/O1~16 (See Note 5)
tOEW (See Note 3) tDH (See Note 5)
VALID DATA IN
2002-07-04
6/11
TC55NEM216AFTN55,70
WRITE CYCLE 2 ( CE CONTROLLED)
(See Note 4)
tWC Address A0~A17 tAS R/W tCW
CE
tWP
tWR
tBW
UB , LB
tBE DOUT I/O1~16 Hi-Z
tODW Hi-Z tDS tDH
tCOE
DIN I/O1~16
(See Note 5)
VALID DATA IN
WRITE CYCLE 3 ( UB, LB CONTROLLED)
(See Note 4)
tWC Address A0~A17 tAS R/W tCW
CE
tWP
tWR
tBW
UB , LB
tBE DOUT I/O1~16 Hi-Z
tODW Hi-Z tDS tDH
tCOE
DIN I/O1~16
(See Note 5)
VALID DATA IN
2002-07-04
7/11
TC55NEM216AFTN55,70
Note: (1) (2) (3) (4) (5) R/W remains HIGH for the read cycle. If CE (or UB or LB ) goes LOW coincident with or after R/W goes LOW, the outputs will remain at high impedance. If CE (or UB or LB ) goes HIGH coincident with or before R/W goes HIGH, the outputs will remain at high impedance. If OE is HIGH during the write cycle, the outputs will remain at high impedance. Because I/O signals may be in the output state at this time, input signals of reverse polarity must not be applied.
DATA RETENTION CHARACTERISTICS (Ta = -40 to 85C)
SYMBOL VDH IDDS2 tCDR tR PARAMETER Data Retention Supply Voltage Standby Current Ta = -40~40C Ta = -40~85C MIN 2.0 0 5 TYP MAX 5.5 3 20 ns ms UNIT V A
Chip Deselect to Data Retention Mode Time Recovery Time
CE CONTROLLED DATA RETENTION MODE
VDD
VDD 4.5 V
DATA RETENTION MODE
(See Note 1) VIH tCDR
CE
(See Note 1) VDD - 0.2 V tR
GND
UB , LB CONTROLLED DATA RETENTION MODE
VDD
(See Note 2)
VDD 4.5 V
DATA RETENTION MODE
(See Note 3) VIH tCDR
UB , LB
(See Note 3) VDD - 0.2 V tR
GND
2002-07-04
8/11
TC55NEM216AFTN55,70
Note: (1) (2) (3) When CE is operating at the VIH(min.) level(2.2 V), the operating current is given by IDDS1 during the transition of VDD from 4.5 to 2.4 V. In UB (or LB ) controlled data retention mode, minimum standby current mode is entered when CE 0.2 V or CE VDD - 0.2 V. When UB (or LB ) is operating at the VIH(min.) level(2.2 V), the operating current is given by IDDS1 during the transition of VDD from 4.5 to 2.4 V.
2002-07-04
9/11
TC55NEM216AFTN55,70
PACKAGE DIMENSIONS
Weight:
g (typ)
2002-07-04
10/11
TC55NEM216AFTN55,70
RESTRICTIONS ON PRODUCT USE
000707EBA
* TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc.. * The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. * The products described in this document are subject to the foreign exchange and foreign trade laws. * The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. * The information contained herein is subject to change without notice.
2002-07-04
11/11

▲Up To Search▲

Price & Availability of TC55NEM216AFTN55

	To Download TC55NEM216AFTN55 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .