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E2I0024-17-Y1 Semiconductor
Semiconductor MSM521004
262,144-Word 4-Bit CMOS STATIC RAM
This version: Jan. 1998 MSM521004 Previous version: Aug. 1996
DESCRIPTION
The MSM521004 is a 262,144-word by 4-bit CMOS fast static RAM featuring a single 5 V power supply operation and direct TTL input/output compatibility. Since the circuitry is completely static, external clock and refreshing operations are unnecessary, making this device very easy to use. The MSM521004 uses NMOS cells and CMOS peripherals and provides high-speed operation at 17 ns access time. In addition, the MSM521004 is provided with a chip enable signal (CE) suited to the power-down function, an output enable signal (OE) suited to the I/O bus line control.
FEATURES
* 262,144-word 4-bit configuration * Single 5 V power supply * Fully static operation * Operating temperature range: Ta = 0C to 70C * Power dissipation Standby: 1 mA (Max.) Operation: - 17 140 mA (Max.) - 20 130 mA (Max.) - 25 120 mA (Max.) * Access time: - 17 17 ns (Max.) - 20 20 ns (Max.) - 25 25 ns (Max.) * (Input/Output) TTL compatible * Power-down function by chip enable signal * 3-state output * Package: 28-pin 400 mil plastic SOJ (SOJ28-P-400-1.27)
(Product : MSM521004-xxJS) xx indicates speed rank.
PRODUCT FAMILY
Family MSM521004-17 MSM521004-20 MSM521004-25 Access Time (Max.) 17 ns 20 ns 25 ns 400 mil 28-pin SOJ Package
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Semiconductor
MSM521004
PIN CONFIGURATION (TOP VIEW)
A0 A1 A2 A3 A4 A5 A6 A7 A8
A9 10 A10 11 CE 12 OE 13 VSS 14
1 2 3 4 5 6 7 8 9 28-Pin Plastic SOJ
Function Address Input Data Input/Output Chip Enable Output Enable Write Enable Power Supply No Connection
28 VCC 27 A17 26 A16 25 A15 24 A14 23 A13 22 A12 21 A11 20 NC 19 I/O3 18 I/O2 17 I/O1 16 I/O0 15 WE
Pin Name A0 - A17 I/O0 - I/O3 CE OE WE VCC, VSS NC
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Semiconductor
MSM521004
BLOCK DIAGRAM
A5 A10 A9 A8 A6 A3 A2 A1 A0 I/O0 I/O1 I/O2 I/O3
Row Select
Memory Array 512 Rows 512 Columns 4 Blocks
V CC V SS
Input Data Control
Column I/O Circuits Column Select
A4
A11 A13 A15 A17 A7 A12 A14 A16
CE WE OE
FUNCTION TABLE
CE H L L L OE * L H * WE * H H L Operating Mode Non Selectable Read Mode Read Mode Write Mode I/O Operation High-Z DOUT High-Z DIN Power Mode Standby Active Active Active
*Don't Care ("H" or "L")
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Semiconductor
MSM521004
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter Power Supply Voltage Pin Voltage Power Dissipation Operating Temperature Storage Temperature Symbol VCC VT PD Topr Tstg Condition Ta = 25C, for VSS Ta = 25C -- -- Rating -0.3 to 7.0 -0.3* to VCC + 0.3 1.0 0 to 70 -55 to 125 Unit V V W C C
* -3.0 V Min. for pulse width less than 10 ns. Recommended Operating Conditions
Parameter Power Supply Voltage Input High Voltage Input Low Voltage Load Capacitance Symbol VCC VSS VIH VIL CL Condition -- VCC = 5 V 10% -- Min. 4.5 0 2.2 -0.3* -- Typ. 5 0 -- -- -- Max. 5.5 0 VCC + 0.3 0.8 30 Unit V V V V pF
* -3.0 V Min. for pulse width less than 10 ns. Capacitance
(Ta = 25C, f = 1 MHz) Parameter Input Capacitance Input/Output Capacitance Symbol CI CI/O Condition VIN = 0 V VI/O = 0 V Min. -- -- Max. 6 8 Unit pF pF
Note:
This parameter is periodically sampled and not 100% tested.
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Semiconductor DC Characteristics
MSM521004
(VCC = 5 V 10%, Ta = 0C to 70C) Parameter Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage Symbol ILI ILO VOH VOL ICCS Condition VIN = 0 to VCC CE = VIH or OE = VIH or WE = VIL, VOUT = 0 to VCC IOH = -4.0 mA IOL = 8.0 mA CE VCC - 0.2 V, Standby Power Supply Current ICCS1 Operating Power Supply Current VIN 0.2 V or VIN VCC - 0.2 V CE = VIH, TCYC = Min. cycle CE = VIL, ICCA TCYC = Min. cycle, IOUT = 0 mA q 521004-17 521004-20 521004-25 140 mA 130 mA 120 mA -- -- q mA -- -- 20 mA -- -- 1 mA 2.4 -- -- -- -- 0.4 V V -10 -- 10 mA Min. -10 MSM521004 Typ. Max. -- 10 Unit mA
AC Characteristics Test Conditions
Parameter Input Pulse Level Input Rise and Fall Times Input/Output Timing Level Output Load Condition VIH = 3 V, VIL = 0 V 3 ns 1.5 V See Figures
5V 480 W DOUT 255 W 30 pF (Including scope and jig) DOUT 255 W
5V 480 W
5 pF (Including scope and jig)
Figure 1 Output Load
Figure 2 Output Load (tOLZ, tOHZ, tCLZ, tCHZ, tWLZ, tWHZ)
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Semiconductor Read Cycle
MSM521004
(VCC = 5 V 10%, Ta = 0C to 70C) MSM521004-17 Parameter Read Cycle Time Address Access Time CE Access Time OE Access Time CE to Output in Low-Z OE to Output in Low-Z Output Hold Time from Address Change CE to Output in High-Z OE to Output in High-Z Symbol tRC tAA tCO tOE tCLZ tOLZ tOH tCHZ tOHZ Min. 17 -- -- -- 3 0 3 -- -- Max. -- 17 17 9 -- -- -- 7 7 MSM521004-20 Min. 20 -- -- -- 3 0 3 -- -- Max. -- 20 20 10 -- -- -- 8 8 MSM521004-25 Min. 25 -- -- -- 3 0 3 -- -- Max. -- 25 25 12 -- -- -- 10 10 Unit ns ns ns ns ns ns ns ns ns
Address Controlled Read (WE = H, CE = L, OE = L)
tRC ADDRESS tAA tOH DOUT Dataout Valid
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, ,
Semiconductor CE, OE Controlled Read (WE = H)
tRC ADDRESS tAA tCHZ CE tCO tCLZ OE tOE tOHZ DOUT Dataout Valid tOLZ tOH
MSM521004
Notes :
1. A read cycle occurs during the overlap of CE = "L", OE = "L" and WE = "H". 2. tCHZ and tOHZ are specified by the time when DATA is floating, not defined by the output level.
7/11
Semiconductor Write Cycle
Parameter Write Cycle Time Address Setup Time Write Pulse Width Write Recovery Time Data Setup Time Data Hold Time WE to Output in High-Z CE to End of Write WE CE Symbol tWC tAS tWP tWR tDS tDH tWHZ tCW tAW
MSM521004
(VCC = 5 V 10%, Ta = 0C to 70C) MSM521004-17 MSM521004-20 MSM521004-25 Min. 17 0 13 0 0 9 0 -- 13 0 Max. -- -- -- -- -- -- -- 7 -- Min. 20 0 15 0 0 10 0 -- 15 0 Max. -- -- -- -- -- -- -- 8 -- Min. 25 0 20 0 0 12 0 -- 20 0 Max. -- -- -- -- -- -- -- 10 -- Unit ns ns ns ns ns ns ns ns
, ,
Address Valid to End of Write 13 -- 15 -- 20 -- ns Output Active from End of Write tWLZ -- -- -- ns
WE Controlled Write (OE = L)
tWC
ADDRESS
tCW
CE
tAW
WE
tAS
tWR
tWP
tWLZ
DOUT
tDS
tDH
tWHZ
DIN
Data In
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Semiconductor CE Controlled Write (OE = H)
MSM521004
tWC ADDRESS tAS CE tCW
WE
DIN
DOUT
Notes:

tAW tWR tWP tDS tDH Data In High Impedance
1. 2. 3. 4. 5. 6.
A write cycle occurs during the overlap of CE = "L" and WE = "L". OE may be either of "H" or "L" in the write cycle. tAS is specified from CE = "L" or WE = "L", whichever occurs last. tWP is an overlap time of CE = "L" and WE = "L". tWR, tDS and tDH are specified from CE = "H" or WE = "H", whichever occurs first. tWHZ is specified by the time when DATA output is floating, not defined by the output level. 7. When I/O pins are in the output mode, don't apply the inverted input signal to the output pins.
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Semiconductor Data Retention Characteristics
Parameter Data Retention Power Supply Voltage Data Retention Power Supply Current Chip Deselect to Data Retention Time Operation Recovery Time Symbol VCCH ICCH tCDR tR Condition CE VCC - 0.2 V VCC = 3 V, CE VCC - 0.2 V -- -- Min. 2.0 -- 0 5 Typ. -- -- -- --
MSM521004
(Ta = 0C to 70C) Max. -- 500 -- -- Unit V mA ns ms
tCDR VCC 4.5 V VIH VCCH CE 0V
Standby mode
tR
CE VCC - 0.2 V
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Semiconductor
MSM521004
PACKAGE DIMENSIONS
(Unit : mm)
SOJ28-P-400-1.27
Mirror finish
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 1.30 TYP.
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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