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19-2440; Rev 2; 10/02
Low-Power, SC70/SOT P Reset Circuits with Capacitor-Adjustable Reset Timeout Delay
General Description
The MAX6340/MAX6421-MAX6426 low-power microprocessor supervisor circuits monitor system voltages from 1.6V to 5V. These devices perform a single function: they assert a reset signal whenever the VCC supply voltage falls below its reset threshold. The reset output remains asserted for the reset timeout period after VCC rises above the reset threshold. The reset timeout is externally set by a capacitor to provide more flexibility. The MAX6421/MAX6424 have an active-low, pushpull reset output. The MAX6422 has an active-high, push-pull reset output and the MAX6340/MAX6423/ MAX6425/MAX6426 have an active-low, open-drain reset output. The MAX6421/MAX6422/MAX6423 are offered in 4-pin SC70 or SOT143 packages. The MAX6340/MAX6424/MAX6425/MAX6426 are available in 5-pin SOT23-5 packages.
Features
o Monitor System Voltages from 1.6V to 5V o Capacitor-Adjustable Reset Timeout Period o Low Quiescent Current (1.6A typ) o Three RESET Output Options Push-Pull RESET Push-Pull RESET Open-Drain RESET o Guaranteed Reset Valid to VCC = 1V o Immune to Short VCC Transients o Small 4-Pin SC70, 4-Pin SOT143, and 5-Pin SOT23 Packages o MAX6340 Pin Compatible with LP3470 o MAX6424/MAX6425 Pin Compatible with NCP300-NCP303, MC33464/MC33465, S807/S808/S809, and RN5VD o MAX6426 Pin Compatible with PST92XX
MAX6340/MAX6421-MAX6426
Applications
Portable Equipment Battery-Powered Computers/Controllers Automotive Medical Equipment Intelligent Instruments Embedded Controllers Critical P Monitoring Set-Top Boxes Computers
Ordering Information
PART MAX6340UK_ _-T MAX6421XS_ _-T MAX6421US_ _-T MAX6422XS_ _-T MAX6422US_ _-T MAX6423XS_ _-T MAX6423US_ _-T MAX6424UK_ _-T MAX6425UK_ _-T TEMP RANGE -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C PIN-PACKAGE 5 SOT23-5 4 SC70-4 4 SOT143-4 4 SC70-4 4 SOT143-4 4 SC70-4 4 SOT143-4 5 SOT23-5 5 SOT23-5 5 SOT23-5
Pin Configurations
TOP VIEW
VCC 1 4 RESET (RESET)
MAX6426UK_ _-T
MAX6421X MAX6422X MAX6423X
GND 2 3
SRT
Note: The MAX6340/MAX6421-MAX6426 are available with factory-trimmed reset thresholds from 1.575V to 5.0V in approximately 0.1V increments. Insert the desired nominal reset threshold suffix (from Table 1) into the blanks. There are 50 standard versions with a required order increment of 2500 pieces. Sample stock is generally held on standard versions only (see Standard Versions Table). Required order increment is 10,000 pieces for nonstandard versions. Contact factory for availability. All devices are available in tape-and-reel only. Typical Operating Circuit appears at end of data sheet. Selector Guide appears at end of data sheet. 1
SC70
( ) ARE FOR THE MAX6422
Pin Configurations continued at end of data sheet.
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Low-Power, SC70/SOT P Reset Circuits with Capacitor-Adjustable Reset Timeout Delay
MAX6340/MAX6421-MAX6426
ABSOLUTE MAXIMUM RATINGS
All Voltages Referenced to GND VCC ........................................................................-0.3V to +6.0V SRT, RESET, RESET (push-pull).................-0.3V to (VCC + 0.3V) RESET (open drain)...............................................-0.3V to +6.0V Input Current (all pins)......................................................20mA Output Current (RESET, RESET) ......................................20mA Continuous Power Dissipation (TA = +70C) 4-Pin SC70 (derate 3.1mW/C above +70C) ..............245mW 4-Pin SOT143 (derate 4mW/C above +70C).............320mW 5-Pin SOT23 (derate 7.1mW/C above +70C)............571mW Operating Temperature Range .........................-40C to +125C Storage Temperature Range .............................-65C to +150C Junction Temperature ......................................................+150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC = 1V to 5.5V, TA = TMIN to TMAX, unless otherwise specified. Typical values are at VCC = 5V and TA = +25C.) (Note 1)
PARAMETER Supply Voltage Range Supply Current SYMBOL VCC VCC 5.0V ICC VCC 3.3V VCC 2.0V VCC Reset Threshold Accuracy Hysteresis VCC to Reset Delay Reset Timeout Period VSRT Ramp Current VSRT Ramp Threshold RAMP Threshold Hysteresis RESET Output Voltage Low VOL VTH VHYST tRD tRP IRAMP VTH-RAMP VCC falling at 1mV/s CSRT = 1500pF CSRT = 0 VSRT = 0 to 0.65V; VCC = 1.6V to 5V VCC = 1.6V to 5V (VRAMP rising) VRAMP falling threshold VCC 1.0V, ISINK = 50A VCC 2.7V, ISINK = 1.2mA VCC 4.5V, ISINK = 3.2mA RESET Output Voltage High, Push-Pull RESET Output Leakage Current, Open-Drain VCC 1.8V, ISOURCE = 200A VOH VCC 2.25V, ISOURCE = 500A VCC 4.5V, ISOURCE = 800A ILKG VCC > VTH, reset not asserted VCC 1.0V, ISOURCE = 1A RESET Output Voltage High VOH VCC 1.8V, ISOURCE = 150A VCC 2.7V, ISOURCE = 500A VCC 4.5V, ISOURCE = 800A VCC 1.8V, ISINK = 500A RESET Output Voltage Low VOL VCC 2.7V, ISINK = 1.2mA VCC 4.5V, ISINK = 3.2mA 0.8 x VCC 0.8 x VCC 0.8 x VCC 0.8 x VCC 0.3 0.3 0.4 V V 0.8 x VCC 0.8 x VCC 0.8 x VCC 1.0 A V 3.00 TA = +25C TA = -40C to +125C VTH - 1.5% VTH - 2.5% 80 4.375 0.275 240 0.65 33 0.3 0.3 0.4 V 5.75 CONDITIONS MIN 1.0 2.5 1.9 1.6 TYP MAX 5.5 4.2 3.4 2.5 VTH + 1.5% VTH + 2.5% V mV s ms nA V mV A UNITS V
4 x VTH
Note 1: Devices production tested at +25C. Overtemperature limits are guaranteed by design.
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Low-Power, SC70/SOT P Reset Circuits with Capacitor-Adjustable Reset Timeout Delay
Typical Operating Characteristics
(VCC = 5V, CSRT = 1500pF, TA = +25C, unless otherwise noted.)
MAX6340/MAX6421-MAX6426
SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX6421/26 toc01
RESET TIMEOUT PERIOD vs. CSRT
MAX6421/26 toc02
RESET TIMEOUT PERIOD vs. TEMPERATURE
CSRT = 1500pF RESET TIMEOUT PERIOD (ms) 4.25
MAX6421/26 toc03 MAX6421/26 toc06
4.0 3.5 SUPPLY CURRENT (A) 3.0 2.5 2.0 1.5 1.0 0.5 0 0 1 2 3 4 5 6 SUPPLY VOLTAGE (V) TA = -40C TA = +25C TA = +125C
10,000
4.30
RESET TIMEOUT PERIOD (ms)
1000
100
4.20
10
4.15
1
0.1 0.001
4.10 0.01 0.1 1 CSRT (nF) 10 100 1000 -50 -25 0 25 50 75 100 125 TEMPERATURE (C)
RESET TIMEOUT PERIOD vs. TEMPERATURE
MAX6421/26 toc04
MAXIMUM TRANSIENT DURATION vs. RESET THRESHOLD OVERDRIVE
MAX6421/26 toc05
VCC TO RESET DELAY vs. TEMPERATURE (VCC FALLING)
160 VCC FALLING AT 1mVs 150 VCC TO RESET DELAY (s) 140 130 120 110 100 90 80 1000 -50 -25 0 25 75 50 TEMPERATURE (C) 100 125
600 550 RESET TIMEOUT PERIOD (s) 500 450 400 350 300 250 200 -50 -25 0 25 50 75 100 CSRT = 0
175 150 TRANSIENT DURATION (s) 125 100 75 50 25 VTH = 2.95V 0 RESET OCCURS ABOVE THE CURVE
125
0
200
400
600
800
TEMPERATURE (C)
RESET THRESHOLD OVERDRIVE (mV)
POWER-UP/POWER-DOWN CHARACTERISTIC
MAX6421/26 toc07
NORMALIZED RESET THRESHOLD vs. TEMPERATURE
MAX6421/26 toc08
NORMALIZED RESET THRESHOLD
VCC
VTH = 1.6V
1.006 1.004 1.002 1.000 0.998 0.996 0.994
1V/div
RESET 1V/div 400s/div
-50
-25
0
25
50
75
100
125
TEMPERATURE (C)
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3
Low-Power, SC70/SOT P Reset Circuits with Capacitor-Adjustable Reset Timeout Delay
MAX6340/MAX6421-MAX6426
Pin Description
PIN MAX6340 SOT23 MAX6421 MAX6422 MAX6423 SOT143 SC70 MAX6424 MAX6425 SOT23 MAX6426 SOT23 Set Reset Timeout Input. Connect a capacitor between SRT and ground to set the timeout period. Determine the period as follows: tRP = 2.73 106 CSRT + 275s with tRP in seconds and CSRT in farads. Ground Not Internally Connected. Can be connected to GND. Supply Voltage and Reset Threshold Monitor Input RESET changes from high to low whenever VCC drops below the selected reset threshold voltage. RESET remains low for the reset timeout period after VCC exceeds the reset threshold. RESET changes from low to high whenever VCC drops below the selected reset threshold voltage. RESET remains high for the reset timeout period after VCC exceeds the reset threshold.
3.3V
NAME
FUNCTION
1
3
3
5
1
SRT
2 3 4
1 -- 2
2 -- 1
3 4 2
2, 3 -- 5
GND N.C. VCC
5 4 -- 4
1
4
RESET
--
--
RESET
Detailed Description
Reset Output
The reset output is typically connected to the reset input of a P. A P's reset input starts or restarts the P in a known state. The MAX6340/MAX6421-MAX6426 P supervisory circuits provide the reset logic to prevent code-execution errors during power-up, power-down, and brownout conditions (see Typical Operating Characteristics). RESET changes from high to low whenever VCC drops below the threshold voltage. Once VCC exceeds the threshold voltage, RESET remains low for the capacitoradjustable reset timeout period. The MAX6422 active-high RESET output is the inverse logic of the active-low RESET output. All device outputs are guaranteed valid for VCC > 1V. The MAX6340/MAX6423/MAX6425/MAX6426 are opendrain RESET outputs. Connect an external pullup resistor to any supply from 0 to 5.5V. Select a resistor value large enough to register a logic low when RESET is asserted and small enough to register a logic high while supplying all input current and leakage paths connected to the RESET line. A 10k to 100k pullup is sufficient in most applications.
VCC LASER-TRIMMED RESISTORS
5.0V
VREF RESET
10k 5V SYSTEM
SRT CSRT
RESET TIMEOUT
N
MAX6340 MAX6423 MAX6425 MAX6426
GND
Figure 1. MAX6340/MAX6423/MAX6425/MAX6426 Open-Drain RESET Output Allows Use with Multiple Supplies
Selecting a Reset Capacitor
The reset timeout period is adjustable to accommodate a variety of P applications. Adjust the reset timeout period (tRP) by connecting a capacitor (CSRT) between SRT and ground. Calculate the reset timeout capacitor as follows:
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Low-Power, SC70/SOT P Reset Circuits with Capacitor-Adjustable Reset Timeout Delay
CSRT = (tRP - 275s) / (2.73 106) where tRP is in seconds and CSRT is in farads. The reset delay time is set by a current/capacitor-controlled ramp compared to an internal 0.65V reference. An internal 240nA ramp current source charges the external capacitor. The charge to the capacitor is cleared when a reset condition is detected. Once the reset condition is removed, the voltage on the capacitor ramps according to the formula: dV/dt = I/C. The CSRT capacitor must ramp to 0.65V to deassert the reset. CSRT must be a low-leakage (<10nA) type capacitor; ceramic is recommended.
Applications Information
Interfacing to Other Voltages for Logic Compatibility
The open-drain outputs of the MAX6340/MAX6423/ MAX6425/MAX6426 can be used to interface to Ps with other logic levels. As shown in Figure 1, the open-drain output can be connected to voltages from 0 to 5.5V. This allows for easy logic compatibility to various Ps.
MAX6340/MAX6421-MAX6426
Wired-OR Reset
To allow auxiliary circuitry to hold the system in reset, an external open-drain logic signal can be connected to the open-drain RESET of the MAX6340/MAX6423/ MAX6425/MAX6426, as shown in Figure 2. This configuration can reset the P, but does not provide the reset timeout when the external logic signal is released.
Operating as a Voltage Detector
The MAX6340/MAX6421-MAX6426 can be operated in a voltage detector mode by floating the SRT pin. The reset delay times for VCC rising above or falling below the threshold are not significantly different. The reset output is deasserted smoothly without false pulses.
VCC
VDD 10k
MAX6340 MAX6423 MAX6425 MAX6426
RESET N GND
P
Negative-Going VCC Transients In addition to issuing a reset to the P during power-up, power-down, and brownout conditions, these supervisors are relatively immune to short-duration negative-going transients (glitches). The graph Maximum Transient Duration vs. Reset Threshold Overdrive in the Typical Operating Characteristics shows this relationship. The area below the curve of the graph is the region in which these devices typically do not generate a reset pulse. This graph was generated using a negativegoing pulse applied to VCC, starting above the actual reset threshold (VTH) and ending below it by the magnitude indicated (reset-threshold overdrive). As the magnitude of the transient decreases (farther below the reset threshold), the maximum allowable pulse width decreases. Typically, a VCC transient that goes 100mV below the reset threshold and lasts 50s or less does not cause a reset pulse to be issued. Ensuring a Valid RESET or RESET Down to VCC = 0
RESET
OPEN-DRAIN LOGIC
N
Figure 2. Wired-OR Reset Circuit
When VCC falls below 1V, RESET/RESET current-sinking (sourcing) capabilities decline drastically. In the case of the MAX6421/MAX6424, high-impedance CMOS-logic inputs connected to RESET can drift to undetermined voltages. This presents no problems in most applications, since most Ps and other circuitry do not operate with VCC below 1V. In those applications where RESET must be valid down to zero, adding a pulldown resistor between RESET and ground sinks any stray leakage currents, holding RESET low (Figure 3). The value of the pulldown resistor is not critical; 100k is large enough not to load RESET and small enough to pull RESET to ground. For applications using the MAX6422, a 100k pullup resis5
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Low-Power, SC70/SOT P Reset Circuits with Capacitor-Adjustable Reset Timeout Delay
MAX6340/MAX6421-MAX6426
VCC
Table 1. Reset Threshold Voltage Suffix
SUFFIX 16 MIN 1.536 1.623 1.755 1.853 1.950 2.048 2.133 2.313 2.340 2.438 2.559 2.633 2.730 2.852 2.925 2.998 3.120 3.218 3.315 3.413 3.510 3.608 3.705 3.803 3.900 3.998 4.095 4.193 4.266 4.388 4.509 4.583 4.680 4.778 4.875 TYP 1.575 1.665 1.800 1.900 2.000 2.100 2.188 2.313 2.400 2.500 2.625 2.700 2.800 2.925 3.000 3.075 3.200 3.300 3.400 3.500 3.600 3.700 3.800 3.900 4.000 4.100 4.200 4.300 4.375 4.500 4.625 4.700 4.800 4.900 5.000 MAX 1.614 1.707 1.845 1.948 2.050 2.153 2.243 2.371 2.460 2.563 2.691 2.768 2.870 2.998 3.075 3.152 3.280 3.383 3.485 3.558 3.690 3.793 3.895 3.998 4.100 4.203 4.305 4.408 4.484 4.613 4.741 4.818 4.920 5.023 5.125
VCC
17 18 19 20
MAX6421 MAX6424
RESET GND 100k
21 22 23 24 25 26 27 28 29
100k
Figure 3. Ensuring RESET Valid to VCC = 0
VCC
30 31 32 33 34
VCC
MAX6422
RESET
35 36 37 38 39 40
GND
Figure 4. Ensuring RESET Valid to VCC = 0
41 42 43 44 45 46 47 48 49 50
tor between RESET and VCC holds RESET high when VCC falls below 1V (Figure 4). Open-drain RESET versions are not recommended for applications requiring valid logic for VCC down to zero.
Layout Consideration
SRT is a precise current source. When developing the layout for the application, be careful to minimize board capacitance and leakage currents around this pin. Traces connected to SRT should be kept as short as possible. Traces carrying high-speed digital signals and traces with large voltage potentials should be routed as far from SRT as possible. Leakage current and stray capacitance (e.g., a scope probe) at this pin could cause errors in the reset timeout period. When evaluating these parts, use clean prototype boards to ensure accurate reset periods.
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Low-Power, SC70/SOT P Reset Circuits with Capacitor-Adjustable Reset Timeout Delay
Standard Versions Table
PART* MAX6340UK16-T MAX6340UK22-T MAX6340UK26-T MAX6340UK29-T MAX6340UK46-T MAX6421US16-T MAX6421XS16-T MAX6421US22-T MAX6421XS22-T MAX6421US26-T MAX6421XS26-T MAX6421US29-T MAX6421XS29-T MAX6421US46-T MAX6421XS46-T MAX6422US16-T MAX6422XS16-T MAX6422US22-T MAX6422XS22-T MAX6422US26-T MAX6422XS26-T MAX6422US29-T MAX6422XS29-T MAX6422US46-T MAX6422XS46-T OUTPUT STAGE Open-Drain RESET Open-Drain RESET Open-Drain RESET Open-Drain RESET Open-Drain RESET Push-Pull RESET Push-Pull RESET Push-Pull RESET Push-Pull RESET Push-Pull RESET Push-Pull RESET Push-Pull RESET Push-Pull RESET Push-Pull RESET Push-Pull RESET Push-Pull RESET Push-Pull RESET Push-Pull RESET Push-Pull RESET Push-Pull RESET Push-Pull RESET Push-Pull RESET Push-Pull RESET Push-Pull RESET Push-Pull RESET TOP MARK AEBE AEBG AEBI AEBJ AEBM KADA ACU KADE ACY KADG ADA KADH ADB KADK ADE KABD ACV KADM ADG KADO ADI KADP ADJ KADS ADM PART* MAX6423US16-T MAX6423XS16-T MAX6423US22-T MAX6423XS22-T MAX6423US26-T MAX6423XS26-T MAX6423US29-T MAX6423XS29-T MAX6423US46-T MAX6423XS46-T MAX6424UK16-T MAX6424UK22-T MAX6424UK26-T MAX6424UK29-T MAX6424UK46-T MAX6425UK16-T MAX6425UK22-T MAX6425UK26-T MAX6425UK29-T MAX6425UK46-T MAX6426UK16-T MAX6426UK22-T MAX6426UK26-T MAX6426UK29-T MAX6426UK46-T OUTPUT STAGE Open-Drain RESET Open-Drain RESET Open-Drain RESET Open-Drain RESET Open-Drain RESET Open-Drain RESET Open-Drain RESET Open-Drain RESET Open-Drain RESET Open-Drain RESET Push-Pull RESET Push-Pull RESET Push-Pull RESET Push-Pull RESET Push-Pull RESET Open-Drain RESET Open-Drain RESET Open-Drain RESET Open-Drain RESET Open-Drain RESET Open-Drain RESET Open-Drain RESET Open-Drain RESET Open-Drain RESET Open-Drain RESET TOP MARK KADC ADUF KADU ADUK KADW ADUM KADX ADUN KAEA ADUQ ADUF ADUK ADUM ADUN ADUQ ADUG ADUS ADUU ADUV ADUY ADUH ADVA ADVC ADVD ADVG
MAX6340/MAX6421-MAX6426
Typical Operating Circuit
VCC
*Sample stock is generally held on all standard versions. Contact factory for availability of nonstandard versions.
VCC LASER-TRIMMED RESISTORS
P VREF
RESET SRT CSRT GND RESET TIMEOUT
RESET
MAX6421 MAX6424
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7
Low-Power, SC70/SOT P Reset Circuits with Capacitor-Adjustable Reset Timeout Delay
MAX6340/MAX6421-MAX6426
Pin Configurations (continued)
TOP VIEW
SRT 1 5 RESET RESET 1 5 SRT
GND 2
MAX6340
VCC 2
MAX6424 MAX6425
4 N.C.
N.C. 3
4 VCC
GND 3
SOT23
SOT23
GND 1
4
MAX6421U MAX6422U MAX6423U
VCC 2 3
RESET (RESET)
SRT
1
5
VCC
GND 2 SRT GND 3
MAX6426
SOT143
4
RESET
SOT23
Selector Guide
PART MAX6340 MAX6421 MAX6422 MAX6423 MAX6424 MAX6425 PUSH-PULL RESET -- -- -- -- PUSH-PULL RESET -- -- -- -- -- OPEN-DRAIN RESET -- -- -- PIN-PACKAGE 5 SOT23 4 SOT143/SC70 4 SOT143/SC70 4 SOT143/SC70 5 SOT23 5 SOT23
Chip Information
TRANSISTOR COUNT: 295 PROCESS: BiCMOS
8
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Low-Power, SC70/SOT P Reset Circuits with Capacitor-Adjustable Reset Timeout Delay
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
SC70, 4L.EPS
MAX6340/MAX6421-MAX6426
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9
Low-Power, SC70/SOT P Reset Circuits with Capacitor-Adjustable Reset Timeout Delay
MAX6340/MAX6421-MAX6426
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
10 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
SOT5L.EPS

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