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IMP705/6/7/8, 8 13L
POWER MANAGEMENT
Low-Power P Supervisor Circuits
- Watc hdog timer - Br o wnout det ection - Po w er suppl y monit or
The IMP705/706/707/708 and IMP813L CMOS supervisor circuits monitor power-supply and battery voltage level, and P/C operation. Compared to pin-compatible devices offered by Maxim Integrated Products, IMP devices feature 60 percent lower maximum supply current. The family offers several functional options. Each device generates a reset signal during power-up, power-down and during brownout conditions. A reset is generated when the supply drops below 4.65V (IMP705/707/813L) or 4.40V (IMP706/708). For 3V power supply applications, refer to the IMP705P/R/S/T data sheet. In addition, the IMP705/706/813L feature a 1.6 second watchdog timer. The IMP707/708 have both active-HIGH and active-LOW reset outputs but no watchdog function. The IMP813L has the same pin-out and functions as the IMP705 but has an active-HIGH reset output. A versatile power-fail circuit has a 1.25V threshold, useful in checking battery levels and non-5V supplies. All devices have a manual reset (MR) input. The watchdog timer output will trigger a reset if connected to MR. All devices are available in 8-pin DIP, SO and MicroSO packages.
Key Features
N Improved replacements for the Maxim MAX705/6/7/8, MAX813L - 140A maximum supply current - 60% improvement N Precision power supply monitor - 4.65V threshold (IMP705/707/813L) - 4.40V threshold (IMP706/8) N Debounced manual reset input N Voltage monitor - 1.25V threshold - Battery monitor/Auxiliary supply monitor N Watchdog timer (IMP705/706/813L) N 200ms reset pulse width N Active HIGH reset output (IMP707/708/813L) N MicroSO package
Applications
N N N N N Computers and embedded controllers Battery-operated systems Intelligent instruments Wireless communication systems PDAs and handheld equipment
Block Diagrams
WDI
VCC
Transition Detector
Watchdog Timer
WDO RESET
VCC
0.25mA
Timebase
0.25mA
MR VCC + + -
RESET Generator
RESET (RESET) (IMP813L)
MR VCC + + -
4.65V (IMP707) 4.40V (IMP708)
RESET Generator
RESET
4.65V (IMP705/813L) 4.40V (IMP706)
PFI
+
IMP705 IMP706 IMP813L
1.25V
-
PFO
PFI
1.25V
+ PFO -
IMP707 IMP708
GND
705_01.eps 705_02.eps
GND
(c) 1999 IMP, Inc.
408-432-9100/www.impweb.com
1
IMP705/6/7/8, 8 13L
Pin Configuration
DIP/SO
MR VCC GND PFI 1 2 3 4 IMP707 IMP708 8 7 6 5 RESET RESET NC PFO MR VCC GND PFI 1 2 3 4 IMP705 IMP706 (IMP813L) 8 7 6 5 WDO RESET (RESET) WDI PFO RESET RESET MR VCC 1 2 3 4 IMP707 IMP708 8 7 6 5
MicroSO
NC PFO PFI GND RESET (RESET) WDO MR VCC 1 2 3 4 IMP705 IMP706 (IMP813L) 8 7 6 5 WDI PFO PFI GND
705_03.eps
Ordering Information
Part Number Reset Threshold (V) Temperature Range IMP705 Active LOW Reset, Watchdog Output and Manual RESET
IMP705CPA IMP705CSA IMP705CUA IMP705C/D IMP705EPA IMP705ESA IMP706ESA IMP706CPA IMP706CSA IMP706CUA IMP706C/D IMP706EPA IMP706ESA IMP707CPA IMP707CSA IMP707CUA IMP707C/D IMP707EPA IMP707ESA IMP708CPA IMP708CSA IMP708CUA IMP708C/D IMP708EPA IMP708ESA IMP813LCPA IMP813LCSA IMP813LCUA IMP813LC/D IMP813LEPA IMP813LESA 4.65 4.65 4.65 4.65 4.65 4.65 4.40 4.40 4.40 4.40 4.40 4.40 4.40 4.65 4.65 4.65 4.65 4.65 4.65 4.40 4.40 4.40 4.40 4.40 4.40 4.65 4.65 4.65 4.65 4.65 4.65 0C to +70C 0C to +70C 0C to +70C 25C -40C to +85C -40C to +85C -40C to +85C 0C to +70C 0C to +70C 0C to +70C 25C -40C to +85C -40C to +85C 0C to +70C 0C to +70C 0C to +70C 25C -40C to +85C -40C to +85C 0C to +70C 0C to +70C 0C to +70C 25C -40C to +85C -40C to +85C 0C to +70C 0C to +70C 0C to +70C 25C -40C to +85C -40C to +85C
Pins-Package
8-Plastic DIP 8-SO 8-MicroSO Dice 8-Plastic DIP 8-SO 8-SO 8-Plastic DIP 8-SO 8-MicroSO Dice 8-Plastic DIP 8-SO 8-Plastic DIP 8-SO 8-MicroSO Dice 8-Plastic DIP 8-SO 8-Plastic DIP 8-SO 8-MicroSO Dice 8-Plastic DIP 8-SO 8-Plastic DIP 8-SO 8-MicroSO Dice 8-Plastic DIP 8-SO
IMP706 Active LOW Reset, Watchdog Output and Manual RESET
IMP707 Active LOW & HIGH Reset with Manual RESET
IMP708 Active LOW & HIGH Reset with Manual RESET
IMP813L Active HIGH Reset, Watchdog Output and Manual RESET
2
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(c) 1999 IMP, Inc.
IMP705/6/7/8, 8 13L
Absolute Maximum Ratings
Pin Terminal Voltage with Respect to Ground VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V All other inputs1 . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to (VCC + 0.3V) Input Current at VCC and GND . . . . . . . . . . 20mA Output Current: All outputs . . . . . . . . . . . . . 20mA Rate of Rise at VCC . . . . . . . . . . . . . . . . . . . . . 100V/s Plastic DIP Power Dissipation . . . . . . . . . . . 700 mW (Derate 9 mW/C above 70C) SO Power Dissipation . . . . . . . . . . . . . . . . . 470 mW (Derate 5.9 mW/C above 70C) MicroSO Power Dissipation . . . . . . . . . . . . . 330mW (Derate 4.1 mW/C above 70C) Operating Temperature Range IMP705E/706E/707E/708E/813LE . . . . . . . -40C to 85C IMP706C/707C/708C/813LC . . . . . . . . . . . 0C to 70C Storage Temperature Range . . . . . . . . . . . . . . -65C to 160C Lead Temperature Soldering(10 sec) . . . . . . 300C Note: 1. The input voltage limits on PFI and MR can be exceeded if the input current is less than 10mA. These are stress ratings only and functional operation is not implied.
Electrical Characteristics
Unless otherwise noted, VCC = 4.75V to 5.5V for the IMP705/707/813L. VCC = 4.5V to 5.5V for the IMP706/708 and over the operating temperature range.
Parameter
Operating Voltage Range
Symbol
VCC
Conditions
IMP705/6/7/8C IMP813L IMP705/6/7/8E, IMP813lE IMP705C/706C/813LC IMP705E, IMP706E, IMP813LE IMP707C, IMP708C IMP707E, IMP708E IMP705, IMP707, IMP813L, Note 2 IMP706, IMP708, Note 2 Note 2 Note 2 Note 2
Min
1.2 1.1 1.2
Typ
Max
5.5 5.5 5.5 140 140 140 140 4.75 4.50 280 0.25
Units
V
Supply Current
ICC
RESET Threshold RESET Threshold Hysteresis RESET Pulse Width MR Pulse Width MR to RESET Out Delay MR Input Threshold MR Pull-up Current RESET Output Voltage
VRT
4.50 4.25 140 0.15 2.0
tRS tMR tMD VIH VIL
75 75 50 50 4.65 4.40 40 200
A
V mV ms s s V A V
RESET Output Voltage
Watchdog Timeout Period WDI Pulse Width WDI Input Threshold WDI Input Current WDO Output Voltage PFI Input Threshold PFI Input Current PFO Output Voltage
tWD tWP VIH VIL
MR = 0V ISOURCE = 800A ISINK = 3.2mA IMP705/6/7/8, VCC = 1.2V, ISINK = 100A IMP707/708/813L, ISOURCE = 800A IMP707/708, ISINK = 1.2mA IMP813L, ISINK = 3.2mA IMP813L, VCC =1.2V, ISOURCE = 4A IMP705/706/813L VIL = 0.4V, VIH = 0.8VCC IMP705/706/813L, VCC = 5V IMP705/706/813L, WDI = VCC IMP705/706/813L, WDI = 0V IMP705/706/813L, ISOURCE = 800A IMP705/706/813L, ISINK = 1.2mA VCC = 5V ISOURCE = 800A ISINK = 3.2mA
100 VCC - 1.5V
250
0.8 600 0.4 0.3
VCC - 1.5V 0.4 0.4 0.9 1.00 50 3.5 1.60 2.25
V
s ns V A V
-150 VCC - 1.5V 1.2 - 25 VCC - 1.5V
50 - 50
0.8 150
1.25 0.01
0.4 1.3 25 0.4
V nA V
Notes: 2. RESET (IMP705/6/7/8), RESET (IMP707/8, IMP813L)
(c) 1999 IMP, Inc.
408-432-9100/www.impweb.com
3
IMP705/6/7/8, 8 13L
Pin Descriptions
Pin Number IMP705/706 IMP707/708 IMP813L DIP/SO MicroSO DIP/SO MicroSO DIP/SO MicroSO Name
1 2 3 4 5 3 4 5 6 7 1 2 3 4 5 3 4 5 6 7 1 2 3 4 5 3 4 5 6 7 MR VCC GND PFI PFO
Function
Manual RESET input. The active LOW input triggers a reset pulse. A 250A pull-up current allows the pin to be driven by TTL / CMOS logic or shorted to ground with a switch. +5V power supply input. Ground reference for all signals. Power-fail voltage monitor input. With PFI less than 1.25V, PFO goes low. Connect PFI to ground or VCC when not used. Power-fail output. The output is active LOW and sinks current when PFI is less than 1.25V. Watchdog input. WDI controls the internal watchdog timer. A HIGH or LOW signal for 1.6sec at WDI allows the internal timer to run-out, setting WDO LOW. The watchdog function is disabled by floating WDI or by connecting WDI to a high-impedance three-state buffer. The internal watchdog timer clears when: RESET is asserted; WDI is three-stated; or WDI sees a rising or falling edge. Not connected. Active-LOW reset output. Pulses LOW for 200ms when triggered, and stays low whenever VCC is below the reset threshold (IMP705: 4.65V, IMP705J: 4.00V, IMP706: 4.40V). RESET remains LOW for 200ms after VCC rises above the RESET threshold or MR goes from LOW to HIGH. A watchdog timeout will not trigger RESET unless WDO is connected to MR. Watchdog output. WDO pulls LOW when the 1.6 sec internal watchdog timer times-out and does not go HIGH until the watchdog is cleared. In addition, when VCC is below the reset threshold, WDO remains low. Unlike RESET, WDO does not have a minimum pulse width and as soon as VCC exceeds the reset threshold, WDO goes HIGH with no delay. Active-HIGH reset output. RESET is the inverse of RESET. The IMP813L has only a RESET output.
6
8
--
--
6
8
WDI
--
--
6
--
--
--
NC
7
1
7
1
--
--
RESET
8
2
--
--
8
2
WDO
--
--
8
2
7
1
RESET
Feature Summary
IMP705
Power-fail detector Brownout detection Manual RESET input Power-up/down RESET Watchdog timer Active-HIGH RESET output Active-LOW RESET output RESET threshold
4
IMP706
I I I I I I 4.40V
IMP707
I I I I I I 4.65V
IMP708
I I I I I I 4.40V
IMP813L
I I I I I I 4.65V
(c) 1999 IMP, Inc.
I I I I I I 4.65V/4.00V
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IMP705/6/7/8, 8 13L
Detail Descriptions
RESET/RESET Operation
The RESET/RESET signals are designed to start a P/C in a known state or return the system to a known state. The IMP707/708 have two RESET outputs, one active-HIGH RESET and one active-LOW RESET output. The IMP813L has only an active-HIGH output. RESET is simply the complement of RESET. RESET is guaranteed to be LOW with VCC above 1.2V. During a power-up sequence, RESET remains low until the supply rises above the threshold level, either 4.65V, 4.40V or 4.00V. RESET goes . high approximately 200ms after crossing the threshold. During power-down, RESET goes LOW as VCC falls below the threshold level and is guaranteed to be under 0.4V with VCC above 1.2V. In a brownout situation where VCC falls below the threshold level, RESET pulses low. If a brownout occurs during an alreadyinitiated reset, the pulse will continue for a minimum of 140ms.
Manual Reset (MR)
The active-LOW manual reset input is pulled high by a 250A pull-up current and can be driven low by CMOS/TTL logic or a mechanical switch to ground. An external debounce circuit is unnecessary since the 140ms minimum reset time will debounce mechanical pushbutton switches. By connecting the watchdog output (WDO) and MR, a watchdog timeout forces RESET to be generated. The IMP813L should be used when an active-HIGH RESET is required.
Watchdog Timer
The watchdog timer available on the IMP705/706/813L monitors P/C activity. If activity is not detected within 1.6 seconds, the internal timer puts the watchdog output, WDO, into a LOW state. WDO will remain LOW until activity is detected at WDI. The watchdog function is disabled, meaning it is cleared and not counting, if WDI is floated or connected to a three-stated circuit. The watchdog timer is also disabled if RESET is asserted. When RESET becomes inactive and the WDI input sees a high or low transition as short as 50ns, the watchdog timer will begin a 1.6 second countdown. Additional transitions at WDI will reset the watchdog timer and initiate a new countdown sequence. WDO will also become LOW and remain so, whenever the supply voltage, VCC , falls below the device threshold level. WDO goes HIGH as soon as VCC transitions above the threshold. There is no minimum pulse width for WDO as there is for the RESET outputs. If WDI is floated, WDO essentially acts as a low-power output indicator.
Auxiliary Comparator
All devices have an auxiliary comparator with 1.25V trip point and uncommitted output (PFO) and noninverting input (PFI). This comparator can be used as a supply voltage monitor with an external resistor voltage divider. The attenuated voltage at PFI should be set just below the 1.25 threshold. As the supply level falls, PFI is reduced causing the PFO output to transit LOW. Normally PFO interrupts the processor so the system can be shut down in a controlled manner.
5V
VCC
0V
vRT tRS tRS
5V
WDI
0V tWD tWP tWD
5V
5V
RESET
0V
WDO
0V tWD
5V
5V MR extermally set low tMD tMR
MR
0V
RESET
0V
RESET triggered by MR tRS
5V
WDO
0V
705_04.eps
(RESET) IMP813L 0V
705_05.eps
5V
Figure 1. WDI Three-state operation
Figure 2. Watchdog Timing
(c) 1999 IMP, Inc.
408-432-9100/www.impweb.com
5
IMP705/6/7/8, 8 13L
Application Information
Ensuring That RESET is Valid Down to VCC = 0V
When VCC falls below 1.1V, the IMP705-708 RESET output no longer pulls down; it becomes indeterminate. To avoid the possibility that stray charges build up and force RESET to the wrong state, a pull-down resistor should be connected to the RESET pin, thus draining such charges to ground and holding RESET low. The resistor value is not critical. A 100k resistor will pull RESET to ground without loading it.
VCC < 1.1V VCC VCC
Bi-directional Reset Pin Interfacing
The IMP705/6/7/8 can interface with P/C bi-directional reset pins by connecting a 4.7k resistor in series with the RESET output and the P/C bi-directional RESET pin.
BUF Buffered RESET
IMP70x
100k9 RESET GND
Power Supply
IMP70x
4.7k RESET GND
Bi-directional I/O Pin (Example: 68HC11)
C or P RESET Input GND
705_08.eps 705_06.eps
Figure 3. Ensuring That RESET is Valid Down to VCC = 0V
Figure 3. Bi-directional Reset Pin Interfacing
6
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(c) 1999 IMP, Inc.
IMP705/6/7/8, 8 13L
Application Information
Monitoring Voltages Other Than VCC
The IMP705-708 can monitor voltages other than VCC using the Power Fail circuitry. If a resistive divider is connected from the voltage to be monitored to the Power Fail input, PFI, the PFO (output) will go LOW if the divider voltage goes below its 1.25V reference. Should hysteresis be desired, connect a resistor (equal to approximately 10 times the sum of the two resistors in the divider) between the PFI and PFO pins. A capacitor between PFI and GND will reduce circuit sensitivity to input high-frequency noise. If it is desired to assert a RESET in addition to the PFO flag, this may be achieved by connecting the PFO output to MR.
Monitoring a Negative Voltage
The Power-Fail circuitry can also monitor a negative supply rail. When the negative rail is OK, PFO will be LOW, and when the negative rail is failing (not negative enough), PFO goes HIGH (the opposite of when positive voltages are monitored). To trigger a reset, these outputs need to be inverted: adding the resistors and transistor as shown achieves this. The RESET output will then have the same sense as for positive voltages: good = HIGH, bad = LOW. It should be noted that this circuit's accuracy depends on the VCC line, the PFI threshold tolerance, and the resistors.
+5V
VCC = 5V VCC MR
+ VCC MR
VIN = 12V
IMP70x
PFO
RP
IMP70x
PFO
1M9 PFI 130k9 RESET GND To Processor 12V Threshold ~10.87V
RN -- Negative Input Voltage PFI RESET GND 5 - 1.25 1.25 - VTRIP = RP RN
705_09.eps
705_07.eps
Figure 4. Monitoring Voltages Other Than VCC
Figure 5. Monitoring a Negative Voltage
(c) 1999 IMP, Inc.
408-432-9100/www.impweb.com
7
IMP705/6/7/8, 8 13L
Package Dimensions
Plastic DIP (8-Pin)*
D1
Inches Min
A A1 ----- 0.015 0.115 0.014 0.045 0.030 0.355 0.005 0.300 0.240 0.100 0.300 ----- ----- 0.115 ----- 0.0020 0.0295 0.0098 0.0051 0.1142
Millimeters Max Min Max Plastic DIP (8-Pin)
0.210 ----- 0.195 0.022 0.070 0.045 0.400 ----- 0.325 0.280 ----- ----- 0.430 0.060 0.150 0.0433 0.0059 0.0374 0.0157 0.0091 0.1220 2.92 ---- 0.050 0.75 0.25 0.13 2.90 0.65 BSC 4.90 BSC 2.90 0.40 0 3.10 0.70 6 1.75 0.25 0.51 0.25 1.27 0.157 0.244 0.050 0.197 3.80 5.80 0.40 4.80 4.00 6.20 1.27 5.00 3.81 1.10 0.15 0.95 0.40 0.23 3.10 ----- ---- 0.38 2.92 0.36 1.14 0.80 9.02 0.13 7.62 6.10 2.54 7.62 10.92 5.33 ----- 4.95 0.56 1.78 1.14 10.16 ----- 8.26 7.11
E D A A2 E1
A2 b b2 b3
L A1 e b b2
0-15 C eA eB
Plastic DIP (8-Pin)a.eps
D D1 E E1 e eA
MicroSO (8-Pin)**
a
eB eC L A
MicroSO (8-Pin)
E1 E
A1 A2 b
+
C
L
D e E E1
D A2 A e b A1
0.10mm 0.004in
C
0.0256 BSC 0.193 BSC 0.1142 0.0157 0 0.053 0.004 0.013 0.007 0.050 0.150 0.228 0.016 0.189 0.1220 0.0276 6 0.069 0.010 0.020 0.010
D
MicroSO (8-Pin).eps
L a A
SO (8-Pin)***
0- 8
SO (8-Pin)
1.35 0.10 0.33 0.19 A1 B
L
C e E
E
H
H L D
C
D A
* JEDEC Drawing MS-001BA ** JEDEC Drawing MO-187AA *** JEDEC Drawing MS-012AA
e B A1
SO (8-Pin).eps
8
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(c) 1999 IMP, Inc.
IMP705/6/7/8, 8 13L
IMP, Inc. Corporate Headquarters 2830 N. First Street San Jose, CA 95134-2071 Tel: 408-432-9100 Tel: 800-438-3722 Fax: 408-434-0335 e-mail: info@impinc.com http://www.impweb.com
The IMP logo is a registered trademark of IMP, Inc. All other company and product names are trademarks of their respective owners.
(c) 1999 IMP, Inc. Printed in USA Publication #: 1017 Revision: A Issue Date: 08/17/99 Type: Preliminary

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