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CMOS Static RAM 256K (32K x 8-Bit)
IDT71256SA
x x
Features
32K x 8 advanced high-speed CMOS static RAM Commercial (0 to 70C) and Industrial (-40 to 85C) temperature options Equal access and cycle times - Commercial and Industrial: 12/15/20/25ns One Chip Select plus one Output Enable pin Bidirectional data inputs and outputs directly TTL-compatible Low power consumption via chip deselect Commercial product available in 28-pin 300- and 600-mil Plastic DIP, 300 mil Plastic SOJ and TSOP packages Industrial product available in 28-pin 300 mil Plastic SOJ and TSOP packages
Description
The IDT71256SA is a 262,144-bit high-speed Static RAM organized as 32K x 8. It is fabricated using IDT's high-perfomance, high-reliability CMOS technology. This state-of-the-art technology, combined with innovative circuit design techniques, provides a cost-effective solution for high-speed memory needs. The IDT71256SA has an output enable pin which operates as fast as 6ns, with address access times as fast as 12ns. All bidirectional inputs and outputs of the IDT71256SA are TTL-compatible and operation is from a single 5V supply. Fully static asynchronous circuitry is used, requiring no clocks or refresh for operation. The IDT71256SA is packaged in 28-pin 300- and 600-mil Plastic DIP, 28-pin 300 mil Plastic SOJ and TSOP.
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Functional Block Diagram
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14
ADDRESS DECODER
262,144-BIT MEMORY ARRAY
,
I/O0 - I/O7
8
8
I/O CONTROL
2948 drw 01
CS WE OE
CONTROL LOGIC
FEBRUARY 2001
1
(c)2000 Integrated Device Technology, Inc. DSC-2948/07
IDT71256SA CMOS Static RAM 256K (32K x 8-Bit)
Commercial and Industrial Temperature Ranges
Pin Configurations
A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15
Absolute Maximum Ratings(1)
Symbol Rating Supply Voltage Relative to GND Terminal Voltage Relative to GND Temperature Under Bias Storage Temperature Power Dissipation DC Output Current Value -0.5 to +7.0 -0.5 to VCC+0.5 -55 to +125 -55 to +125 1.0 50 Unit V V
o
SO28-5 P28-2 P28-1
VCC WE A13 A8 A9 A11 OE A10 CS I/O7 I/O6 I/O5 I/O4 I/O3
2948 drw 02
VCC VTERM TBIAS TSTG PT IOUT
C C
o
W mA
2948 tbl 02
,
DIP/SOJ Top View
OE A11 A9 A8 A13 WE VCC A14 A12 A7 A6 A5 A4 A3
22 23 24 25 26 27 28 1 2 3 4 5 6 7 21 20 19 18 17 16 15 14 13 12 11 10 9 8
NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
SO28-8
A10 CS I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2
Truth Table(1,2)
CS L OE L X H X X WE H L H X X I/O DATAOUT DATAIN High-Z High-Z High-Z Function Read Data Write Data Outputs Disabled Deselected - Standby (ISB) Deselecte d - Standby (ISB1)
2948 tbl 03
,
L L H VHC(3)
2948 drw 02a
TSOP Top View
NOTES: 1. H = VIH, L = VIL, x = Don't care. 2. VLC = 0.2V, VHC = VCC -0.2V. 3. Other inputs VHC or VLC.
Recommended Operating Temperature and Supply Voltage
Grade Commercial Industrial Temperature 0OC to +70OC -40OC to +85OC GND 0V 0V Vcc 4.5V 5.5V 4.5V 5.5V
2948 tbl 01
Recommended DC Operating Conditions
Symbol VCC GND VIH VIL Parameter Supply Voltage Ground Input High Voltage Input Low Voltage Min. 4.5 0 2.2 -0.5(1) Typ. 5.0 0
____
Max. 5.5 0 VCC +0.5 0.8
Unit V V V V
2948 tbl 04
____
NOTE: 1. VIL (min.) = -1.5V for pulse width less than 10ns, once per cycle.
2
IDT71256SA CMOS Static RAM 256K (32K x 8-Bit)
Commercial and Industrial Temperature Ranges
DC Electrical Characteristics
(VCC = 5.0V 10%)
Symbol |ILI| |ILO| VOL VOH IDT71256SA Parameter Input Leakage Current Output Leakage Current Output Low Voltage Output High Voltage Test Conditions VCC = Max., VIN = GND to VCC VCC = Max., CS = VIH, VOUT = GND to VCC IOL = 8mA, VCC = Min. IOH = -4mA, VCC = Min. Min.
___ ___ ___
Max. 5 5 0.4
___
Unit A A V V
2948 tbl 05
2.4
DC Electrical Characteristics(1)
Symbol ICC ISB ISB1 Parameter Dynamic Operating Current CS < VIL, Outputs Open, VCC = Max., f = fMAX(2) Standby Power Supply Current (TTL Level) CS > VIH, Outputs Open, VCC = Max., f = fMAX(2) Standby Power Supply Current (CMOS Level) CS > VHC, Outputs Open, VCC = Max., f = 0(2), VIN < VLC or VIN > VHC
(VCC = 5.0V 10%, VLC = 0.2V, VHC = VCC0.2V)
71256SA12 160 50 15 71256SA15 150 40 15 71256SA20 145 40 15 71256SA25 145 40 15 Unit mA mA mA
NOTES: 1. All values are maximum guaranteed values. 2. fMAX = 1/tRC (all address inputs are cycling at fMAX); f = 0 means no address input lines are changing.
2948 tbl 06
AC Test Conditions
Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels AC Test Load GND to 3.0V 3ns 1.5V 1.5V See Figures 1 and 2
2948 tbl 07
(TA = +25C, f = 1.0MHz, SOJ package)
Symbol CIN CI/O Parameter(1) Input Capacitance I/O Capacitance Conditions VIN = 3dV VOUT = 3dV Max. 7 7 Unit pF pF
2948 tbl 08
Capacitance
NOTE: 1. This parameter is guaranteed by device characterization, but not production tested.
5V 480 DATA OUT 30pF* 255
2948 drw 03
5V 480 DATA OUT 5pF* 255
,
6.42 3
.
2948 drw 04
Figure 1. AC Test Load *Including jig and scope capacitance.
Figure 2. AC Test Load (for tCLZ, tOLZ, tCHZ, tOHZ, tOW, and tWHZ)
IDT71256SA CMOS Static RAM 256K (32K x 8-Bit)
Commercial and Industrial Temperature Ranges
AC Electrical Characteristics
Symbol Parameter
(VCC = 5.0V 10%)
71256SA12 Min. Max. 71256SA15 Min. Max. 71256SA20 Min. Max. 71256SA25 Min. Max. Unit
Read Cycle
tRC tAA tACS tCLZ(1) tCHZ(1) tOE tOLZ(1) tOHZ(1) tOH tPU(1) tPD(1) Read Cycle Time Address Access Time Chip Select Access Time Chip Select to Output in Low-Z Chip Sele ct to Output in High-Z Output Enable to Output Valid Output Enab le to Output in Low-Z Output Disab le to Output in High-Z Output Hold from Address Change Chip Sele ct to Power Up Time Chip Deselect to Power Down Time 12
____ ____
15
____
____
20
____
____
25
____
____
ns ns ns ns ns ns ns ns ns ns ns
12 12
____
15 15
____
20 20
____
25 25
____
____
____
____
____
4 0
____
4 0
____
4 0
____
4 0
____
6 6
____
7 7
____
10 10
____
11 11
____
0 0 3 0
____
0 0 3 0
____
0 0 3 0
____
0 0 3 0
____
6
____
6
____
8
____
10
____
____
____
____
____
12
15
20
25
Write Cycle
tWC tAW tCW tAS tWP tWR tDW tDH tOW(1) tWHZ(1) Write Cycle Time Address Valid to End-of-Write Chip Select to End-of-Write Address Set-up Time Write Pulse Width Write Recovery Time Data Valid to End-of-Write Data Hold Time Output Active from End-of-Write Write Enab le to Output in High-Z 12 9 9 0 8 0 6 0 4 0
____ ____ ____ ____ ____ ____ ____ ____
15 10 10 0 10 0 7 0 4 0
____ ____ ____ ____ ____ ____ ____ ____
20 15 15 0 15 0 11 0 4 0
____ ____ ____ ____ ____ ____ ____ ____
25 20 20 0 20 0 13 0 4 0
____ ____ ____ ____ ____ ____ ____ ____
ns ns ns ns ns ns ns ns ns ns
2948 tbl 09
____
____
____
____
6
6
10
11
NOTE: 1. This parameter is guaranteed with the AC Load (Figure 2) by device characterization, but is not production tested.
4
IDT71256SA CMOS Static RAM 256K (32K x 8-Bit)
Commercial and Industrial Temperature Ranges
Timing Waveform of Read Cycle No. 1(1)
tRC ADDRESS tAA OE tOE CS tOLZ
(5)
tACS tCLZ DATAOUT ICC ISB
(5)
(3)
tOHZ tCHZ
(5)
(5)
HIGH IMPEDANCE tPU
DATA OUT VALID tPD
VCC SUPPLY CURRENT
2948 drw 05
,
Timing Waveform of Read Cycle No. 2(1,2,4)
tRC ADDRESS tAA tOH DATAOUT PREVIOUS DATAOUT VALID tOH DATAOUT VALID
2948 drw 06
,
NOTES: 1. WE is HIGH for Read Cycle. 2. Device is continuously selected, CS is LOW. 3. Address must be valid prior to or coincident with the later of CS transition LOW; otherwise tAA is the limiting parameter. 4. OE is LOW. 5. Transition is measured 200mV from steady state.
6.42 5
IDT71256SA CMOS Static RAM 256K (32K x 8-Bit)
Commercial and Industrial Temperature Ranges
Timing Waveform of Write Cycle No. 1 (WE Controlled Timing)(1,2,4)
tWC ADDRESS tAW CS tAS WE tWHZ (5) DATAOUT
(3)
tWP (2)
tWR
tOW HIGH IMPEDANCE tDW tDH
(5)
tCHZ (5)
(3)
DATAIN
DATAIN VALID
2948 drw 07
,
Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)(1,4)
tWC ADDRESS tAW CS tAS WE tDW DATAIN DATAIN VALID
2948 drw 08
tCW
tWR
tDH
,
NOTES: 1. A write occurs during the overlap of a LOW CS and a LOW WE. 2. OE is continuously HIGH. If during a WE controlled write cycle OE is LOW, tWP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse is as short as the specified tWP. 3. During this period, I/O pins are in the output state, and input signals must not be applied. 4. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state. 5. Transition is measured 200mV from steady state.
6
IDT71256SA CMOS Static RAM 256K (32K x 8-Bit)
Commercial and Industrial Temperature Ranges
Ordering Information Commercial
IDT 71256 Device Type SA Power XX Speed XXX Package X Process/ Temperature Range Blank Commercial (0C to +70C)
P TP Y PZ
600-mil Plastic DIP (P28-1) only 25ns available 300-mil Plastic DIP (P28-2) 300-mil SOJ (SO28-5) TSOP Type I (SO28-8)
12 15 20 25
Speed in nanoseconds
,
2948 drw 09
Ordering Information Industrial
IDT 71256 Device Type SA Power XX Speed XXX Package X Process/ Temperature Range
I
Industrial (-40C to +85C)
Y PZ
300-mil SOJ (SO28-5) TSOP Type I (SO28-8)
12 15 20 25
,
Speed in nanoseconds
2948 drw 10
6.42 7
IDT71256SA CMOS Static RAM 256K (32K x 8-Bit)
Commercial and Industrial Temperature Ranges
Datasheet Document History
1/7/00 Pp. 1, 3, 4, 7 Pg. 6 Pg. 8 08/09/00 02/01/01 Updated to new format Revised Industrial Temperature range offerings Removed Note No. 1 for Write Cycle diagrams, renumbered footnotes and notes Added Datasheet Document History Not recommended for new designs Removed "Not recommended for new designs"
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for Tech Support: sramhelp@idt.com 800 544-7726, x4033
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
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