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4 Megabit (512K x 8) SuperFlash MTP
SST27VF040
Preliminary Specifications
FEATURES: * 2.7 to 3.6 Volt Read Operation * Superior Reliability - Endurance: Greater than 1000 Cycles - Greater than 100 years Data Retention * Low Power Consumption - Active Current: 10 mA (typical) - Standby Current: 10 A (typical) * Fast Access Time - 90 and 120 ns * Fast Programming Operation - 10 s Programming Pulse - Chip Programming Time of 7 seconds
* Features Electrical Erase - Does Not Require UV Source - Chip Erase Time: 100 ms * CMOS I/O Compatibility * JEDEC Standard Byte-wide EPROM Pinouts * 12V Power Supply for Programming/Erase * Packages Available - 32-Pin PLCC - 32-Pin Plastic DIP - 32-Pin TSOP (8mm x 14mm)
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PRODUCT DESCRIPTION The SST27VF040 is a 512K x 8 CMOS, many-time programmable (MTP) low cost flash, manufactured with SST's proprietary, high performance CMOS SuperFlash technology. The split gate cell design and thick oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The SST27VF040 can be electrically erased and programmed at least 1000 times using an external programmer, e.g., to change the contents of devices in inventory. The SST27VF040 has to be erased prior to programming. The SST27VF040 conforms to JEDEC standard pinouts for byte-wide memories. Featuring high performance byte programming, the SST27VF040 uses a programming pulse of 10 s. The entire memory can be programmed byte by byte in 7 seconds. Designed, manufactured, and tested for a wide spectrum of applications, the SST27VF040 is offered with a endurance of 1000 cycles. Data retention is rated at greater than 100 years. The SST27VF040 is suited for applications that require infrequent writes and low power nonvolatile storage. The SST27VF040 will improve flexibility, efficiency, and performance while matching the low cost in nonvolatile applications that currently use UV-EPROMs, OTPs, and mask ROMs. To meet surface mount and conventional through hole requirements, the SST27VF040 is offered in 32-pin PLCC, 32-pin PDIP and 32-pin TSOP packages. See Figures 1 and 2 for pinouts.
Device Operation The SST27VF040 is a low cost flash solution that can be used to replace existing UV-EPROM, OTP and mask ROM sockets. It is functionally (Read and Program) and pin compatible with industry standard EPROM products. In addition to EPROM functionality, the device also supports electrical erase operation via an external programmer. The SST27VF040 does not require a UV source to erase, and therefore the packages do not have windows. Read The Read operation of the SST27VF040 is controlled by CE# and OE#. Both CE# and OE# have to be low for the system to obtain data from the outputs. Once the address is stable, the address access time is equal to the delay from CE# to output (TCE). Data is available at the output after a delay of TOE from the falling edge of OE#, assuming the CE# pin has been low and the addresses have been stable for at least TCE - TOE. When the CE# pin is high, the chip is deselected and a standby current of only 10 A (typical) is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either CE# or OE# is high. Programming operation The SST27VF040 is programmed by using an external programmer. The programming mode is activated by asserting 12V (5%) on VPP pin and VIL on CE#, pin. The device is programmed using a single pulse (CE# pin low) of 10 s per byte. Using the MTP programming algorithm, the byte programming process continues byte by byte until the entire chip (512 KBytes) has been programmed.
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(c) 1998 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. MTP is a trademark of Silicon storage Technology, Inc. 1 324-08 12/98 These specifications are subject to change without notice.
4 Megabit SuperFlash MTP SST27VF040
Preliminary Specifications Chip Erase Operation The only way to change a data from a "0" to "1" is by electrical erase that changes every bit in the device to "1". Unlike traditional EPROMs, which use UV light to the chip erase, the SST27VF040 uses an electrical Chip Erase operation. This saves a significant amount of time (about 30 minutes for each Erase operation). The entire chip can be erased in 100 ms (CE# pin low). In order to activate erase mode, the 12V (5%) is applied to VPP and A9 pins and VIH on OE# pin. All other address and data pins are don't care. The falling edge of CE# will start the chip erase operation. Once the chip has been erased, all bytes must be verified for FF. Refer to Figure 8 for the flow chart. The SST27VF040 can also be reprogrammed in the system. This requires the availability of 12V on VPP to program and 12V on address pin A9 to erase. Product Identification Mode The product identification mode identifies the device as the SST27VF040 and manufacturer as SST. This mode may be accessed by the hardware method. To activate this mode, the programming equipment must force VH (12V5%) on address A9 with VPP = VDD = 2.7-3.6V. Two identifier bytes may then be sequenced from the device outputs by toggling address line A0. For details, see Table 3 for hardware operation.
TABLE 1: PRODUCT IDENTIFICATION TABLE Byte Manufacturer's Code 0000 H Device Code 0001 H
Data BF H C7 H
324 PGM T1.0
Design Consideration The SST27VF040 should have a 0.1F ceramic high frequency low inductance capacitor connected between VDD and GND, as well as VPP and GND. These capacitors should be placed as close as possible to the package terminals.
FUNCTIONAL BLOCK DIAGRAM OF THE SST27VF040 4,194,304 bit EEPROM Cell Array
X-Decoder
A18 - A0
Address Buffer Y-Decoder
CE# OE# A9 VPP
Control Logic
I/O Buffers DQ7 - DQ0
324 ILL B1.3
(c) 1998 Silicon Storage Technology, Inc.
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4 Megabit SuperFlash MTP SST27VF040
Preliminary Specifications
A11 A9 A8 A13 A14 A17 A18 VDD VPP A16 A15 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 GND DQ2 DQ1 DQ0 A0 A1 A2 A3
324 ILL F01.1
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Standard Pinout Top View Die Up
FIGURE 1: PIN ASSIGNMENTS FOR 32-PIN TSOP PACKAGES
VDD
VPP
6
A18 A17
A14 A13 A8 A9 A11 OE# A10 CE# DQ7
A12
A15
GND
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
VPP A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 GND
1 2 3 4 5 32-Pin 6 PDIP 7 8 Top View 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
VDD A18 A17 A14 A13 A8 A9 A11 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3
A16
A7 A6 A5 A4 A3 A2 A1 A0 DQ0
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4
3
2
1
32 31 30 29 28 27 26 25 24 23 22
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324 ILL F02.0
32-Lead PLCC Top View
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FIGURE 2: PIN ASSIGNMENTS FOR 32-PIN PLASTIC DIPS AND 32-LEAD PLCCS
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TABLE 2: PIN DESCRIPTION Symbol Pin Name A18-A0 Address Inputs DQ7-DQ0 Data Input/Output CE# OE# VPP VDD GND Chip Enable Output Enable Power Supply for Program or Erase Power Supply Ground Functions To provide memory addresses To output data during read cycles and receive input data during program cycle, the outputs are in tri-state when OE# or CE# is high. To activate the device when CE# is low To gate the data output buffers during read operation High voltage pin during chip erase and programming operation 12-volt (5%) To provide 3-volt supply (2.7 to 3.6V)
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324 PGM T2.1
(c) 1998 Silicon Storage Technology, Inc.
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4 Megabit SuperFlash MTP SST27VF040
Preliminary Specifications TABLE 3: OPERATION MODES SELECTION Mode CE# OE# A9 Read VIL VIL AIN Output Disable X VIH X Standby VIH X X Chip Erase VIL VIH VH Program VIL VIH AIN Program/Erase VIH X X Inhibit VIL VH Product VIL Identification
Note: X = VIL or VIH VH = 12V5% VPPH = 12V5%
VPP VDD or GND VDD or GND VDD or GND VPPH VPPH VPPH VDD or GND
DQ DOUT High Z High Z High Z DIN High Z Manufacturer Code (BF) Device Code (C7)
Address AIN AIN X X AIN X A18-A1 = VIL, A0 = VIL A18-A1 = VIL, A0 = VIH
324 PGM T3.1
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under "Absolute Maximum Stress Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Temperature Under Bias ................................................................................................................. -55C to +125C Storage Temperature ...................................................................................................................... -65C to +150C D. C. Voltage on Any Pin to Ground Potential ............................................................................. -0.5V to VDD+ 0.5V Transient Voltage (<20 ns) on Any Pin to Ground Potential ......................................................... -1.0V to VDD+ 1.0V Voltage on A9, and VPP Pin to Ground Potential ................................................................................ -0.5V to 13.2V Package Power Dissipation Capability (TA = 25C) ........................................................................................... 1.0W Through Hole Lead Soldering Temperature (10 Seconds) .............................................................................. 300C Surface Mount Lead Soldering Temperature (3 Seconds) ............................................................................... 240C Output Short Circuit Current(1) ................................................................................................................................................................. 50 mA
Note: (1) Outputs shorted for no more than one second. No more than one output shorted at a time.
OPERATING RANGE Range Ambient Temp Commercial 0C to +70C Industrial -40C to +85C
AC CONDITIONS OF TEST VDD 2.7 to 3.6V 2.7 to 3.6V Input Rise/Fall Time ......... 10 ns Output Load ..................... CL = 100 pF See Figures 6 and 7
(c) 1998 Silicon Storage Technology, Inc.
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Preliminary Specifications TABLE 4: READ MODE DC OPERATING CHARACTERISTICS VDD = 2.7 to 3.6V, TA = 0C to 70C (Commercial) or -40C to +85C (Industrial) Limits Symbol Parameter Min Max Units Test Conditions ICC VDD Read Current 12 mA CE# = OE# = VIL, all I/Os open, Address Input = VIL/VIH, at f = 1/TRC Min, VDD = VDD Max IPPR VPP Read Current 100 A CE# = OE# = VIL, all I/Os open, Address Input = VIL/VIH, at f = 1/TRC Min, VDD = VDD Max, VPP = VDD ISB Standby VDD Current 15 A CE# = VIHC VDD = VDD Max ILI Input Leakage Current 1 A VIN = GND to VDD, VDD = VDD Max ILO Output Leakage Current 1 A VOUT = GND to VDD, VDD = VDD Max Input Low Voltage 0.8 V VDD = VDD Max VIL VIH Input High Voltage 2.0 VDD+0.5 V VDD = VDD Max VIHC Input High Voltage VDD-0.3 V VDD = VDD Max (CMOS) VOL Output Low Voltage 0.4 V IOL = 100A, VDD = VDD Min VOH Output High Voltage 2.4 V IOH = -100 A, VDD = VDD Min IH Supervoltage Current 200 A CE# = OE# = VIL, A9 = VH Max. for A9
324 PGM T4.6
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(c) 1998 Silicon Storage Technology, Inc.
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4 Megabit SuperFlash MTP SST27VF040
Preliminary Specifications TABLE 5: PROGRAM/ERASE DC OPERATING CHARACTERISTICS VDD = 2.7 to 3.6V, VPP = VPPH, TA = 25C 5C Limits Symbol Parameter Min Max Units ICP VDD Erase or Program 30 mA Current IPP VPP Erase or Program 1 mA Current ILI Input Leakage Current 1 A ILO Output Leakage Current 1 A VH Supervoltage for A9 11.4 12.6 V IH Supervoltage Current 200 A for A9 VPPH High Voltage for VPP Pin 11.4 12.6 V
Test Conditions CE# = VIL, VPP = 12V5%, VDD = VDD Max CE# = VIL, VPP = 12V5%, VDD = VDD Max VIN = GND to VDD, VDD = VDD Max VOUT = GND to VDD, VDD = VDD Max CE# = OE# = VIL CE# = OE# = VIL, A9 = VH Max
324 PGM T5.4
TABLE 6: RECOMMENDED SYSTEM POWER-UP TIMINGS Symbol Parameter TPU-READ Power-up to Read Operation PPU-WRITE Power-up to Write Operation
Minimum 100 100
Units s s
324 PGM T6.1
TABLE 7: CAPACITANCE (TA = 25 C, f=1 MHz, other pins open) Parameter Description Test Condition (1) CI/O I/O Pin Capacitance VI/O = 0V CIN(1) Input Capacitance VIN = 0V
Maximum 12 pF 6 pF
324 PGM T7.1
Note: (1)This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 8: RELIABILITY CHARACTERISTICS Symbol Parameter NEND Endurance TDR(1) Data Retention (1) VZAP_HBM ESD Susceptibility Human Body Model (1) VZAP_MM ESD Susceptibility Machine Model (1) ILTH Latch Up
Note:
(1)
Minimum Specification 1000 100 1000 200 100 + IDD
Units Cycles Years Volts Volts mA
Test Method MIL-STD-883, Method 1033 JEDEC Standard A103 JEDEC Standard A114 JEDEC Standard A115 JEDEC Standard 78
324 PGM T8.2
This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
(c) 1998 Silicon Storage Technology, Inc.
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4 Megabit SuperFlash MTP SST27VF040
Preliminary Specifications AC CHARACTERISTICS TABLE 9: READ CYCLE TIMING PARAMETERS VDD = 2.7 to 3.6V, TA = 0C to 70C (Commercial) or -40C to +85C (Industrial) SST27VF040-90 SST27VF040-120 Symbol Parameter Min Max Min Max Units TRC Read Cycle Time 90 120 ns TCE Chip Enable Access Time 90 120 ns TAA Address Access Time 90 120 ns TOE Output Enable Access Time 45 55 ns TCLZ CE# Low to Active Output 0 0 ns TOLZ OE# Low to Active Output 0 0 ns TCHZ CE# High to High-Z Output 30 30 ns TOHZ OE# High to High-Z Output 30 30 ns TOH Output Hold from Address 0 0 ns Change
324 PGM T9.5
1 2 3 4 5 6 7
TABLE 10: PROGRAMMING/ERASE CYCLE TIMING PARAMETERS VDD = 2.7 to 3.6V, VPP = 12V 5%, TA = 25C 5C Symbol Parameter Min TPC Program Cycle Time 12 TAS Address Setup Time 1 TAH Address Hold Time 1 TDS Data Setup Time 1 TDH Data Hold Time 1 TPRT VPP Pulse Rise Time 1 TVPS VPP Setup Time 1 TVPH VPP Hold Time 1 TPWP CE# Program Pulse Width 10 TPWE CE# Erase Pulse Width 100 TVR A9 Recovery Time for Erase 1 TART A9 Rise Time to 12V during Erase 1 TA9S A9 Setup Time during Erase 1 TA9H A9 Hold Time during Erase 1
8
Max Units s s s s s s s s s ms s s s s
324 PGM T10.5
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15 500
(c) 1998 Silicon Storage Technology, Inc.
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4 Megabit SuperFlash MTP SST27VF040
Preliminary Specifications
TRC ADDRESS
TAA
CE#
TCE
OE#
TOE TOLZ TOH DATA VALID TCLZ VDD
TOHZ TCHZ DATA VALID
DQ7-0
HIGH-Z
VPP
VSS
324 ILL F03.0
FIGURE 3: READ CYCLE TIMING DIAGRAM
ADDRESS (EXCEPT A9)
CE#
TPWE VIH
OE#
DQ7-0 VPPH TVPS VPP VDD VSS VPPH A9 TA9S VIH VIL TART TA9H TVR TPRT TVPH
324 ILL F04.0
FIGURE 4: ERASE TIMING DIAGRAM
(c) 1998 Silicon Storage Technology, Inc.
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4 Megabit SuperFlash MTP SST27VF040
Preliminary Specifications
TPC ADDRESS ADDRESS VALID TAH TAS CE#
1 2 3
VIH OE# TDS TDH
4 5 6
DQ7-0
HIGH-Z VPPH
DATA VALID
VDD VPP VSS TPRT
TVPS
TPWP TVPH
324 ILL F05.0
7 8
FIGURE 5: PROGRAM TIMING DIAGRAM
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VIHT VHT
INPUT REFERENCE POINTS
VHT
OUTPUT
VLT VILT
VLT
324 ILL F06.1
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AC test inputs are driven at VIHT (VDD*0.9) for a logic "1" and VILT (VDD*0.1) for a logic "0". Measurement reference points for inputs and outputs are at VHT (VDD*0.7) and VLT (VDD*0.3) Input rise and fall times (10% 90%) are <10 ns.
Note: VHT-VHIGH Test VLT-VLOW Test VIHT-VINPUT HIGH Test VILT-VINPUT LOW Test
FIGURE 6: AC INPUT/OUTPUT REFERENCE WAVEFORMS
(c) 1998 Silicon Storage Technology, Inc.
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4 Megabit SuperFlash MTP SST27VF040
Preliminary Specifications
TEST LOAD EXAMPLE VDD TO TESTER RL HIGH
TO DUT CL RL LOW
324 ILL F07.1
FIGURE 7: A TEST LOAD EXAMPLE
(c) 1998 Silicon Storage Technology, Inc.
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4 Megabit SuperFlash MTP SST27VF040
Preliminary Specifications
Start
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A9 = VH, VPP = VPPH
CE# = VIH, OE# = VIH Erase 100ms pulse (CE# = VIL)
CE# = VIH
A9 = VIL or VIH
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A9 Recovery Time
7
Device into Read mode
8
Compare All bytes to FF Yes No
9 10
Device Passed
Device Failed
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324 ILL F08.0
12
FIGURE 8: ERASE ALGORITHM
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(c) 1998 Silicon Storage Technology, Inc.
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4 Megabit SuperFlash MTP SST27VF040
Preliminary Specifications
Start
Erase
VPP = VPPH
Address = First Location
CE# = VIH, OE# = VIH
Program 10s pulse (CE# = VIL)
Increment Address No
Last Address? Yes
Device into Read mode
Compare all bytes to original data Yes
No
Device Passed
Device Failed
324 ILL F09.1
FIGURE 9: PROGRAMMING ALGORITHM
(c) 1998 Silicon Storage Technology, Inc.
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4 Megabit SuperFlash MTP SST27VF040
Preliminary Specifications PRODUCT ORDERING INFORMATION
Device SST27VF040
Speed - XXX -
Suffix1 XX -
Suffix2 XX Package Modifier H = 32 leads Numeric = Die modifier Package Type P = PDIP N = PLCC W = TSOP 8x14 mm U = Unencapsulated die Operating Temperature C = Commercial = 0 to 70C I = Industrial = -40 to 85C Minimum Endurance 3 = 1000 cycles Read Access Speed 90 = 90 ns 120 = 120 ns
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Valid combinations SST27VF040-90-3C-WH SST27VF040-90-3I-WH SST27VF040-120-3C-WH SST27VF040-120-3I-WH SST27VF040-90-3C-NH SST27VF040-90-3I-NH SST27VF040-120-3C-NH SST27VF040-120-3I-NH SST27VF040-90-3C-PH
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SST27VF040-120-3C-PH
Example:Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations.
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(c) 1998 Silicon Storage Technology, Inc.
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4 Megabit SuperFlash MTP SST27VF040
Preliminary Specifications PACKAGING DIAGRAMS
1.10 0.90 1.05 0.95 .50 BSC
PIN # 1 IDENT. DIA. 1.00
8.10 7.90
.270 .170
12.50 12.30
0.15 0.05
0.70 0.50
14.20 13.80
Note:
1. Complies with JEDEC publication 95 MO-142 BA dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in metric (min/max). 3. Coplanarity: 0.1 (.05) mm.
32.TSOP-WH-ILL.0
32-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) SST PACKAGE CODE: WH
pin 1 index 1
C L
Optional Ejector Pin Indentation Shown for Conventional Mold Only
32
.600 .625 .530 .550
.065 .075
1.645 1.655
7 4 PLCS.
Base Plane Seating Plane
.015 .050 .120 .150
.170 .200
.008 .012 .600 BSC
0 15
.070 .080
.045 .065
.016 .022
.100 BSC
Note:
1. Complies with JEDEC publication 95 MO-015 AP dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in inches (min/max). 3. Dimensions do not include mold flash. Maximum allowable mold flash is .010 inches.
32.pdipPH-ILL.0
32-LEAD PLASTIC DUAL-IN-LINE PACKAGE (PDIP) SST PACKAGE CODE: PH
(c) 1998 Silicon Storage Technology, Inc.
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4 Megabit SuperFlash MTP SST27VF040
Preliminary Specifications
TOP VIEW
SIDE VIEW
BOTTOM VIEW
1 2
.045 Dia. x .000/.010 Deep Polished (Optional) .042 .048
.485 .495 .447 .453
2 1 32
.106 .112 .020 R. MAX. .023 x 30 .029 .030 R. .040
3
.076/.125 Dia. Ejector Pin .490 .530
K
.042 .048 .585 .595 .547 .553 .026 .032
.013 .021 .400 BSC
ORE
4 5
1
A
.020 High x .002 Deep Characters .050 BSC. .015 Min. .050 BSC. .125 .140 .075 .095 .026 .032
6 7
32.PLCC.NH-ILL.0
Note:
1. Complies with JEDEC publication 95 MS-016 AE dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in inches (min/max). 3. Dimensions do not include mold flash. Maximum allowable mold flash is .008 inches.
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32-LEAD PLASTIC LEAD CHIP CARRIER (PLCC) SST PACKAGE CODE: NH
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(c) 1998 Silicon Storage Technology, Inc.
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