View SP5512_279452.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

SP5512
1.3GHz Bidirectional I C BUS Controlled Synthesiser
2
Datasheet
DS2384 ISSUE 4.2 November 2001
The SP5512 is a single-chip frequency synthesiser designed for TV tuning systems. Control data is entered in the standard I2C BUS format. The device has six controllable open-collector output ports (P2-P7), each capable of sinking 20mA. In addition, P6 is a 3-bit 5-level ADC input. The information on these ports can be read via the I 2C BUS. The device has one fixed I 2C BUS address and three programmable addresses, allowing two or more synthesisers to be used in a system.
Ordering Information
SP5512DS/KG/MPAS (Tubes) SP5512DS/KG/MPAD (Tape & Reel) (16-lead miniature plastic package)
CHARGE PUMP
1
16
DRIVE OUTPUT VEE RF INPUT RF INPUT VCC P2 OUTPUT PORT P3 OUTPUT PORT/ADD SELECT I/O PORT P4
FEATURES s Complete 1*3GHz Single Chip System s Programmable via the I2C BUS
CRYSTAL Q1 CRYSTAL Q2 SDA SCL
SP5512S
s s s s s s s s
Low Power Consumption (215mW Typ.) Low Radiation Phase Lock Detector Varactor Drive Amp Disable 6 Controllable Outputs, 5 Bi-directional 5-Level ADC Variable I C BUS Address for Picture in Picture TV ESD Protection *
2
I/O PORT P7
* I/O PORT P6
I/O PORT P5
8 9
MP16
= Logic level I/O port * = 3-bit ADC input
Fig. 1 Pin connections - top view
* Normal ESD handling precautions should be observed.
APPLICATIONS s Cable Tuning Systems s VCRs
SP5512
Datasheet
ELECTRICAL CHARACTERISTICS
TAMB = -10C to +80C, VCC = +4*5V to +5*5V. These Characteristics are guaranteed by either production test or design. They apply within the specified ambient temperature and supply voltage ranges unless otherwise stated. Reference frequency 4MHz unless otherwise stated. Value Characteristic Pin Min. Supply current Prescaler input voltage Prescaler input impedance Prescaler input capacitance SDA, SCL Input high voltage Input low voltage Input high current Input low current Leakage current SDA Output voltage Charge pump current low Charge pump current high Charge pump output leakage current Charge pump drive output current Charge pump amplifier gain Recommended crystal series resistance Crystal oscillator drive level Crystal oscillator negative resistance Output Ports P2-P7 sink current (see note 1) P2-P7 leakage current (see note 1) Input Ports P3 input current high P3 input current low P4, P5, P7 input voltage low P4, P5, P7 input voltage high P6 input current high P6 input current low 12 13,14 13,14 Typ. 43 12*5 30 50 2 3 0 5*5 1*5 10 -10 10 0*4 50 170 5 500 6400 10 40 2 6-11 6-11 10 10 6,8,9 6,8,9 7 7 750 20 10 -10 -10 0*8 2*7 +10 -10 200 Max. 53 300 300 VCC = 5V mA mVrms 50MHz to 1GHz mVrms 1*3GHz, see Fig. 5 pF V V A A A V A A nA Units Conditions
4,5 4,5 4,5 4,5 4,5 4 1 1 1 16
Input voltage = VCC Input voltage = 0V When VCC = 0V Sink current = 3mA Byte 4, bit 2 = 0, pin 1 = 2V Byte 4, bit 2 = 1, pin 1 = 2V Byte 4, bit 4 = 1, pin 1 = 2V V pin 16 = 0*7V
Parallel resonant crystal (note 2) mV p-p mA A A A V V A A VOUT = 0*7V, see note 1 VOUT = 13*2V V pin 10 = 13*2V V pin 10 = 0V
See Table 3 for ADC levels
NOTES 1. Source impedance between all output ports and ground is approximately 5. This should be taken into account when calculating output port saturation voltages. 2. The recommended crystal series resistance quoted refers to all conditions including start-up.
2
Datasheet
ABSOLUTE MAXIMUM RATINGS
All voltages are referred to VEE and pin 3 at 0V. Parameter Supply voltage RF input voltage Port voltage Total port output current RF input DC offset Charge pump DC offset Drive output DC offset Crystal oscillator DC offset SDA, SCL input voltage Pin Min. 12 13,14 6-11 6-11 6-11 13-14 1 16 2 4,5 -0*3 -0*3 -0*3 -0*3 -0*3 -0*3 -55 -0*3 -0*3 -0*3 Value Max. 7 2*5 14 6 50 VCC+0*3 VCC+0*3 VCC+0*3 VCC+0*3 VCC+0*3 5*5 +150 +150 111 41 321 V V p-p V V mA V V V V V V C C C/W C/W mW Units
SP5512
Conditions
Port in off state Port in on state
With VCC applied VCC not applied
Storage temperature Junction temperature MP16 thermal resistance, chip-to-ambient MP16 thermal resistance, chip-to-case Power consumption at 5*5V
VCC RF IN RF IN POWER ON DETECTOR LOCK DETECTOR 15 BIT DIVIDER RATIO LATCH I2C BUS TRANSCEIVER SDA 6-BIT LATCH PORT INFORMATION ADDRESS SELECT 3-BIT ADC 3 TTL LEVEL COMP CHARGE PUMP T0 CP CONTROL DATA LATCH T1 OS
PRE AMP
48 PRESCALER
15 BIT PROGRAMMABLE DIVIDER
FDIV
PHASE COMP F
FCOMP
DIVIDER 4512
OSC 4MHz
Q1 CRYSTAL Q2
CHARGE PUMP DRIVE OUTPUT
SCL
LOGIC
VEE
P2 P3 P4 P5 P6 P7
Fig. 2 Block diagram
3
SP5512
Datasheet
local oscillator control voltage until the output of the programmable divider is frequency and phase locked to the comparison frequency. The reference frequency may be generated by an external source capacitively coupled into pin 2 or provided by an on-chip 4MHz crystal controlled oscillator. Note that the comparison frequency is 7*8125kHz when a 4MHz reference is used. Bit 2 of Byte 4 of the programming data (CP) controls the current in the charge pump circuit, a logic 1 for 170A and a logic 0 for 50A, allowing compensation for the variable tuning slope of the tuner and also to enable fast channel changes over the full band. Bit 4 of Byte 4 (T0) disables the charge pump if set to a logic 1. Bit 8 of Byte 4 (OS) switches the charge pump drive amplifier's output off when it is set to a logic 1. Bit 3 of Byte 4 (T1) selects a test mode where the phase comparator inputs are available on P6 and P7, a logic 1 connects F COMP to P6 and FDIV to P7. Byte 5 programs the output ports P2-P7, a logic 0 for a high impedance output, logic 1 for low impedance (on).
The SP5512 is programmed from an I2C BUS. Data and Clock are fed in on the SDA and SCL lines respectively as defined by the I2C Bus format. The synthesiser can either accept new data (write mode) or send data (read mode). The Tables in Fig. 3 illustrate the format of the data. The device can be programmed to respond to several addresses, which enables the use of more than one synthesiser in an I2C BUS system. Table 4 shows how the address is selected by applying a voltage to P3. The LSB of the address byte (R/ W) sets the device into read mode if it is high and write mode if it is low. When the SP5512 receives a correct address byte it pulls the SDA line low during the acknowledge period and during following acknowledge periods after further data bytes are programmed. When the SP5512 is programmed into the read mode the controlling device accepting the data must pull down the SDA line during the following acknowledge period to read another status byte.
FUNCTIONAL DESCRIPTION
WRITE MODE (FREQUENCY SYNTHESIS)
When the device is in the write mode Bytes 2+3 select the synthesised frequency while Bytes 4+5 select the output port states and charge pump information. Once the correct address is received and acknowledged, the first bit of the next byte determines whether that byte is interpreted as Byte 2 or 4, a logic 0 for frequency information and a logic 1 for charge pump and output port information. Additional data bytes can be entered without the need to readdress the device until an I 2C stop condition is recognised. This allows a smooth frequency sweep for fine tuning or AFC purposes. If the transmission of data is stopped mid-byte (e.g., by another device on the bus) then the previously programmed byte is maintained. Frequency data from Bytes 2 and 3 is stored in a 15-bit shift register and is used to control the division ratio of the 15bit programmable divider which is preceded by a divide-by8 prescaler and amplifier to give excellent sensitivity at the local oscillator input; see Fig 5. The input impedance is shown in Fig. 7. The programmed frequency can be calculated by multiplying the programmed division ratio by 8 times the comparison frequency FCOMP . When frequency data is entered, the phase comparator, via the charge pump and varactor drive amplifier, adjusts the
READ MODE
When the device is in the read mode the status data read from the device on the SDA line takes the form shown in Table 2. Bit 1 (POR) is the power on reset indicator and is set to a logic 1 if the power supply to the device has dropped below a nominal 3V and the programmed information lost (e.g., when the device is initially turned on). The POR is set to 0 when the read sequence is terminated by a stop command. The outputs are all set to high impedance when the device is initially powered up. Bit 2 (FL) indicates whether the device is phase locked, a logic 1 is present if the device is locked and a logic 0 if the device is unlocked. Bits 3, 4 and 5 (I2, I1, I0) show the status of the I/O Ports P7, P5 and P4 respectively. A logic 0 indicates a low level and a logic 1 a high level. If the ports are to be used as inputs they should be programmed to a high impedance state (logic1). These inputs will then respond to data complying with standard TTL voltage levels. Bits 6, 7 and 8 (A2,A1,A0) combine to give the output of the 5-level ADC. The 5-level ADC can be used to feed AFC information to the microprocessor from the IF section of the television, as illustrated in Fig. 4.
4
Datasheet
SP5512
MSB Address Programmable divider Programmable divider Charge pump and test bits I/O port control bits 1 0 2
7
LSB 1 2
14 6
0 2
13 5
0 2
12 4
0 2
11 3
MA1 MA0 2
10 2
0 2 2
8 0
A A A A A
Byte 1 Byte 2 Byte 3 Byte 4 Byte 5
2 2
9 1
2
2
2
2
2
1 P7
CP P6
T1 P5
T0 P4
1 P3
1 P2
1 X
OS X
Table 1 Write data format (MSB transmitted first)
Address Status byte
1
1
0 I2
0 I1
0 I0
MA1 MA0 A2 A1
1 A0
A A
Byte 1 Byte 2
POR FL
Table 2 Read data format
A2 1 0 0 0 0
A1 0 1 1 0 0
A0 0 1 0 1 0
Voltage input to P6 0*6V CC to 13*2V 0*45VCC to 0*6VCC 0*3VCC to 0*45VCC 0*15VCC to 0*3VCC 0V to 0*15VCC MA1 MA0 Voltage input to P3 0 0 1 1 0 1 0 1 0V to 0*2V CC Always valid 0*3VCC to 0*7VCC 0*8VCC to 13*2V
Table 3 ADC levels
A MA1, MA0 CP T1 T0 OS P7, P6, P5, P4, P3, P2 POR FL I2, I1, I0 A2, A1, A0 X : : : : : : : : : : : :
Table 4 Address selection
Acknowledge bit Variable address bits (see Table 4) Charge Pump current select Test mode selection Charge pump disable Varactor drive Output disable Switch Control output port states Power On Reset indicator Phase lock detect flag Digital information from ports P7, P5 and P4 respectively 5-level ADC data from P6 (see Table 3) Don't care
Fig. 3 Data formats
5
SP5512
APPLICATION
Datasheet
A typical application is shown in Fig. 4. All input/output interface circuits are shown in Fig. 6.
130V 112V 22k 39n 180n 0*1 10k 22k 1 2 4MHz SDA 3 4 16 15 14 13 22k P2 P3 P4 12k 12k 2N3906 12k 2N3906 112V 2N3906 22k 22k 1n 1n OSCILLATOR OUTPUT 2N3904 47k 10n VT VARACTOR DRIVE 15V
15V
18p
CONTROL MICRO
I2C BUS
SCL P7 P6 P5
5 SP5512 12 6 7 8 11 10 9
TUNER
BAND INPUTS
AFC OUT
IF SECTION
IF SIGNAL
Fig. 4 Typical application
300
VIN (mV RMS INTO 50 )
37*5
OPERATING WINDOW
25
12*5
50
500
1000 FREQUENCY (MHz)
1300
1500
Fig. 5 Typical input sensitivity
6
Datasheet
SP5512
VREF
VCC
550
550
CHARGE PUMP
RF INPUTS 170 DRIVE OUTPUT
RF input
Loop amplifier
VCC
VCC
PORT 3k SCL/SDA
* * ON SDA ONLY
Ports P3 - P7 SCL and SDA inputs
ACK
PORT
CRYSTAL Q1
CRYSTAL Q2
Reference oscillator
Port P2
Fig. 6 Input/output interface circuits
7
SP5512
Datasheet
j1 j 0.5 j2
j 0.2 j5
0
0.2
0.5
1
2
5
2j 5 2j 0.2
1*25GHz
S11:ZO = 50 NORMALISED TO 50
2j 0.5 2j 1
2j 2
FREQUENCY MARKER STEP = 250MHz
Fig. 7 Typical input impedance
8
For more information about all Zarlink products visit our Web Site at
www.zarlink.com
Information relating to products and services furnished herein by Zarlink Semiconductor Inc. trading as Zarlink Semiconductor or its subsidiaries (collectively "Zarlink") is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use of product in certain ways or in combination with Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink. This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user's responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink's conditions of sale which are available on request.
Purchase of Zarlink's I2C components conveys a licence under the Philips I2C Patent rights to use these components in an I2C System, provided that the system conforms to the I2C Standard Specification as defined by Philips. Zarlink and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2002, Zarlink Semiconductor Inc. All Rights Reserved.
TECHNICAL DOCUMENTATION - NOT FOR RESALE

▲Up To Search▲

Price & Availability of SP5512

	To Download SP5512 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .