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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Dual Supply Octal Translating Transceiver
with 3-State Outputs
The 74LVX4245 is a 24-pin dual-supply, octal translating transceiver that is designed to interface between a 5V bus and a 3V bus in a mixed 3V/5V supply environment such as laptop computers using a 3.3V CPU and 5V LCD display. The A port interfaces with the 5V bus; the B port interfaces with the 3V bus. The Transmit/Receive (T/R) input determines the direction of data flow. Transmit (active-High) enables data from the A port to the B port. Receive (active-Low) enables data from the B port to the A port. The Output Enable (OE) input, when High, disables both A and B ports by placing them in 3-State.
MC74LVX4245
LOW-VOLTAGE CMOS
LVX
* * * * *
Bi-directional Interface Between 5V and 3V Buses Control Inputs Compatible with TTL Level 5V Data Flow at A Port and 3V Data Flow at B Port Outputs Source/Sink 24mA at 5V Bus and 12mA at 3V Bus
DW SUFFIX 24-LEAD PLASTIC SOIC PACKAGE CASE 751E-04
Guaranteed Simultaneous Switching Noise Level and Dynamic Threshold Performance * Available in SOIC and TSSOP Packages
* Functionally Compatible with the 74 Series 245
VCCB VCCB OE 24 23 22 B0 21 B1 20 B2 19 B3 18 B4 17 B5 16 B6 15 B7 14 GND 13 DT SUFFIX 24-LEAD PLASTIC TSSOP PACKAGE CASE 948H-01
PIN NAMES
1 2 3 A0 4 A1 5 A2 6 A3 7 A4 8 A5 9 A6 10 A7 11 12 Pins OE T/R A0-A7 B0-B7 Function Output Enable Input Transmit/Receive Input Side A 3-State Inputs or 3-State Outputs Side B 3-State Inputs or 3-State Outputs VCCA T/R GND GND
Figure 1. 24-Lead Pinout (Top View)
7/97
(c) Motorola, Inc. 1997
1
REV 2
MC74LVX4245
OE 22 T/R 2 3 21 A1 4 20 A2 5 19 A3 6 18 A4 7 17 A5 8 16 A6 9 15 A7 10 14
A0
B0
B1
B2
B3
B4
B5
B6
B7
Figure 2. Logic Diagram
INPUTS OE L L H T/R L H X OPERATING MODE Non-Inverting B Data to A Bus A Data to B Bus Z
H = High Voltage Level; L = Low Voltage Level; Z = High Impedance State; X = High or Low Voltage Level and Transitions are Acceptable; For ICC reasons, Do Not Float Inputs
MOTOROLA
2
LVX Data -- Low-Voltage CMOS Logic BR1492 -- Rev 0
MC74LVX4245
ABSOLUTE MAXIMUM RATINGS*
Symbol VCCA, VCCB VI VI/O DC Supply Voltage DC Input Voltage DC Input/Output Voltage OE, T/R An Bn IIK IOK IO ICC, IGND DC Input Diode Current DC Output Diode Current DC Output Source/Sink Current DC Supply Current Per Output Pin Maximum Current at ICCA Maximum Current at ICCB OE, T/R Parameter Value -0.5 to +7.0 -0.5 to VCCA +0.5 -0.5 to VCCA +0.5 -0.5 to VCCB +0.5 20 50 50 50 200 100 -65 to +150 300 VI < GND VO < GND; VO > VCC Condition Unit V V V V mA mA mA mA
TSTG Latchup
Storage Temperature Range DC Latchup Source/Sink Current
C mA
* Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated conditions is not implied.
RECOMMENDED OPERATING CONDITIONS
Symbol VCCA, VCCB VI VI/O TA t/V Supply Voltage Input Voltage Input/Output Voltage Operating Free-Air Temperature Minimum Input Edge Rate VIN from 30% to 70% of VCC; VCC at 3.0V, 4.5V, 5.5V Parameter VCCA VCCB OE, T/R An Bn Min 4.5 2.7 0 0 0 -40 0 Max 5.5 3.6 VCCA VCCA VCCB +85 8 Unit V V V C ns/V
DC ELECTRICAL CHARACTERISTICS
TA = 25C Symbol VIHA VIHB VILA VILB VOHA VOHB Minimum HIGH Level Output Voltage Maximum LOW Level Input Voltage Parameter Minimum HIGH Level Input Voltage An,OE T/R Bn An,OE T/R Bn Condition VOUT 0.1V or VCC - 0.1V VOUT 0.1V or VCC - 0.1V IOUT = -100A IOH = -24mA IOUT = -100A IOH = -12mA IOH = -8mA Maximum LOW Level Output Voltage IOUT = 100A IOL = 24mA IOUT = 100A IOL = 12mA IOL = 8mA VCCA 5.5 4.5 5.0 5.0 5.5 4.5 5.0 5.0 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 VCCB 3.3 3.3 3.6 2.7 3.3 3.3 2.7 3.6 3.0 3.0 3.0 3.0 2.7 3.0 3.0 3.0 3.0 2.7 4.50 4.25 2.99 2.80 2.50 0.002 0.18 0.002 0.1 0.1 Typ 2.0 2.0 2.0 2.0 0.8 0.8 0.8 0.8 4.40 3.86 2.9 2.4 2.4 0.10 0.36 0.10 0.31 0.31 TA = -40 to +85C Guaranteed Limits 2.0 2.0 2.0 2.0 0.8 0.8 0.8 0.8 4.40 3.76 2.9 2.4 2.4 0.10 0.44 0.10 0.40 0.40 Unit V V V V V V
VOLA VOLB
V V
LVX Data -- Low-Voltage CMOS Logic BR1492 -- Rev 0
3
MOTOROLA
MC74LVX4245
DC ELECTRICAL CHARACTERISTICS
TA = 25C Symbol IIN IOZA Parameter Max Input Leakage Current Max 3-State Output Leakage Max 3-State Output Leakage Maximum ICCT per Input OE, T/R An Condition VI = VCCA, GND VI = VIH, VIL OE = VCCA VO = VCCA, GND VI = VIH, VIL OE = VCCA VO = VCCB, GND VI=VCCA-2.1V VI=VCCB-0.6V An=VCCA or GND Bn=VCCB or GND OE=GND T/R=GND An=VCCA or GND Bn=VCCB or GND OE=GND T/R=VCCA Notes 1., 2. Notes 1., 2. Notes 1., 3. VCCA 5.5 VCCB 3.6 Typ TA = -40 to +85C Guaranteed Limits 0.1 0.5 1.0 5.0 Unit A A
5.5
3.6
IOZB
Bn An,OE T/R Bn
5.5
3.6
0.5
5.0
A
ICC
5.5 5.5
3.6 3.6
1.0
1.35 0.35
1.5 0.5
mA mA A
ICCA
Quiescent VCCA Supply Current
5.5
3.6
8
80
ICCB
Quiescent VCCB Supply Current
A 5.5 3.6 5 50
VOLPA VOLPB VOLVA VOLVB VIHDA VIHDB
Quiet Output Max Dynamic VOL Quiet Output Min Dynamic VOL Min HIGH Level Dynamic Input Voltage
5.0 5.0 5.0 5.0 5.0 5.0
3.3 3.3 3.3 3.3 3.3 3.3
1.5 1.2 -1.2 -0.8 2.0 2.0
V V V
VILDA Max LOW Level 5.0 3.3 0.8 V Notes 1., 3. VILDB Dynamic Input Voltage 5.0 3.3 0.8 1. Worst case package. 2. Max number of outputs defined as (n). Data inputs are driven 0V to VCC level; one output at GND. 3. Max number of data inputs (n) switching. (n-1) inputs switching 0V to VCC level. Input under test switching: VCC level to threshold (VIHD), 0V to threshold (VILD), f = 1MHz.
CAPACITIVE CHARACTERISTICS
Symbol CIN CI/O CPD Parameter Input Capacitance Input/Output Capacitance Power Dissipation Capacitance (Measured at 10MHz) BA AB Condition VCCA = 5.0V; VCCB = 3.3V VCCA = 5.0V; VCCB = 3.3V VCCA = 5.0V VCCB = 3.3V Typical 4.5 15 55 40 Unit pF pF pF
MOTOROLA
4
LVX Data -- Low-Voltage CMOS Logic BR1492 -- Rev 0
MC74LVX4245
AC ELECTRICAL CHARACTERISTICS
TA = -40 to +85C CL = 50pF VCCA = 5V 0.5V VCCB = 3.3V 0.3V Symbol tPHL tPLH tPHL tPLH tPZL tPZH tPZL tPZH tPHZ tPLZ tPHZ tPLZ Parameter Propagation Delay A to B Propagation Delay B to A Output Enable Time OE to B Output Enable Time OE to A Output Disable Time OE to B Output Disable Time OE to A Min 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 Typ (Note 4.) 5.1 5.3 5.4 5.5 6.5 6.7 5.2 5.8 6.0 3.3 3.9 2.9 Max 9.0 9.0 9.0 9.0 10.5 10.5 9.5 9.5 10.0 7.0 7.5 7.0 TA = -40 to +85C CL = 50pF VCCA = 5V 0.5V VCCB = 2.7V Min 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 Max 10.0 10.0 10.0 10.0 11.5 11.5 10.0 10.0 10.0 7.5 7.5 7.5 Unit ns ns ns ns ns ns
tOSHL ns Output to Output Skew, Data to Output (Note 5.) 1.0 1.5 1.5 tOSLH 4. Typical values at VCCA = 5.0V; VCCB = 3.3V at 25C. 5. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH); parameter guaranteed by design.
Dual Supply Octal Translating Transceiver The 74LVX4245 is a is a dual-supply device well capable of bidirectional signal voltage translation. This level shifting ability provides an excellent interface between low voltage CPU local bus and a standard 5V I/O bus. The device control inputs can be controlled by either the low voltage CPU and core logic or a bus arbitrator with 5V I/O levels. The LVX4245 is ideal for mixed voltage applications such as notebook computers using a 3.3V CPU and 5V peripheral devices. Applications: Mixed Mode Dual Supply Interface Solutions The LVX4245 is designed to solve 3V/5V interfaces when CMOS devices cannot tolerate I/O levels above their applied VCC. If an I/O pin of a 3V device is driven by a 5V device, the P-Channel transistor in the 3V device will conduct -- causing current flow from the I/O bus to the 3V power supply. The result may be destruction of the 3V device through latchup effects. A current limiting resistor may be used to prevent destruction, but it causes speed degradation and needless power dissipation. A better solution is provided in the LVX4245. It provides two different output levels that easily handle the dual voltage interface. The A port is a dedicated 5V port; the B port is a dedicated 3V port. Figure 4 on page 6 shows how the LVX4245 may fit into a mixed 3V/5V system. Since the LVX4245 is a `245 transceiver, the user may either use it for bidirectional or unidirectional applications. The center 20 pins are configured to match a `245 pinout.
This enables the user to easily replace this level shifter with a 3V `245 device without additional layout work or re- manufacture of the circuit board (when both buses are 3V).
LOW VOLTAGE CPU LOCAL BUS
VCCB LVX4245 VCCA
VCCB LVX4245 VCCA
EISA - ISA - MCA (5V I/O LEVELS)
Figure 3. 3.3V/5V Interface Block Diagram Powering Up the LVX4245 When powering up the LVX4245, please note that if the VCCB pin is powered-up well in advance of the VCCA pin, several milliamps of either ICCA or ICCB current will result. If the VCCA pin is powered-up in advance of the VCCB pin then only nanoamps of Icc current will result. In actuality the VCCB can be powered "slightly" before the VCCA without the current penalty, but this "setup time" is dependent on the power-up ramp rate of the VCC pins. With a ramp rate of approximately 50mV/ns (50V/s) a 25ns setup time was observed (VCCB
LVX Data -- Low-Voltage CMOS Logic BR1492 -- Rev 0
5
MOTOROLA
MC74LVX4245
before VCCA). With a 7V/s rate, the setup time was about 140ns. When all is said and done, the safest power-up strategy is to simply power VCCA before VCCB. One more note: if the VCCB ramp rate is faster than the VCCA ramp rate then power problems might still occur, even if the VCCA power-up began prior to the VCCB power-up.
5V
MICROCHANNEL/ EISA/ISA/AT 5V BUS
LOCAL 3V BUS
3V
KEYBOARD CONTROLLER
CACHE SRAM 5V VCCA 3V VCCB CPU 386/486
SUPER I/O
CORE LOGIC
LVX4245
TRANSCEIVERS A PORT A0:7 B PORT B0:7 ROM BIOS
PCMCIA CONTROLLER MEMORY DRIVER
VGA CONTROLLER
Figure 4. MC74LVX4245 Fits Into a System with 3V Subsystem and 5V Subsystem
VCCA (T/R) DIR A0 A1 A2 A3 A4 A5 A6 A7 GND GND
MC74LVX4245
VCCB VCCB OE B0
STANDARD 74 SERIES `245
B1 B2 B3 B4 B5 B6 B7 GND
Figure 5. MC74LVX4245 Pin Arrangement Is Compatible to 20-Pin 74 Series `245s
MOTOROLA
6
LVX Data -- Low-Voltage CMOS Logic BR1492 -- Rev 0
MC74LVX4245
VCC An, Bn 50%VCC 50% VCC 0V tPLH Bn, An 50% VCC tPHL VOH 50% VCC VOL WAVEFORM 1 - PROPAGATION DELAYS tR = tF = 2.5ns, 10% to 90%; f = 1MHz; tW = 500ns
VCCA OE, T/R 50% VCC 50% VCC 0V tPZH An, Bn 50% VCC 0V tPZL 50% VCC VOL + 0.3V GND WAVEFORM 2 - OUTPUT ENABLE AND DISABLE TIMES tR = tF = 2.5ns, 10% to 90%; f = 1MHz; tW = 500ns tPLZ VCC tPHZ VCC VOH - 0.3V
An, Bn
Figure 6. AC Waveforms
VCC 2 x VCC OPEN
PULSE GENERATOR RT
DUT CL
R1 RL
TEST tPLH, tPHL, tPZH, tPHZ tPZL, tPLZ
SWITCH Open 2 x VCC
CL = 50pF or equivalent (Includes jig and probe capacitance) RL = R1 = 500 or equivalent RT = ZOUT of pulse generator (typically 50)
Figure 7. Test Circuit
LVX Data -- Low-Voltage CMOS Logic BR1492 -- Rev 0
7
MOTOROLA
MC74LVX4245
OUTLINE DIMENSIONS
DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948H-01 ISSUE O
24X K REF
0.10 (0.004) 0.15 (0.006) T U
S
M
TU
S
V
S
2X
L/2
24
13
L
PIN 1 IDENT. 1 12
B -U-
0.15 (0.006) T U
S
A -V-
NOTES: 1 DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2 CONTROLLING DIMENSION: MILLIMETER. 3 DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4 DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5 DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6 TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7 DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 7.70 7.90 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.27 0.37 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.303 0.311 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.011 0.015 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_
C 0.10 (0.004) -T- SEATING
PLANE
D
G
H
-W-
DETAIL E N K K1 J1
0.25 (0.010) M
SECTION N-N J
MOTOROLA
CCC EE CCC EE
N F DETAIL E
8
LVX Data -- Low-Voltage CMOS Logic BR1492 -- Rev 0
MC74LVX4245
OUTLINE DIMENSIONS
DW SUFFIX PLASTIC SOIC PACKAGE CASE 751E-04 ISSUE E
-A -
24 13 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 15.25 15.54 7.60 7.40 2.65 2.35 0.49 0.35 0.90 0.41 1.27 BSC 0.32 0.23 0.29 0.13 8 0 10.05 10.55 0.25 0.75 INCHES MIN MAX 0.601 0.612 0.292 0.299 0.093 0.104 0.014 0.019 0.016 0.035 0.050 BSC 0.009 0.013 0.005 0.011 0 8 0.395 0.415 0.010 0.029
-B -
1 12
P 12 PL 0.010 (0.25)
M
B
M
J D 24 PL 0.010 (0.25)
M
TA
S
B
S
F R X 45 C -T - SEATING PLANE G 22 PL K M
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LVX Data -- Low-Voltage CMOS Logic BR1492 -- Rev 0
9
MC74LVX4245/D MOTOROLA

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