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i960(R) VH Embedded-PCI Processor
Preliminary Datasheet
Product Features
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High Performance 80960JT Core -- Sustained One Instruction/Clock Execution -- 16 Kbyte Two-Way Set-Associative Instruction Cache -- 4 Kbyte Direct-Mapped Data Cache -- Sixteen 32-Bit Global Registers -- Sixteen 32-Bit Local Registers -- Programmable Bus Widths: 8-, 16-, 32-Bit -- 1 Kbyte Internal Data RAM -- Local Register Cache (Eight Available Stack Frames) -- Two 32-Bit On-Chip Timer Units -- Core Clock Rate: 1x, 2x or 3x Local Bus Clock PCI Interface -- Complies with PCI Local Bus Specification 2.2 -- Runs at Local Bus Clock Rate -- 5 Volts PCI Signaling Environment Address Translation Unit -- Connects Local Bus to PCI Bus -- Inbound/Outbound Address Translation Support -- Direct Outbound Addressing Support Messaging Unit -- Four Message Registers -- Two Doorbell Registers
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Memory Controller -- 256 Mbytes of 32- or 36-Bit DRAM -- Interleaved or Non-Interleaved DRAM -- Fast Page-Mode DRAM Support -- Extended Data Out DRAM Support -- Two Independent Banks for SRAM / ROM / Flash (16 Mbytes/Bank; 8- or 32-Bit) DMA Controller -- Two Independent Channels -- PCI Memory Controller Interface -- 32-Bit Local Bus Addressing -- 64-Bit PCI Bus Addressing -- Independent Interface to PCI Bus -- 132 Mbyte/sec Burst Transfers to PCI and Local Buses -- Direct Addressing to and from PCI Buses -- Unaligned Transfers Supported in Hardware -- Channels Dedicated to PCI Bus I2C Bus Interface Unit -- Serial Bus -- Master/Slave Capabilities -- System Management Functions 3.3 V Supply -- 5 V Tolerant Inputs -- TTL Compatible Outputs Plastic BGA* Package -- 324 Ball-Grid Array (PBGA)
Notice: This document contains preliminary information on new products in production. The specifications are subject to change without notice. Verify with your local Intel sales office that you have the latest datasheet before finalizing a design.
Order Number: 273179-004 April 1999
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The i960 (R) VH Processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800548-4725 or by visiting Intel's website at http://www.intel.com. Copyright (c) Intel Corporation, 1999 *Third-party brands and names are the property of their respective owners.
Preliminary Datasheet
80960VH
Contents
1.0 About This Document......................................................................................................... 7 1.1 1.2 1.3 2.0 Solutions960(R) Program......................................................................................... 7 Terminology........................................................................................................... 7 Additional Information Sources ............................................................................. 7
Functional Overview........................................................................................................... 8 2.1 Key Functional Units ............................................................................................. 9 2.1.1 DMA Controller......................................................................................... 9 2.1.2 Address Translation Unit .......................................................................... 9 2.1.3 Messaging Unit......................................................................................... 9 2.1.4 Memory Controller.................................................................................... 9 2.1.5 Core and Peripheral Unit.......................................................................... 9 2.1.6 I2C Bus Interface Unit .............................................................................. 9 i960(R) Core Features (80960JT) .......................................................................... 10 2.2.1 Burst Bus................................................................................................ 11 2.2.2 Timer Unit ............................................................................................... 11 2.2.3 Priority Interrupt Controller ..................................................................... 11 2.2.4 Faults and Debugging ............................................................................ 11 2.2.5 On-Chip Cache and Data RAM .............................................................. 12 2.2.6 Local Register Cache ............................................................................. 12 2.2.7 Test Features ......................................................................................... 12 2.2.8 Memory-Mapped Control Registers ....................................................... 12 2.2.9 Instructions, Data Types and Memory Addressing Modes .....................13
2.2
3.0
Package Information ........................................................................................................15 3.1 Package Introduction........................................................................................... 15 3.1.1 Functional Signal Definitions ..................................................................15 3.1.2 324-Lead PBGA Package ...................................................................... 25 Package Thermal Specifications .........................................................................33 3.2.1 Thermal Specifications ........................................................................... 33 3.2.1.1 Ambient Temperature................................................................ 33 3.2.1.2 Case Temperature .................................................................... 33 3.2.1.3 Thermal Resistance ..................................................................34 3.2.2 Thermal Analysis .................................................................................... 34
3.2
4.0
Electrical Specifications.................................................................................................... 35 4.1 4.2 4.3 4.4 VCC5 Pin Requirements (VDIFF) .......................................................................... 35 VCCPLL Pin Requirements ................................................................................... 36 DC Specifications ................................................................................................ 37 AC Specifications ................................................................................................ 39 4.4.1 Relative Output Timings .........................................................................41 4.4.2 Memory Controller Relative Output Timings .......................................... 41 4.4.3 Boundary Scan Test Signal Timings ...................................................... 43 4.4.4 I2C Interface Signal Timings ..................................................................44 AC Test Conditions ............................................................................................. 44 AC Timing Waveforms ........................................................................................ 45 Memory Controller Output Timing Waveforms ....................................................48
4.5 4.6 4.7
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5.0 6.0
Bus Functional Waveforms .............................................................................................. 54 Device Identification On Reset ......................................................................................... 63
Figures
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Product Name Functional Block Diagram ............................................................. 8 80960JT Core Block Diagram ............................................................................. 10 324-Plastic Ball Grid Array Top and Side View ................................................... 25 324-Plastic Ball Grid Array (Top View)................................................................ 26 Thermocouple Attachment .................................................................................. 33 VCC5 Current-Limiting Resistor ........................................................................... 36 VCCPLL Lowpass Filter ........................................................................................ 36 AC Test Load ...................................................................................................... 44 P_CLK, TCLK Waveform .................................................................................... 45 TOV Output Delay Waveform .............................................................................. 45 TOF Output Float Waveform................................................................................ 46 TIS and TIH Input Setup and Hold Waveform ...................................................... 46 TLXL and TLXA Relative Timings Waveform ........................................................ 46 DT/R# and DEN# Timings Waveform ................................................................. 47 I2C Interface Signal Timings................................................................................ 47 Fast Page-Mode Read Access, Non-Interleaved, 2,1,1,1 Wait State, 32-Bit 80960 Local Bus ............................................................................................................ 48 Fast Page-Mode Write Access, Non-Interleaved, 2,1,1,1 Wait States, 32-Bit 80960 Local Bus ............................................................................................................ 49 FPM DRAM System Read Access, Interleaved, 2,0,0,0 Wait States.................. 50 FPM DRAM System Write Access, Interleaved, 1,0,0,0 Wait States .................. 51 EDO DRAM, Read Cycle .................................................................................... 52 EDO DRAM, Write Cycle .................................................................................... 52 32-Bit Bus, SRAM Read Accesses with 0 Wait States ....................................... 53 32-Bit Bus, SRAM Write Accesses with 0 Wait States........................................ 53 Non-Burst Read and Write Transactions without Wait States, 32-Bit 80960 Local Bus ...................................................................................................................... 54 Burst Read and Write Transactions without Wait States, 32-Bit 80960 Local Bus ............................................................................................................ 55 Burst Write Transactions with 2,1,1,1 Wait States, 32-Bit 80960 Local Bus ....... 56 Burst Read and Write Transactions without Wait States, 8-Bit 80960 Local Bus57 Burst Read and Write Transactions with 1, 0 Wait States and Extra Tr State on Read, 16-Bit 80960 Local Bus ............................................................................ 58 Bus Transactions Generated by Double Word Read Bus Request, Misaligned One Byte From Quad Word Boundary, 32-Bit 80960 Local Bus................................. 59 HOLD/HOLDA Waveform For Bus Arbitration .................................................... 60 80960 Core Cold Reset Waveform ..................................................................... 61 80960 Local Bus Warm Reset Waveform ........................................................... 62
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Tables
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Related Documentation......................................................................................... 7 80960VH Instruction Set .....................................................................................14 Signal Type Definition ......................................................................................... 15 Signal Descriptions.............................................................................................. 16 Power Requirement, Processor Control and Test Signal Descriptions ............... 19 Interrupt Unit Signal Descriptions........................................................................ 20 PCI Signal Descriptions....................................................................................... 21 Memory Controller Signal Descriptions ............................................................... 22 DMA, I2C Units Signal Descriptions .................................................................... 24 Clock Related Signals ......................................................................................... 24 PBGA 324 Package Dimensions.........................................................................26 324-Plastic Ball Grid Array Ballout -- In Ball Order ............................................ 27 324-Plastic Ball Grid Array Ballout -- In Signal Order ........................................30 324-Lead PBGA Package Thermal Characteristics ............................................ 34 Absolute Maximum Ratings................................................................................. 35 Operating Conditions........................................................................................... 35 VDIFF Specification for Dual Power Supply Requirements (3.3 V, 5 V) ............... 36 DC Characteristics .............................................................................................. 37 ICC Characteristics .............................................................................................. 38 Input Clock Timings............................................................................................. 39 Synchronous Output Timings ..............................................................................39 Synchronous Input Timings................................................................................. 40 Relative Output Timings ...................................................................................... 41 Fast Page Mode Non-interleaved DRAM Output Timings................................... 41 Fast Page Mode Interleaved DRAM Output Timings .......................................... 41 EDO DRAM Output Timings................................................................................ 42 SRAM/ROM Output Timings ............................................................................... 42 Boundary Scan Test Signal Timings ................................................................... 43 I2C Interface Signal Timings ............................................................................... 44 Processor Device ID Register - PDIDR .............................................................. 63
Preliminary Datasheet
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1.0
About This Document
This is the Preliminary data sheet for the low-power (3.3 V) version of Intel's i960(R) VH processor ("80960VH") family. This data sheet contains a functional overview, mechanical data (package signal locations and simulated thermal characteristics), targeted electrical specifications (simulated), and bus functional waveforms. Detailed functional descriptions other than parametric performance is published in the i960(R) VH Processor Developer's Manual.
1.1
Solutions960(R) Program
Intel's Solutions960(R) program features a wide variety of development tools which support the i960 processor family. Many of these tools are developed by partner companies; some are developed by Intel, such as profile-driven optimizing compilers. For more information on these products, contact your local Intel representative.
1.2
Terminology
In this document, the following terms are used:
* local bus refers to the 80960VH's internal local bus, not the PCI local bus. * primary PCI bus is the 80960VH's internal PCI bus which conforms to PCI SIG
specifications.
* 80960 core refers to the 80960JT processor which is integrated into the 80960VH.
1.3
Additional Information Sources
Intel documentation is available from your local Intel Sales Representative or Intel Literature Sales. Call 1-800-879-4683 or visit Intel's website at http://www.intel.com.
Table 1.
Related Documentation
Document Title Order / Contact Intel Order # 273173 Intel Order # 272483 PCI Special Interest Group 1-800-433-5177 Philips Semiconductor
i960 VH Processor Developer's Manual i960(R) Jx Microprocessor User's Guide PCI Local Bus Specification, revision 2.2 I2C Peripherals for Microcontrollers
(R)
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2.0
Functional Overview
As indicated in Figure 1, the 80960VH combines many features with the 80960JT to create a highly integrated processor. Subsections following the figure briefly describe the main features; for detailed functional descriptions, refer to the i960(R) VH Processor Developer's Manual. The PCI bus is an industry standard, high performance, low latency system bus that operates up to 132 Mbyte/sec. The 80960VH is fully compliant with the PCI Local Bus Specification, revision 2.2. Function 0 is the address translation unit. The 80960VH, object code compatible with the i960 core processor, is capable of sustained execution at the rate of one instruction per clock. The local bus, a 32-bit multiplexed burst bus, is a high-speed interface to system memory and I/O. A full complement of control signals simplifies the connection of the 80960VH to external components. Physical and logical memory attributes are programmed via memory-mapped control registers (MMRs), an extension not found on the i960 Kx, Sx or Cx processors. Physical and logical configuration registers enable the processor to operate with all combinations of bus width and data object alignment.
Figure 1. Product Name Functional Block Diagram
I2C Serial Bus
Local Memory
Memory Controller
i960(R) JT
Core Processor I2C Bus Interface Unit Internal Arbitration
Local Bus
Primary ATU Address Translation Unit Core and Peripheral Control Unit
Two DMA Channels
Messaging Unit
Primary PCI Bus
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2.1
2.1.1
Key Functional Units
DMA Controller
The DMA Controller supports low-latency, high-throughput data transfers between PCI bus agents and 80960 local memory. Two separate DMA channels accommodate data transfers for the primary PCI bus. The DMA Controller supports chaining and unaligned data transfers. It is programmable only through the i960 core processor.
2.1.2
Address Translation Unit
The Address Translation Unit (ATU) allows PCI transactions direct access to the 80960VH local memory. The 80960VH has direct access to the PCI bus. The ATU supports transactions between PCI address space and 80960VH address space. Address translation is controlled through programmable registers accessible from the PCI interface and the 80960 core. Dual access to registers allows flexibility in mapping the two address spaces.
2.1.3
Messaging Unit
The Messaging Unit (MU) provides data transfer between the PCI system and the 80960VH. It uses interrupts to notify each system when new data arrives. The MU has two messaging mechanisms. Each allows a host processor or external PCI device and the 80960VH to communicate through message passing and interrupt generation. The two mechanisms are Message Registers and Doorbell Registers.
2.1.4
Memory Controller
The Memory Controller allows direct control of external memory systems, including DRAM, SRAM, ROM and Flash Memory. It provides a direct connect interface to memory that typically does not require external logic. It features programmable chip selects, a wait state generator and byte parity. External memory can be configured as PCI addressable memory.
2.1.5
Core and Peripheral Unit
The Core and Peripheral Unit allows software to control the 80960VH through the primary PCI bus. For example, the 80960 processor core and the 80960VH local bus can be reset via the PCI bus.
2.1.6
I2C Bus Interface Unit
The I2C (Inter-Integrated Circuit) Bus Interface Unit allows the 80960 core to serve as a master and slave device residing on the I2C bus. The I2C bus is a serial bus developed by Philips Semiconductor consisting of a two pin interface. The bus allows the 80960VH to interface to other I2C peripherals and microcontrollers for system management functions. It requires a minimum of hardware for an economical system to relay status and reliability information on the I/O subsystem to an external device. For more information, see I2C Peripherals for Microcontrollers (Philips Semiconductor).
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2.2
i960(R) Core Features (80960JT)
The processing power of the 80960VH comes from the 80960JT processor core. The 80960JT is a new, scalar implementation of the 80960 Core Architecture. Figure * shows a block diagram of the 80960JT Core processor. Factors that contribute to the 80960 family core's performance include:
* * * * * * * *
Single-clock execution of most instructions Independent Multiply/Divide Unit Efficient instruction pipeline minimizes pipeline break latency Register and resource scoreboarding allow overlapped instruction execution 128-bit register bus speeds local register caching 16 Kbyte two-way set-associative, integrated instruction cache 4 Kbyte direct-mapped, integrated data cache 1 Kbyte integrated data RAM delivers zero wait state program data
The 80960 core operates out of its own 32-bit address space, which is independent of the PCI address space. The local bus memory can be:
* Made visible to the PCI address space * Kept private to the 80960 core * Allocated as a combination of the two
Figure 2. 80960JT Core Block Diagram
32-bit buses address / data
P_CLK PLL, Clocks, Power Mgmt Instruction Cache 16 Kbyte Two-Way Set TAP 5 Boundary Scan Controller Instruction Sequencer
Constants Control
Physical Region Configuration Bus Control Unit Bus Request Queues
Control
Address/ Data Bus 32
Two 32-Bit Timers Interrupt Port 9
8-Set Local Register Cache Multiply Divide Unit
Programmable Interrupt Controller Execution and Address Generation Unit
Effective Address SRC1 SRC2 SRC1 SRC2 DST DST
Memory Interface Unit
Memory-Mapped Register Interface
128 Global / Local Register File
SRC1 SRC2 DST
32-bit Addr 32-bit Data SRC1 DST
1 Kbyte Data RAM
4 Kbyte Direct Mapped Data Cache
3 Independent 32-Bit SRC1, SRC2, and DST Buses
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2.2.1
Burst Bus
A 32-bit high-performance bus controller interfaces the 80960VH to external memory and peripherals. The Bus Control Unit fetches instructions and transfers data on the local bus at the rate of up to four 32-bit words per six clock cycles. The external address/data bus is multiplexed. Users may configure the 80960VH's bus controller to match an application's fundamental memory organization. Physical bus width is programmable for up to eight regions. Data caching is programmed through a group of logical memory templates and a defaults register. The Bus Control Unit's features include:
* Multiplexed external bus minimizes pin count * 32-, 16- and 8-bit bus widths simplify I/O interfaces * External ready control for address-to-data, data-to-data and data-to-next-address wait state
types
* Little endian byte ordering * Unaligned bus accesses performed transparently * Three-deep load/store queue decouples the bus from the 80960 core
Upon reset, the 80960VH conducts an internal self test. Before executing its first instruction, it performs an external bus confidence test by performing a checksum on the first words of the Initialization Boot Record.
2.2.2
Timer Unit
The timer unit (TU) contains two independent 32-bit timers that are capable of counting at several clock rates and generating interrupts. Each is programmed by use of the Timer Unit registers. These memory-mapped registers are addressable on 32-bit boundaries. The timers have a singleshot mode and auto-reload capabilities for continuous operation. Each timer has an independent interrupt request to the 80960VH's interrupt controller. The TU can generate a fault when unauthorized writes from user mode are detected.
2.2.3
Priority Interrupt Controller
Low interrupt latency is critical to many embedded applications. As part of its highly flexible interrupt mechanism, the 80960VH exploits several techniques to minimize latency:
* Interrupt vectors and interrupt handler routines can be reserved on-chip * Register frames for high-priority interrupt handlers can be cached on-chip * The interrupt stack can be placed in cacheable memory space 2.2.4 Faults and Debugging
The 80960VH employs a comprehensive fault model. The processor responds to faults by making implicit calls to a fault handling routine. Specific information collected for each fault allows the fault handler to diagnose exceptions and recover appropriately.
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The processor also has built-in debug capabilities. Via software, the 80960VH may be configured to detect as many as seven different trace event types. Alternatively, mark and fmark instructions can generate trace events explicitly in the instruction stream. Hardware breakpoint registers are also available to trap on execution and data addresses.
2.2.5
On-Chip Cache and Data RAM
External memory subsystems often impose substantial wait state penalties. The 80960VH integrates considerable storage resources on-chip to decouple CPU execution from the external bus by including a 16 Kbyte instruction cache, a 4 Kbyte data cache and 1 Kbyte data RAM.
2.2.6
Local Register Cache
The 80960VH rapidly allocates and deallocates local register sets during context switches. The processor needs to flush a register set to the stack only when it saves more than seven sets to its local register cache.
2.2.7
Test Features
The 80960VH incorporates numerous features that enhance the user's ability to test both the processor and the system to which it is attached. These features include ONCE (On-Circuit Emulation) mode and Boundary Scan (JTAG). The 80960VH provides testability features compatible with IEEE Standard Test Access Port and Boundary Scan Architecture (IEEE Std. 1149.1). One of the boundary scan instructions, HIGHZ, forces the processor to float all its output pins (ONCE mode). ONCE mode can also be initiated at reset without using the boundary scan mechanism. ONCE mode is useful for board-level testing. This feature allows a mounted 80960VH to electrically "remove" itself from a circuit board. This mode allows system-level testing where a remote tester can exercise the processor system. The test logic does not interfere with component or system behavior and ensures that components function correctly, and also the connections between various components are correct. The JTAG Boundary Scan feature is an alternative to conventional "bed-of-nails" testing. It can examine connections that might otherwise be inaccessible to a test system.
2.2.8
Memory-Mapped Control Registers
The 80960VH is compliant with 80960 family architecture and has the added advantage of memory-mapped, internal control registers not found on the 80960Kx, Sx or Cx processors. This feature provides software an interface to easily read and modify internal control registers. Each memory-mapped, 32-bit register is accessed via regular memory-format instructions. The processor ensures that these accesses do not generate external bus cycles.
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2.2.9
Instructions, Data Types and Memory Addressing Modes
As with all 80960 family processors, the 80960VH instruction set supports several different data types and formats:
* * * * * * * * * *
Bit Bit fields Integer (8-, 16-, 32-, 64-bit) Ordinal (8-, 16-, 32-, 64-bit unsigned integers) Triple word (96 bits) Quad word (128 bits)
The 80960VH provides a full set of addressing modes for C and assembly: Two Absolute modes Five Register Indirect modes Index with displacement mode IP with displacement mode
Table 2 shows the available instructions.
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Table 2.
80960VH Instruction Set
Arithmetic Add Subtract Multiply Divide Remainder And Not And And Not Or Exclusive Or Not Or Or Not Nor Exclusive Nor Not Nand Set Bit Clear Bit Not Bit Alter Bit Scan For Bit Span Over Bit Extract Modify Scan Byte for Equal Byte Swap Logical Bit, Bit Field and Byte
Data Movement
Load Store Move Conditional Select Load Address
Modulo Shift Extended Shift Extended Multiply Extended Divide Add with Carry Subtract with Carry Conditional Add Conditional Subtract Rotate Comparison Branch
Call/Return Call
Fault
Compare Conditional Compare Compare and Increment Compare and Decrement Test Condition Code Check Bit Debug Processor Management Flush Local Registers Modify Arithmetic Controls Modify Trace Controls Mark Force Mark Modify Process Controls Halt System Control Cache Control Interrupt Control Unconditional Branch Conditional Branch Compare and Branch
Call Extended Call System Return Branch and Link
Conditional Fault Synchronize Faults
Atomic
Atomic Add Atomic Modify
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3.0
3.1
Package Information
Package Introduction
The 80960VH is offered in a Plastic Ball Grid Array (PBGA) package. This is a perimeter array package with five rows of ball connections in the outer area of the package. See Figure , (pg. 26). Section 3.1.1, Functional Signal Definitions describes signal function. Section 3.1.2, 324-Lead PBGA Package defines the signal and ball locations.
3.1.1
Functional Signal Definitions
Table 3 presents the legend for interpreting the Type Field in the following tables. Table 4 defines signals associated with the bus interface. Table 5 defines signals associated with basic control and test functions. Table 6 defines signals associated with the Interrupt Unit. Table 7 defines PCI signals. Table 8 defines Memory Controller signals. Table 9 defines DMA, and I2C signals. Table 10 defines clock signals.
Table 3.
Signal Type Definition
Symbol I O I/O OD - S (...) Input signal only. Output signal only. Signal can be either an input or output. Open Drain signal. Signal must be connected as described. Synchronous. Inputs must meet setup and hold times relative to P_CLK. S(E) Edge sensitive input S(L) Level sensitive input Asynchronous. Inputs may be asynchronous relative to P_CLK. A (...) A(E) Edge sensitive input A(L) Level sensitive input While the P_RST# signal is asserted, the signal: R(1) is driven to V CC R(0) is driven to V SS R(Q) is a valid output R(Z) Floats R(H) is pulled up to V CC R(X) is driven to an unknown state Description
R (...)
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Table 3.
Signal Type Definition
Symbol Description While the is in the hold state, the signal: H (...) H(1) is driven to VCC H(0) is driven to VSS H(Q) Maintains previous state or continues to be a valid output H(Z) Floats While the 80960VH is halted, the signal: P (...) P(1) is driven to V CC P(0) is driven to V SS P(Q) Maintains previous state or continues to be a valid output While the PCI Bus is in park mode, the pin: K (...) K(Z) Floats K(Q) Maintains previous state or continues to be a valid output
Table 4.
Signal Descriptions (Sheet 1 of 4)
NAME TYPE DESCRIPTION ADDRESS / DATA BUS carries 32-bit physical addresses and 8-, 16- or 32bit data to and from memory. During an address (Ta) cycle, bits 2-31 contain a physical word address (bits 0-1 indicate SIZE; see below). During a data (Td) cycle, read or write data is present on one or more contiguous bytes, comprising AD31:24, AD23:16, AD15:8 and AD7:0. During write operations, unused signals are driven to determinate values. SIZE, which comprises bits 0-1 of the AD lines during a Ta cycle, specifies the number of data transfers during the bus transaction on the local bus. I/O S(L) R(Z) H(Z) P(Q) When the DMA or ATUs initiate data transfers, transfer size shown below is not valid. AD1 0 0 1 1 AD0 0 1 0 1 Bus Transfers 1 Transfer 2 Transfers 3 Transfers 4 Transfers
AD31:0
When the 80960VH enters Halt mode and the previous bus operation was: * write -- AD31:2 are driven with the last data value on the AD bus. * read -- AD31:2 are driven with the last address value on the AD bus. Typically, AD1:0 reflect the SIZE information of the last bus transaction (either instruction fetch or load/store) that was executed before entering Halt mode. O R(1) H(Z) P(1) O R(0) H(Z) P(0) ADDRESS STROBE indicates a valid address and the start of a new bus access. The processor asserts ADS# for the entire Ta cycle. External bus control logic typically samples ADS# at the end of the cycle. ADDRESS LATCH ENABLE indicates the transfer of a physical address. ALE is asserted during a Ta cycle and deasserted before the beginning of the Td state. It is active HIGH and floats to a high impedance state during a hold cycle (Th). BURST LAST indicates the last transfer in a bus access. BLAST# is asserted in the last data transfer of burst and non-burst accesses. BLAST# remains active while wait states are detected via the LRDYRCV# or RDYRCV# signal on the memory controller. BLAST# becomes inactive after the final data transfer in a bus cycle. BLAST# has a weak internal pullup which is active during reset to ensure normal operation when the signal is not connected. 0 = Last Data Transfer 1 = Not the Last Data Transfer
ADS#
ALE
O BLAST# R(H) H(Z) P(1)
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Table 4.
Signal Descriptions (Sheet 2 of 4)
NAME TYPE DESCRIPTION BYTE ENABLES select which of up to four data bytes on the bus participate in the current bus access. Byte enable encoding depends on the bus width of the memory region accessed:
BE3:0#
O R(1) H(Z) P(1)
32-bit bus: BE3# enables data on AD31:24 BE2# enables data on AD23:16 BE1# enables data on AD15:8 BE0# enables data on AD7:0 16-bit bus: BE3# becomes Byte High Enable (enables data on AD15:8) BE2# is not used (state is high) BE1# becomes Address Bit 1 (A1) (increments with the assertion of LRDY# or RDYRCV#) BE0# becomes Byte Low Enable (enables data on AD7:0) 8-bit bus: BE3# is not used (state is high) BE2# is not used (state is high) BE1# becomes Address Bit 1 (A1) (increments with the assertion of LRDY# or RDYRCV#) BE0# becomes Address Bit 0 (A0) (increments with the assertion of LRDY# or RDYRCV#) The processor asserts byte enables, byte high enable and byte low enable during Ta. Since unaligned bus requests are split into separate bus transactions, these signals do not toggle during a burst (32-bit bus only) from the i960 core processor; they do toggle for DMA and ATU cycles. They remain active through the last Td cycle.
DATA ENABLE indicates data transfer cycles during a bus access. DEN# is asserted at the start of the first data cycle in a bus access and deasserted at the end of the last data cycle. DEN# is used with DT/R# to provide control for data transceivers connected to the data bus. DEN# has a weak internal pullup which is active during reset to ensure normal operation when the signal is not connected. 0 = Data Cycle 1 = Not a Data Cycle DATA/CODE/RESET_MODE indicates that a bus access is a data access or an instruction access. D/C# has the same timing as W/R#. 0 = Instruction Access 1 = Data Access The RST_MODE# signal is sampled at primary PCI bus reset to determine whether the 80960 core is to be held in reset. When RST_MODE# is high, the 80960VH begins initialization immediately following the deassertion of P_RST#. When RST_MODE# is low, the 80960 core remains in reset until the 80960 core reset bit is cleared in the Reset/Retry control register. This signal has a weak internal pullup that is active during reset to ensure normal operation when the signal is left unconnected. 0 = RST_MODE enabled 1 = RST_MODE not enabled While the 80960 core is in reset, all peripherals may be accessed from the primary PCI bus depending on the status of the WIDTH/HLTD1/RETRY/ signal.
O DEN# R(H) H(Z) P(1)
D/C#/ RST_MODE#
I/O R(H) H(Z) P(Q)
DT/R#
O R(0) H(Z) P(Q)
DATA TRANSMIT/RECEIVE indicates the direction of data transfer to and from the address/data bus. It is low during Ta and Tw/Td cycles for a read; it is high during Ta and Tw /Td cycles for a write. DT/R# never changes state when DEN# is asserted. 0 = Receive 1 = Transmit
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Table 4.
Signal Descriptions (Sheet 3 of 4)
NAME TYPE DESCRIPTION BUS LOCK indicates that an atomic read-modify-write operation is in progress. The LOCK# output is asserted in the first clock of an atomic operation and deasserted in the last data transfer of the sequence. The processor does not grant HOLDA while asserting LOCK#. This prevents external agents from accessing memory involved in semaphore operations. LOCK#/ONCE# I/O S(L) R(H) H(Z) P(Q) 0 = Atomic Read-Modify-Write in Progress 1 = No Atomic Read-Modify-Write in Progress ONCE MODE: The processor samples the ONCE input during reset. When ONCE# is asserted LOW at the end of reset, the processor enters ONCE mode, stops all clocks and floats all output signals. This signal has a weak internal pullup which is active during reset to ensure normal operation when the signal is not connected. 0 = ONCE Mode Enabled 1 = ONCE Mode Not Enabled LOCAL READY/RECOVER, generated by the 80960VH's memory controller unit, is an output version of the READY/RECOVER (RDYRCV#) signal. Refer to the RDYRCV# signal description. LRDYRCV#/ STEST I/O R(H) H(Q) P(Q) SELF TEST enables or disables the processor's internal self-test feature at initialization. STEST is examined at the end of P_RST#. When STEST is asserted, the processor performs its internal self-test and the external bus confidence test. When STEST is deasserted, the processor performs only the external bus confidence test. This signal has a weak internal pullup which is active during reset to ensure normal operation. 0 = Self Test Disabled 1 = Self Test Enabled HOLD is a request from an external bus master to acquire the bus. When the processor receives HOLD and grants bus control to another master, it asserts HOLDA, floats the address/data and control lines and enters the Th state. When HOLD is deasserted, the processor deasserts HOLDA and enters either the Ti or Ta state, resuming control of the address/data and control lines. See Figure , (pg. 61). 0 = No Hold Request 1 = Hold Requested O R(0) H(1) P(Q) HOLD ACKNOWLEDGE indicates to an external bus master that the processor has relinquished bus control. The processor can grant HOLD requests and enter the Th state and while halted as well as during regular operation. See Figure , (pg. 61). 0 = No Hold Acknowledged 1 = Hold Acknowledged READY/RECOVER is only used in systems that use an external memory controller (and do not use the 80960VH's memory controller unit). This signal indicates that data on AD lines can be sampled or removed. When RDYRCV# is not asserted during a Td cycle, the Td cycle extends to the next cycle by inserting a wait state (Tw). 0 = Sample Data 1 = Do Not Sample Data RDYRCV# I S(L) RDYRCV# has an alternate function during the recovery (Tr) state. The processor continues to insert recovery states until it samples the signal HIGH. This gives slow external devices more time to float their buffers before the processor drives addresses. 0 = Insert Wait States 1 = Recovery Complete When using the internal memory controller, connect this signal to V CC through a 2.7 K resistor.
HOLD
I S(L)
HOLDA
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80960VH
Table 4.
Signal Descriptions (Sheet 4 of 4)
NAME TYPE O R(0) H(Z) P(Q) DESCRIPTION WRITE/READ specifies during a Ta cycle whether the operation is a write or read. It is latched on-chip and remains valid during Td cycles. 0 = Read 1 = Write WIDTH denotes the physical memory attributes for a bus transaction in conjunction with WIDTH/HLTD1/RETRY: WIDTH/HLTD1/RETRY WIDTH/HLTD0 I/O R(H) H(Z) P(Q) 0 0 1 1 0 1 0 1 8 Bits Wide 16 Bits Wide 32 Bits Wide Undefined
W/R#
WIDTH/ HLTD0
WIDTH/HLTD0 For proper operation, do not connect this signal to ground. This signal has a weak internal pullup which is active during reset to ensure normal operation. HLTD0 signal name has no function in the 80960VH; the signal name is included for 80960JT naming convention compatibility. WIDTH denotes the physical memory attributes for a bus transaction in conjunction with the WIDTH/HLTD0 signal. Refer to description above. RETRY is sampled at primary PCI bus reset to determine when the primary PCI interface is disabled. When high, the Primary PCI interface disables PCI configuration cycles by signaling a RETRY until the Reset/Retry Control Register's Configuration Cycle Disable bit is cleared. When low, the primary PCI interface allows configuration cycles to occur. WIDTH/HLTD1/RETRY has a weak internal pullup which is active during reset to ensure normal operation when the signal is not connected. When the RST_MODE# pin is asserted, RETRY is internally forced low [inactive] regardless of its external state. HLTD1 signal name has no function in the 80960VH; the signal name is included for 80960JT naming convention compatibility.
WIDTH/ HLTD1/ RETRY
I/O R(H) H(Z) P(Q)
Table 5.
Power Requirement, Processor Control and Test Signal Descriptions (Sheet 1 of 2)
NAME TYPE DESCRIPTION FAIL indicates a failure of the processor's built-in self-test performed during initialization. FAIL# is asserted immediately upon reset and toggles during self-test to indicate the status of individual tests: O R(0) H(Q) * When self-test passes, the processor deasserts FAIL# and commences operation from user code. * When self-test fails, the processor asserts FAIL# and then stops executing. 0 = Self Test Failed 1 = Self Test Passed L_RST# O LOCAL BUS RESET notifies external devices that the local bus has reset. TEST CLOCK is a CPU input that provides the clocking function for IEEE 1149.1 Boundary Scan Testing (JTAG). State information and data are clocked into the processor on the rising edge; data is clocked out of the processor on the falling edge. TEST DATA INPUT is the serial input signal for JTAG. TDI is sampled on the rising edge of TCK, during the SHIFT-IR and SHIFT-DR states of the Test Access Port. This signal has a weak internal pullup to ensure normal operation.
FAIL#
TCK
I
TDI
I S(L)
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19
80960VH
Table 5.
Power Requirement, Processor Control and Test Signal Descriptions (Sheet 2 of 2)
NAME TYPE O R(Q) H(Q) P(Q) I S(L) DESCRIPTION TEST DATA OUTPUT is the serial output signal for JTAG. TDO is driven on the falling edge of TCK during the SHIFT-IR and SHIFT-DR states of the Test Access Port. At other times, TDO floats. TEST MODE SELECT is sampled at the rising edge of TCK to select the operation of the test logic for IEEE 1149.1 Boundary Scan testing. This signal has a weak internal pullup to ensure normal operation. TEST RESET asynchronously resets the Test Access Port (TAP) controller function of IEEE 1149.1 Boundary Scan testing (JTAG). When using the Boundary Scan feature, connect a pulldown resistor (1.5 K) between this signal and VSS. When TAP is not used, this signal must be connected to VSS; however, no resistor is required. The signal has a weak internal pullup which must be overcome during reset to ensure normal operation. NOTE: The system must ensure that TRST# is asserted after power-up to put the TAP controller in a known state. Failure to do so may cause improper processor operation. LCD INITIALIZATION is a static signal used to initialize the internal logic of the LCD960 debugger. This signal has an internal pullup for normal operation. POWER. Connect to a 3.3 Volt power board plane. 5 VOLT REFERENCE VOLTAGE. Input is the reference voltage for the 5 V-tolerant I/O buffers. Connect this signal to +5 V for use with signals which exceed 3.3 V. When all inputs are from 3.3 V components, connect this signal to 3.3 V. GROUND. Connect to a VSS board plane. NO CONNECT. Do not make electrical connections to these balls. PLL POWER. For external connection to a 3.3 V VCC board plane. Power to PLLs requires external filtering. See Section 4.2, VCCPLL Pin Requirements.
TDO
TMS
TRST#
I A(L)
LCDINIT# VCC V CC5REF V SS N.C. VCCPLL2:1
I -
-
- - I
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Table 6.
Interrupt Unit Signal Descriptions
NAME NMI# TYPE I A(L) DESCRIPTION NON-MASKABLE INTERRUPT causes a non-maskable interrupt event to occur. NMI# is the highest priority interrupt source and is level-detect. When NMI# is unused, it is recommended that you connect it to VCC. EXTERNAL INTERRUPT. External devices use this signal to request an interrupt service. These signals operate in dedicated mode, where each signal is assigned a dedicated interrupt level. The XINT3:0# signals can be directed as follows: XINT3:0# I A(L) External Int. XINT0# XINT1# XINT2# XINT3# XINT7:4# I A(L) Primary PCI 80960 Core Processor or or or or XINT0# XINT1# XINT2# XINT3#

P_INTA# P_INTB# P_INTC# P_INTD#
EXTERNAL INTERRUPT. External devices use this signal to request an interrupt service. These signals operate in dedicated mode, where each signal is assigned a dedicated interrupt level.
NOTE: 1. PCI signal functions are summarized in this data sheet. Refer to the PCI Local Bus Specification, revision 2.2 for
a more complete definition.
Table 7.
PCI Signal Descriptions (Sheet 1 of 2)
NAME P_AD31:0 TYPE I/O K(Q) R(Z) I/O K(Q) R(Z) I/O P_DEVSEL# R(Z) I/O P_FRAME# R(Z) P_GNT# P_IDSEL I R(Z) I S(L) O OD R(Z) I/O R(Z) DESCRIPTION 1 PRIMARY PCI ADDRESS/DATA is the primary multiplexed PCI address and data bus. PRIMARY PCI BUS COMMAND and BYTE ENABLE signals are multiplexed on the same PCI signals. During an address phase, P_C/BE3:0# define the bus command. During a data phase, P_C/BE3:0# are used as byte enables. PRIMARY PCI BUS DEVICE SELECT is driven by a target agent that has successfully decoded the address. As an input, it indicates whether or not an agent has been selected. PRIMARY PCI BUS CYCLE FRAME is asserted to indicate the beginning and duration of an access on the Primary PCI bus. PRIMARY PCI BUS GRANT indicates to the agent that access to the bus has been granted. This is a point-to-point signal. PRIMARY PCI BUS INITIALIZATION DEVICE SELECT selects the 80960VH during a Configuration Read or Write command on the primary PCI bus. PRIMARY PCI BUS INTERRUPT requests an interrupt. The assertion and deassertion of P_INTx# is asynchronous to P_CLK. A device asserts its P_INTx# line when requesting attention from its device driver. Once the P_INTx# signal is asserted, it remains asserted until the device driver clears the pending request. P_INTx# Interrupts are level sensitive. PRIMARY PCI BUS INITIATOR READY indicates the initiating agent's (bus master's) ability to complete the current data phase of the transaction.
P_C/BE3:0#
P_INT[A:D]#
P_IRDY#
NOTE: 1. PCI signal functions are summarized in this data sheet; refer to the PCI Local Bus Specification, revision 2.2 for
a more complete definition.
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80960VH
Table 7.
PCI Signal Descriptions (Sheet 2 of 2)
NAME P_LOCK# TYPE I S(L) I/O K(Q) R(Z) I/O R(Z) O K(Q) R(Z) DESCRIPTION1 PRIMARY PCI BUS LOCK indicates an atomic operation that may require multiple transactions to complete. PRIMARY PCI BUS PARITY. This signal ensures even parity across P_AD31:0 and P_C/BE3:0. All PCI devices must provide a parity signal. PRIMARY PCI BUS PARITY ERROR is used for reporting data parity errors during all PCI transactions except a special cycle. PRIMARY PCI BUS REQUEST indicates to the arbiter that this agent desires use of the bus. This is a point to point signal. PRIMARY RESET brings 80960VH to a consistent state. When P_RST# is asserted: * PCI output signals are driven to a known consistent state. P_RST# I A(L) * PCI bus interface output signals are three-stated. * open drain signals such as P_SERR# are floated. * S_RST# asserts. P_RST# may be asynchronous to P_CLK when asserted or deasserted. Although asynchronous, deassertion must be guaranteed to be a clean, bounce-free edge. P_SERR# I/O OD R(Z) I/O P_STOP# R(Z) I/O P_TRDY# R(Z) PRIMARY PCI BUS SYSTEM ERROR reports address and data parity errors on the special cycle command, or any other system error where the result would be catastrophic. PRIMARY PCI BUS STOP indicates that the current target is requesting the master to stop the current transaction on the primary PCI bus. PRIMARY PCI BUS TARGET READY indicates the target agent's (selected device's) ability to complete the current data phase of the transaction.
P_PAR
P_PERR#
P_REQ#
NOTE: 1. PCI signal functions are summarized in this data sheet; refer to the PCI Local Bus Specification, revision 2.2 for
a more complete definition.
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Table 8.
Memory Controller Signal Descriptions (Sheet 1 of 2)
NAME TYPE DESCRIPTION COLUMN ADDRESS STROBE signals are used for DRAM accesses and are asserted when the MA11:0 signals contain a valid column address. CAS7:0# signals are asserted during refresh.
CAS7:0#
O R(1) H(Q) P(Q)
Non-Interleaved Operation: CAS0#,CAS4# = BE0# CAS1#,CAS5# = BE1# CAS2#,CAS6# = BE2# CAS3#,CAS7# = BE3# Interleaved Operation: CAS0# = BE0# CAS1# = BE1# CAS2# = BE2# CAS3# = BE3# CAS4# = BE0# CAS5# = BE1# CAS6# = BE2# CAS7# = BE3#
lane access lane access lane access lane access Even leaf lane access Even leaf lane access Even leaf lane access Even leaf lane access Odd leaf lane access Odd leaf lane access Odd leaf lane access Odd leaf lane access
CE1:0#
O R(1) H(Q) P(Q)
CHIP ENABLE signals indicate an access to one of the two SRAM/ FLASH/ ROM memory banks. CE0# and CE1# are never asserted at the same time. These signals are valid during the entire memory operation. CE0# is asserted for accesses to memory bank 0. CE1# is asserted for accesses to memory bank 1. DRAM ADDRESS LATCH ENABLE signals support external address demultiplexing of the MA11:0 address lines for interleaved DRAM systems. Use these to directly interface to `373' type latches. These signals are only valid for accesses to interleaved memory systems. DALE0 is asserted during a valid even leaf address. DALE1 is asserted during a valid odd leaf address. DATA PARITY carries the parity information for DRAM accesses. Each parity bit corresponds to a group of 8 data bus signals as follows:
DALE1:0
O R(0) H(Q) P(Q)
DP3:0
I/O R(X) H(Q) P(Q)
DP0 -- AD7:0 DP1 -- AD15:8
DP2 -- AD23:16 DP3 -- AD31:24
The memory controller generates parity information for local bus writes during data cycles. During read data cycles, the memory controller checks parity and provides notification of parity errors on the clock following the data cycle. Parity checking and polarity are user-programmable. Parity generation and checking are valid only for data lines that have their associated enable bits asserted.
DWE1:0#
O R(1) H(Q) P(Q)
DRAM WRITE ENABLE signals distinguish between read and write accesses to DRAM. DWE1:0# lines are asserted for writes and deasserted for reads. CAS7:0# determine valid bytes lanes during the access. These two outputs are functionally equivalent for all DRAM accesses; these provide increased drive capability for heavily loaded systems. LEAF ENABLE signals control the data output enables of the memory system during an interleaved DRAM read access. Use these to directly interface to either DRAM or transceiver output enable signals. LEAF0# is asserted during an even leaf access. LEAF1# is asserted during an odd leaf access.
LEAF1:0#
O R(1) H(Q) P(Q)
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80960VH
Table 8.
Memory Controller Signal Descriptions (Sheet 2 of 2)
NAME TYPE DESCRIPTION MULTIPLEXED ADDRESS signals are multi-purpose depending on the device that is selected. O R(X) H(Q) P(Q) For memory banks 0 and 1, these signals output address bits A13:2. These address bits are incremented for each data transfer of a burst access. For DRAM bank, these signals output the row/column multiplexed address bits 11:0. The relationship between the AD31:0 lines and the MA11:0 lines depends on the bank size, type and arrangement of the DRAM that is accessed. MEMORY WRITE ENABLE signals for write accesses to SRAM/FLASH devices. The MWE's rising edge strobes valid data into these devices. MWE0# is asserted for writes to the BE0# MWE1# is asserted for writes to the BE1# MWE2# is asserted for writes to the BE2# MWE3# is asserted for writes to the BE3# lane lane lane lane
MA11:0
MWE3:0#
O R(1) H(Q) P(Q)
ROW ADDRESS STROBE signals are used for DRAM accesses and are asserted when the MA11:0 signals contain a valid row address. RAS3:0# always deasserts after the last data transfer in a DRAM access. RAS3:0# O R(1) H(Q) P(Q)
Non-Interleaved Operation: RAS0# = Bank0 access RAS1# = Bank1 access RAS2# = Bank2 access RAS3# = Bank3 access Interleaved Operation: RAS0,2# = Even leaf RAS1,3# = Odd leaf
Table 9.
DMA, I2C Units Signal Descriptions
NAME TYPE O R(H) H(Q) P(Q) I S(L) I/O OD R(Z) H(Q) P(Q) I/O OD R(Z) H(Q) P(Q) O R(1) H(Q) P(Q) DESCRIPTION DMA DEMAND MODE ACKNOWLEDGE The DMA Controller asserts this signal to indicate (1) it can receive new data from an external device or (2) it has data to send to an external device. This signal has a weak internal pullup which is active during reset to ensure normal operation. DMA DEMAND MODE REQUEST External devices use this signal to indicate (1) new data is ready for transfer to the DMA controller or (2) buffers are available to receive data from the DMA controller.
DACK#
DREQ#
SCL
I2C CLOCK provides synchronous I2C bus operation.
SDA
I2C DATA used for data transfer and arbitration on the I2C bus.
WAIT#
WAIT is an output that allows the DMA controller to insert wait states during DMA accesses to an external memory system.
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80960VH
Table 10. Clock Related Signals
NAME P_CLK TYPE I DESCRIPTION SYNCHRONOUS PCI BUS CLOCK Provides the timing for all primary PCI transactions and is the clock source for all internal units. All input/output timings are relative to P_CLK. CLOCK MODE are used to select the mode of operation in terms of the 80960 local bus / PCI bus vs. the internal 80960 processor core. These signals are internally pulled high. This causes the 80960 processor core to run in DX mode after reset. In this mode, the 80960 processor core speed can be altered by using the Core Select Register (CSR). 00 - DX4 Mode 01 - DX2 Mode 10 - DX Mode 11 - Select Speed via PCI Bus
CLKMODE1:0#
I
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25
80960VH
3.1.2
324-Lead PBGA Package
Figure 3. 324-Plastic Ball Grid Array Top and Side View
Pin #1 Corner
D D1
Pin #1 I.D.
30
E1
E
Seating Plate
f
A2 A A1 C
Top View
Side View
Note: All Dimensions are in Millimeters
A4628-01
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Preliminary Datasheet
80960VH
Figure 4. 324-Plastic Ball Grid Array (Top View)
Pin #1 Corner
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 A B C D E F G H J K
b
e
325 Balls 20 x 20 Matrix
L M N P R T U V W Y
1.0 3 places S1 Top View
A4630-01
e
Table 11. PBGA 324 Package Dimensions
PBGA Package Dimensions Min N (# of balls) A A1 A2 D/E D1/E1 S1 b C e 0.60 0.52 1.27 2.14 0.50 1.12 26.80 23.75 1.44 Ref 0.90 0.60 324 2.52 0.70 1.22 27.20 24.25 Max
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27
80960VH
Table 12. 324-Plastic Ball Grid Array Ballout -- In Ball Order (Sheet 1 of 3)
Ball A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 Signal VSS WAIT# P_AD3 VCC P_C/BE0# VSS P_AD10 VCC P_AD13 P_AD14 P_PAR P_PERR# VCC P_TRDY# VSS P_AD17 P_AD22 P_IDSEL P_C/BE3# VSS DREQ# VSS P_AD0 VCC P_AD5 VSS P_AD9 VCC P_AD12 VSS Ball B12 B13 B14 B15 B16 B17 B18 B19 B20 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 D1 Signal P_LOCK# VCC P_C/BE2# VSS P_AD21 VCC P_AD24 VSS P_AD28 DP3 CLKMODE0 # DACK# P_AD1 P_AD4 P_AD6 P_AD8 P_AD11 NC P_AD15 P_SERR# P_DEVSEL# P_IRDY# P_AD16 P_AD20 P_AD23 P_AD25 P_AD27 P_AD29 VCC DP1 Ball D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 Signal CLKMODE1# VSS P_AD2 VCC P_AD7 VSS NC VCC VCC VCC VSS P_AD18 VCC P_AD26 VSS P_AD30 VCC NC MA9 DP0 DP2 VCC NC NC NC NC NC P_C/BE1# P_STOP# P_FRAME# Ball E14 E15 E16 E17 E18 E19 E20 F1 F2 F3 F4 F5 F6 F14 F15 F16 F17 F18 F19 F20 G1 G2 G3 G4 G5 G6 G16 G17 G18 G19 Signal NC NC NC NC NC NC P_AD31 MA6 VSS MA11 VCC NC VCC VCC VCC NC VCC P_REQ# VSS P_GNT# NC MA5 MA7 MA10 NC VCC NC P_RST# P_INTD# VCC
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Table 12. 324-Plastic Ball Grid Array Ballout -- In Ball Order (Sheet 2 of 3)
Ball B11 H1 H2 H3 H4 H5 H16 H17 H18 H19 H20 J1 J2 J3 J4 J5 J9 J10 J11 J12 J16 J17 J18 J19 J20 K1 K2 K3 K4 K5 K9 Signal VSS VCC VCC MA4 V SS MA8 P_INTC# V SS P_INTB# VCC VCC MA0 MA1 MA2 MA3 VCC V SS VSS VSS VSS ADS# BLAST# SDA SCL P_INTA# LEAF1# V SS DALE0 VCC DALE1 V SS Ball D2 K11 K12 K16 K17 K18 K19 K20 L1 L2 L3 L4 L5 L9 L10 L11 L12 L16 L17 L18 L19 L20 M1 M2 M3 M4 M5 M9 M10 M11 M12 Signal VCC VSS VSS BE0# VCC DT/R# VSS W/R# LEAF0# VSS CE1# VCC CE0# VSS VSS VSS VSS AD31 VCC ALE VSS DEN# DWE1# DWE0# MWE3# MWE2# MWE1# VSS VSS VSS VSS Ball E13 M17 M18 M19 M20 N1 N2 N3 N4 N5 N16 N17 N18 N19 N20 P1 P2 P3 P4 P5 P15 P16 P17 P18 P19 P20 R1 R2 R3 R4 R5 Signal P_AD19 BE3# BE2# BE1# VCC VCC VCC MWE0# V SS CAS5# NC VSS AD30 VCC VCC CAS7# VCC CAS6# CAS3# NC VCC NC AD22 AD27 AD29 VCC5REF V SS V SS CAS2# VCC NC Ball G20 R7 R15 R16 R17 R18 R19 R20 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 U1 U2 U3 Signal VCCPLL2 VCC VCC NC VCC AD23 VSS VSS CAS4# CAS1# RAS3# RAS0# NC NC XINT0# FAIL# D/C#/ RST_MODE# RDYRCV# NC VCC AD6 TCK TDI NC AD17 AD20 AD24 AD28 CAS0# VCC RAS1#
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80960VH
Table 12. 324-Plastic Ball Grid Array Ballout -- In Ball Order (Sheet 3 of 3)
Ball K10 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 Signal VSS VCC VCC WIDTH/HLTD0 VSS VCC VCC VCC VCC VSS AD9 VCC VCC VSS AD18 VCC AD25 RAS2# XINT7# XINT6# XINT4# XINT2# WIDTH/HLTD1/RETRY NC LOCK#/ONCE# HOLDA TDO AD0 AD2 Ball M16 V13 V14 V15 V16 V17 V18 V19 V20 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 Signal AD26 AD5 AD8 TMS AD12 AD13 AD16 AD19 AD21 NC VSS VCC VCC LRST# V SS VCC VCC NMI# VSS VSS AD3 VCC VCC V SS NC AD11 VCC V SS P_CLK Ball R6 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Signal VCC VSS XINT5# XINT3# XINT1# VCC VSS LCDINIT# HOLD LRDYRCV#/ STEST VCCPLL1 AD1 AD4 AD7 TRST# VSS AD10 NC AD14 AD15 VSS Ball U4 Signal VSS
NOTE: 1. Do not connect any external logic to balls marked NC (no connect balls).
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Table 13. 324-Plastic Ball Grid Array Ballout -- In Signal Order (Sheet 1 of 3)
Signal AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 Ball V11 Y11 V12 W12 Y12 V13 T13 Y13 V14 U14 Y16 W17 V16 V17 Y18 Y19 V18 T17 U18 V19 T18 V20 P17 R18 T19 U20 M16 P18 T20 P19 N18 Signal AD31 ADS# ALE BE0# BE1# BE2# BE3# BLAST# CAS0# CAS1# CAS2# CAS3# CAS4# CAS5# CAS6# CAS7# CE0# CE1# CLKMODE0# CLKMODE1# D/C#/RST_MODE# DACK# DALE0 DALE1 DEN# DP0 DP1 DP2 DP3 DREQ# DT/R# Ball L16 J16 L18 K16 M19 M18 M17 J17 U1 T2 R3 P4 T1 N5 P3 P1 L5 L3 C2 D3 T9 C3 K3 K5 L20 E2 D1 E3 C1 B1 K18 Signal DWE0# DWE1# FAIL# HOLD HOLDA LCDINIT# LEAF0# LEAF1# LOCK#/ONCE# LRDYRCV#/STEST LRST# MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7 MA8 MA9 MA10 MA11 MWE0# MWE1# MWE2# MWE3# NC NC NC NC Ball M2 M1 T8 Y8 V9 Y7 L1 K1 V8 Y9 W5 J1 J2 J3 J4 H3 G2 F1 G3 H5 E1 G4 F3 N3 M5 M4 M3 C9 D9 D20 E5 Signal NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NMI# P_AD0 P_AD1 Ball E6 E7 E8 E9 E14 E15 E16 E17 E18 E19 F5 F16 G1 G5 G16 N16 P5 P16 R5 R16 T5 T6 T11 T16 V7 W1 W16 Y17 W9 B3 C4
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80960VH
Table 13. 324-Plastic Ball Grid Array Ballout -- In Signal Order (Sheet 2 of 3)
Signal P_AD2 P_AD3 P_AD4 P_AD5 P_AD6 P_AD7 P_AD8 P_AD9 P_AD10 P_AD11 P_AD12 P_AD13 P_AD14 P_AD15 P_AD16 P_AD17 P_AD18 P_AD19 P_AD20 P_AD21 P_AD22 P_AD23 P_AD24 P_AD25 P_AD26 P_AD27 P_AD28 P_AD29 P_AD30 P_AD31 P_C/BE0# Ball D5 A3 C5 B5 C6 D7 C7 B7 A7 C8 B9 A9 A10 C10 C14 A16 D14 E13 C15 B16 A17 C16 B18 C17 D16 C18 B20 C19 D18 E20 A5 Signal P_C/BE1# P_C/BE2# P_C/BE3# P_CLK P_DEVSEL# P_FRAME# P_GNT# P_IDSEL P_INTA# P_INTB# P_INTC# P_INTD# P_IRDY# P_LOCK# P_PAR P_PERR# P_REQ# P_RST# P_SERR# P_STOP# P_TRDY# RAS0# RAS1# RAS2# RAS3# RDYRCV# SCL SDA TCK TDI TDO Ball E10 B14 A19 W20 C12 E12 F20 A18 J20 H18 H16 G18 C13 B12 A11 A12 F18 G17 C11 E11 A14 T4 U3 V1 T3 T10 J19 J18 T14 T15 V10 Signal TMS TRST# VCC V CC V CC VCC VCC V CC VCC V CC V CC V CC V CC V CC V CC VCC V CC V CC VCC VCC V CC V CC VCC V CC V CC VCC VCC VCC V CC V CC VCC Ball V15 Y14 A8 A13 B4 B8 B13 B17 D2 D6 D10 D11 D15 D19 F4 F6 F14 F15 F17 G6 H1 H2 H19 H20 K4 K17 L4 L17 N1 N2 N19 Signal VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC Ball N20 P15 R4 R6 R7 R15 R17 U2 U6 U10 U11 U15 U19 W4 W8 W13 Y5 A4 D12 G19 J5 M20 P2 U5 U9 U12 U16 W3 W7 W14 W18
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Table 13. 324-Plastic Ball Grid Array Ballout -- In Signal Order (Sheet 3 of 3)
Signal VCC VCC VCC VCC5REF VCCPLL1 VCCPLL2 VSS VSS VSS VSS VSS V SS V SS V SS VSS VSS VSS V SS VSS V SS V SS VSS VSS V SS V SS VSS VSS V SS Ball C20 E4 T12 P20 Y10 G20 A1 A6 A15 A20 B2 B6 B10 B11 B15 B19 D4 D8 D13 D17 F2 F19 H4 H17 J9 J10 J11 J12 Signal VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Ball K2 K9 K10 K11 K12 K19 L2 L9 L10 L11 L12 L19 M9 M10 M11 M12 N4 N17 R1 R2 R19 R20 U4 U8 U13 U17 W2 W6 Signal VSS VSS VSS VSS VSS VSS VSS VSS W/R# WAIT# WIDTH/HLTD0 WIDTH/HLTD1/RETRY XINT0# XINT1# XINT2# XINT3# XINT4# XINT5# XINT6# XINT7# Ball W10 W11 W15 W19 Y1 Y6 Y15 Y20 K20 A2 U7 V6 T7 Y4 V5 Y3 V4 Y2 V3 V2 Signal Ball
NOTE: 1. Do not connect any external logic to balls marked NC (no connect balls).
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33
80960VH
3.2
Package Thermal Specifications
The device is specified for operation when TC (case temperature) is within the range of 0 C to 95 C. Case temperature may be measured in any environment to determine whether the processor is within specified operating range. Measure the case temperature at the center of the top surface, opposite the ballpad.
3.2.1
Thermal Specifications
This section defines the terms used for thermal analysis.
3.2.1.1
Ambient Temperature
Ambient temperature, TA, is the temperature of the ambient air surrounding the package. In a system environment, ambient temperature is the temperature of the air upstream from the package.
3.2.1.2
Case Temperature
To ensure functionality and reliability, the device is specified for proper operation when the case temperature, TC, is within the specified range in Table 16, Operating Conditions (pg. 36). When measuring case temperature, attention to detail is required to ensure accuracy. If a thermocouple is used, then calibrate it before taking measurements. Errors may result when the measured surface temperature is affected by the surrounding ambient air temperature. Such errors may be due to a poor thermal contact between thermocouple junction and the surface, heat loss by radiation, or conduction through thermocouple leads. To minimize measurement errors:
* Use a 35 gauge K-type thermocouple or equivalent. * Attach the thermocouple bead or junction to the package top surface at a location
corresponding to the center of the die (). The center of the die gives a more accurate measurement and less variation as the boundary condition changes.
* Attach the thermocouple bead or junction at a 90 angle by an adhesive bond (such as thermal
epoxy or heat-tolerant tape) to the package top surface as shown in .
Figure 5. Thermocouple Attachment
Thermocouple Wire Thermocouple Bead Epoxy Fillet
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80960VH
3.2.1.3
Thermal Resistance
The thermal resistance value for the case-to-ambient, CA, is used as a measure of the cooling solution's thermal performance.
3.2.2
Thermal Analysis
Table 14 lists the case-to-ambient thermal resistances of the 80960VH for different air flow rates without a heat sink. To calculate TA, the maximum ambient temperature to conform to a particular case temperature: TA = TC - P (CA) Compute P by multiplying ICC and VCC. Values for JC and CA are given in Table 14. Junction temperature (TJ) is commonly used in reliability calculations. TJ can be calculated from JC (thermal resistance from junction to case) using the following equation: TJ = TC + P (JC) Similarly, when TA is known, the corresponding case temperature (TC) can be calculated as follows: TC = TA + P (CA) The JA (Junction-to-Ambient) for this package is currently estimated at 26.54 C/Watt with no airflow. JA = JC + CA
Table 14. 324-Lead PBGA Package Thermal Characteristics
Thermal Resistance -- C/Watt Airflow -- ft./min (m/sec) Parameter 0 (0) 1.36 25.18 100 (0.50) 1.36 20.30 200 (1.01) 1.36 18.29 400 (2.03) 1.36 16.57 600 (3.04) 1.36 15.55 800 (4.06) 1.36 14.75
JC (Junction-to-Case) CA (Case-to-Ambient) Without Heatsink
JA
JC
CA
NOTE: 1. This table applies to a PBGA device soldered directly onto a board.
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35
80960VH
4.0
Electrical Specifications
Table 15. Absolute Maximum Ratings
Parameter Storage Temperature Case Temperature Under Bias Supply Voltage wrt. VSS Supply Voltage wrt. VSS on VCC5 Voltage on Any Ball wrt. V SS Maximum Rating -55 C to + 125 C 0 C to + 95 C -0.5 V to + 4.6 V -0.5 V to + 6.5 V -0.5 V to VCC + 0.5 V
NOTICE: This data sheet contains information on products in the design phases of development. The specifications are subject to change without notice. Contact your local Intel representative before finalizing a design. WARNING: Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. Operation beyond the "Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions" may affect device reliability.
Table 16. Operating Conditions
Symbol VCC VCC5 FP_CLK TC Parameter Supply Voltage Input Protection Bias Input Clock Frequency Case Temperature Under Bias i960(R) VH processor (324 PBGA) Min 3.0 3.0 16 0 Max 3.6 5.25 33.33 95 Units V V MHz C (1) (1) Notes
NOTE: 1. The 80960VH processor is produced on Intel's advanced CMOS process. Proper bulk decoupling must be used to prevent device damage during power up and power down. Power supply behavior during these transitions, without proper bulk decoupling, can cause the power supply to exceed the maximum VCC specification, causing device damage.
4.1
VCC5 Pin Requirements (VDIFF)
In mixed voltage systems that drive 80960VH inputs in excess of 3.3 V, the VCC5 pin must be connected to the system's 5 V supply. To limit current flow into the VCC5 pin, there is a limit to the voltage differential between the V CC5 pin and the other V CC pins. The voltage differential between the 80960VH VCC5 pin and its 3.3 V VCC pins should never exceed 2.25 V. This limit applies to power-up, power-down, and steady-state operation. Table 17 outlines this requirement. Meeting this requirement ensures proper operation and guarantees that the current draw into the V CC5 pin does not exceed the ICC5 specification. If the voltage difference requirements cannot be met due to system design limitations, then an alternate solution may be employed. As shown in Figure 6., a minimum of 100 series resistor may be used to limit the current into the V CC5 pin. This resistor ensures that current drawn by the VCC5 pin does not exceed the maximum rating for this pin.
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Preliminary Datasheet
80960VH
Figure 6. VCC5 Current-Limiting Resistor
+5 V (0.25 V) 100 (5%, 0.5 W)
VCC5 Pin
This resistor is not necessary in systems that can guarantee the V DIFF specification. In 3.3 V-only systems and systems that drive 80960VH pins from 3.3 V logic, connect the V CC5 pin directly to the 3.3 V V CC plane. Table 17. VDIFF Specification for Dual Power Supply Requirements (3.3 V, 5 V)
Symbol VDIFF Parameter VCC5-VCC Difference Min Max 2.25 Units V Notes VCC5 input should not exceed VCC by more than 2.25 V during power-up and power-down, or during steady-state operation.
4.2
VCCPLL Pin Requirements
To reduce clock skew on the i960 Jx processor, the VC CP L L pin for the Phase Lock Loop (PLL) circuit is isolated on the pinout. The lowpass filter, as shown in Figure 7., reduces noise-induced clock jitter and its effects on timing relationships in system designs. The 4.7 F capacitor must be (low ESR solid tantalum), the 0.01 F capacitor must be of the type X7R and the node connecting VC CP L L must be as short as possible.
Figure 7. VCCPLL Lowpass Filter
10, 5%, 1/8W
VCC (Board Plane)
+ 4.7F 0.01F
VCCPLL (On i960(R) Jx processors)
F_CA078A
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80960VH
4.3
DC Specifications
Table 18. DC Characteristics
Symbol VIL VIH1 VOL1 VOH1 VOL2 VOH2 VOL3 VOH3 VOL4 VOH4 CIN COUT CCLK CIDSEL LPIN Parameter Input Low Voltage Input High Voltage for all signals except P_CLK Output Low Voltage Processor signals Output High Voltage Processor signals Output Low Voltage PCI signals Output High Voltage PCI signals Output Low Voltage Memory Controller Normal drive Output High Voltage Memory Controller Normal drive Output Low Voltage Memory Controller High Drive Output High Voltage Memory Controller High Drive Input Capacitance - PBGA I/O or Output Capacitance - PBGA P_CLK Capacitance - PBGA IDSEL Ball Capacitance Ball Inductance 5 2.4 10 10 12 8 20 2.4 0.45 2.4 0.45 2.4
VCC - 0.5
Min -0.5 2.0
Max 0.8
VCC +
Units V V V V (1) (1)
Notes
0.5 0.45
I OL = 6 mA (3) IOH = -2 mA (3) IOH = -200 A (3) IOL = 1.5 mA (1) IOH = 0.5 mA (1) IOL = 6 mA (4) IOH = -2 mA (4) IOL = 7 mA
0.55
V V V V V V pF pF pF pF nH
IOH = -2 mA FP_CLK = TF Min (1, 2) FP_CLK = TF Min (1, 2) FP_CLK = TF Min (1, 2) (1) (1)
NOTES: 1. As required by the PCI Local Bus Specification, revision 2.2. 2. Not tested. 3. Processor signals include AD31:0, ALE, ADS#, BE3:0#, WIDTH/HLTD0, WIDTH/HLTD1/RETRY, D/C#/RST_MODE#, W/ R#, DT/R#, DEN#, BLAST#, LRDYRCV#, LOCK#/ONCE#, HOLD, FAIL#, TDO, DACK#, WAIT#, SDA, SCL. 4. Memory Controller signals include MA11:0, DP3:0, RAS3:0#, CAS7:0#, MWE3:0#, DWE1:0#, DALE1:0, CE1:0#, LEAF1:0#. 5. Memory Controller signals capable of high drive are MA11:0, CAS7:0#, RAS3:0#, DWE1:0#.
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Table 19. ICC Characteristics
Symbol Parameter Input Leakage Current for each signal except PCI Bus Signals, LOCK#/ONCE#, WIDTH/ HLTD0, WIDTH/HLTD1/RETRY, BLAST#, D/C#/RST_MODE#, DEN#, TMS, TRST#, TDI, DACK#/PLLEN, LCDINIT#, LRDYRCV#/STEST, CLKMODE1:0# Input Leakage Current for LOCK#/ONCE#, WIDTH/HLTD0, WIDTH/HLTD1/RETRY, BLAST#, D/C#/RST_MODE#, DEN#, TMS, TRST#, TDI, DACK#/PLLEN, LCDINIT#, LRDYRCV#/STEST, CLKMODE1:0# Input Leakage Current for PCI Bus Signals (except PCLK) Output Leakage Current Power Supply Current i960(R) VH processor ICC Active (Power Supply) DX Mode DX2 Mode DX4 Mode Thermal Current i960(R) VH processor ICC Active (Thermal) DX Mode DX2 Mode DX4 Mode ICC Active (Power Modes) Reset Mode i960(R) VH processor ONCE Mode i960(R) VH processor 390 550 690 470 40 mA mA mA (1,3) (1,3) (1,3) (4) (4) 450 590 720 mA mA mA (1,2) (1,2) (1,2) Typ Max Units Notes
ILI1
5
A
VIN = 0.8 V (VIL) and 2.0 V (VIH )
ILI2
-140
-250
A
VIN = 0.45 V (1)
ILI3 ILO
5 5
A A
VIN = 0.8 V (VIL) and 2.0 V (VIH ) 0.4 VOUT VCC
mA
NOTES: 1. Measured with device operating and outputs loaded to the test condition in Figure 8. 2. ICC Active (Power Supply) value is provided for selecting your system's power supply. It is measured using one of the worst case instruction mixes with VCC = 3.6 V and ambient temperature = 55 C. This parameter is characterized but not tested. 3. ICC Active (Thermal) value is provided for your system's thermal management. Typical ICC is measured with VCC = 3.3 V and ambient temperature = 55 C. This parameter is characterized but not tested. 4. ICC Active (Power modes) refers to the ICC values that are tested when the device is in Reset mode or ONCE mode with VCC = 3.6 V and ambient temperature = 55 C.
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80960VH
4.4
AC Specifications
Table 20. Input Clock Timings
Symbol TF TC TCS TCH TCL TCR TCF Parameter P_CLK Frequency P_CLK Period P_CLK Period Stability P_CLK High Time P_CLK Low Time P_CLK Rise Time P_CLK Fall Time 12 12 4 4 Min 16 30 Max 33.33 62.5 250 Units MHz ns ps ns ns V/ns V/ns (1) Adjacent Clocks (2,3) Measured at 1.5 V (2,3) Measured at 1.5 V (2,3) 0.4 V to 2.4 V (2,3) 2.4 V to 0.4 V (2,3) Notes
NOTES: 1. See Figure 9, (pg. 46). 2. To ensure a 1:1 relationship between the amplitude of the input jitter and the internal clock, the jitter frequency spectrum should not have any power peaking between 500 KHz and 1/3 of the P_CLK frequency. 3. Not tested.
Table 21. Synchronous Output Timings
Symbol TOV1 TOV2 TOV3 TOV4 TOV5 TOF Parameter Output Valid Delay - All Local Bus Signals Except ALE Inactive and DT/R# Output Valid Delay, DT/R# Output Valid Delay - PCI Signals Except P_REQ# Output Valid Delay P_REQ# Output Valid Delay - DP3:0 Output Float Delay Min 2 0.5 TC +3 2 2 3 3 Max 15.5 0.5 TC +15 11 12 19 13 Units ns ns ns ns ns ns Notes (1,2,5) (2,5) (2,5) (2,5) (2,5) (3,4,5)
NOTES: 1. Inactive ALE refers to the falling edge of ALE. For inactive ALE timings, see Table 23, Relative Output Timings (pg. 42). 2. See Figure 10, (pg. 46). 3. A float condition occurs when the output current becomes less than ILO. Float delay is not tested, but is designed to be no longer than the valid delay. 4. See Figure 11, (pg. 47). 5. Outputs precharged to VCC5 maximum.
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Table 22. Synchronous Input Timings
Sym TIS1 TIS1A TIS1B TIH1 TIS2 TIH2 TIS3 TIH3 TIS4 TIH4 TIS5 TIH5 TIS6 TIS6 TIH6 TIS7 TIS8 TIH8 Parameter Input Setup to P_CLK -- NMI#, XINT7:0#, DP3:0 Input Setup to P_CLK -- for all accesses except Expansion ROM Accesses -- AD31:0 only Input Setup to P_CLK during Expansion ROM Accesses -- AD31:0 only Input Hold from P_CLK -- AD31:0, NMI#, XINT7:0#, DP3:0 Input Setup to P_CLK -- RDYRCV# and HOLD Input Hold from P_CLK -- RDYRCV# and HOLD Input Setup to P_CLK -- LOCK#/ONCE#, STEST Input Hold from P_CLK -- LOCK#/ONCE#, STEST Input Setup to P_CLK -- DREQ# Input Hold from P_CLK -- DREQ# Input Setup to P_CLK -- PCI Signals Except P_GNT# Input Hold from P_CLK -- PCI Signals Input Setup to P_CLK -- P_RST# - DX4 Mode Input Setup to P_CLK -- P_RST# - DX2 and DX Mode Input Hold to P_CLK -- P_RST# Input Setup to P_CLK -- P_GNT# Input Setup to P_RST# -- WIDTH/HLTD0, WIDTH/HLTD1/RETRY, D/C#/RST_MODE# Input Hold from P_RST# -- WIDTH/HLTD0, WIDTH/HLTD1/RETRY, D/C#/RST_MODE# Min 6 6 8 2 10 2 7 3 12 7 7 0 6 10 2 10 7 3 Max Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Notes (1,2) (1,2) (1,2) (1,2,4) (2) (2) (1,2,4) (1,2,4) (2) (2) (2) (2,4) (2,3) (2,3) (2,3,4) (2) (1,2,4) (1,2,4)
NOTES: 1. Setup and hold times must be met for proper processor operation. NMI#, and XINT7:0# may be synchronous or asynchronous. Meeting setup and hold time guarantees recognition at a particular clock edge. For asynchronous operation, NMI#, and XINT7:0# must be asserted for a minimum of two P_CLK periods to guarantee recognition. 2. See Figure 12, (pg. 47). 3. P_RST# may be synchronous or asynchronous. Meeting setup and hold time guarantees recognition at a particular clock edge. 4. Guaranteed by design. May not be 100% tested.
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80960VH
4.4.1
Relative Output Timings
Table 23. Relative Output Timings
Symbol TLXL TLXA TDXD ALE Width Address Hold from ALE Inactive DT/R# Valid to DEN# Active Parameter Min 0.5TC-3 0.5TC-1 0.5TC-3 Max Units ns ns ns (1,2,4) Equal Loading (1,2,4) Equal Loading (1,3,4) Notes
NOTES: 1. Guaranteed by design. May not be 100% tested. 2. See Figure 13, (pg. 47). 3. See Figure 14, (pg. 48) 4. Outputs precharged to VCC5 maximum.
4.4.2
Memory Controller Relative Output Timings
Table 24. Fast Page Mode Non-interleaved DRAM Output Timings
Symbol TOV6 TOV7 TOV8 TOV9 TOV10 TOV11 Description RAS3:0# Rising and Falling edge Output Valid Delay CAS7:0# Rising Edge Output Valid Delay CAS7:0# Falling Edge Output Valid Delay MA11:0 Output Valid Delay-Row Address MA11:0 Output Valid Delay-Column Address DWE1:0# Rising and Falling edge Output Valid Delay Min 1 1 0.5Tc+1 0.5Tc+1 1 1 Max 9 8 0.5Tc+8 0.5Tc+10 10 11 Units ns ns ns ns ns ns Notes 2 2 1,2 1,2 2 2
NOTES: 1. Signal generated on the rising edge of an internally generated 2XCLK which corresponds to the center of an P_CLK period. For testing purposes, the signal is specified relative to the rising edge of P_CLK with the 0.5Tc period offset. 2. Output switching between VCC3 maximum and VSS.
Table 25. Fast Page Mode Interleaved DRAM Output Timings (Sheet 1 of 2)
Symbol TOV12 TOV13 TOV14 TOV15 TOV16 TOV17 Description RAS3:0# Rising and Falling edge Output Valid Delay CAS7:0# Rising Edge Output Valid Delay CAS7:0# Falling Edge Output Valid Delay MA11:0 Output Valid Delay-Row Address MA11:0 Output Valid Delay-Column Address DWE1:0# Rising and Falling Edge Output Valid Delay Min 1 1 0.5Tc+1 0.5Tc+1 1 1 Max 9 8 0.5Tc+8 0.5Tc+10 10 11 Units ns ns ns ns ns ns Notes 2 2 1,2 1,2 2 2
NOTES: 1. Signal generated on the rising edge of an internally generated 2XCLK which corresponds to the center of an P_CLK period. For testing purposes, the signal is specified relative to the rising edge of P_CLK with the 0.5Tc period offset. 2. Output switching between VCC3 maximum and VSS.
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Table 25. Fast Page Mode Interleaved DRAM Output Timings (Sheet 2 of 2)
Symbol TOV18 TOV19 TOV20 TOV21 Description DALE1:0 Initial Falling Edge Output Valid Delay DALE1:0 Burst Falling Edge Output Valid Delay DALE1:0 Rising Edge Output Valid Delay LEAF1:0# Rising and Falling Edge Output Valid Delay Min 1 0.5Tc+1 1 1 Max 10 0.5Tc+10 10 10 Units ns ns ns ns Notes 2 1,2 2 2
NOTES: 1. Signal generated on the rising edge of an internally generated 2XCLK which corresponds to the center of an P_CLK period. For testing purposes, the signal is specified relative to the rising edge of P_CLK with the 0.5Tc period offset. 2. Output switching between VCC3 maximum and VSS.
Table 26. EDO DRAM Output Timings
Symbol TOV22 TOV23 TOV24 TOV25 TOV26 TOV27 TOV28 TOV29 TOV30 Description RAS3:0# Rising and Falling Edge Output Valid Delay CAS7:0# Rising Edge Output Valid Delay Read Cycles CAS7:0# Falling Edge Output Valid Delay Read Cycles CAS7:0# Rising Edge Output Valid Delay Write Cycles CAS7:0# Falling Edge Output Valid Delay Write Cycles MA11:0 Output Valid Delay - Row Address MA11:0 Output Valid Delay - Column Address Read Cycles MA11:0 Output Valid Delay - Column Address Write Cycles DWE1:0# Rising and Falling Edge Output Valid Delay Min 1 0.5Tc+1 1 1 0.5Tc+1 0.5Tc+1 0.5Tc+1 1 1 Max 9 0.5Tc+8 8 8 0.5Tc+8 0.5Tc+10 0.5Tc+10 10 11 Units ns ns ns ns ns ns ns ns ns Note s 2 1,2 2 2 1,2 1,2 1,2 2 2
NOTES: 1. Signal generated on the rising edge of an internally generated 2XCLK which corresponds to the center of an P_CLK period. For testing purposes, the signal is specified relative to the rising edge of P_CLK with the 0.5Tc period offset. 2. Output switching between VCC3 maximum and VSS.
Table 27. SRAM/ROM Output Timings (Sheet 1 of 2)
Symbol TOV40 TOV41 TOV42 Description CE1:0# Rising and Falling Edge Output Valid Delay MWE3:0# Rising Edge Output Valid Delay MWE3:0# Falling Edge Output Valid Delay Min 1 1 0.5Tc+1 Max 8 9 0.5Tc +9 Units ns ns ns Notes 2 2 1,2
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80960VH
Table 27. SRAM/ROM Output Timings (Sheet 2 of 2)
Symbol TOV43 TOV44 Description MA11:0 Output Valid Delay - Initial Address MA11:0 Output Valid Delay - Burst Address Min 0.5Tc+1 1 Max 0.5Tc +10 10 Units ns ns Notes 2 2
NOTES: 1. Signal generated on the rising edge of an internally generated 2XCLK which corresponds to the center of an P_CLK period. For testing purposes, the signal is specified relative to the rising edge of P_CLK with the 0.5Tc period offset. 2. Output switching between VCC3 maximum and VSS.
4.4.3
Boundary Scan Test Signal Timings
Table 28. Boundary Scan Test Signal Timings
Symbol TBSF TBSCH TBSCL TBSCR TBSCF TBSIS1 TBSIH1 TBSOV1 TBSOF1 TBSOV2 TBSOF2 TBSIS2 TBSIH2 Parameter TCK Frequency TCK High Time TCK Low Time TCK Rise Time TCK Fall Time Input Setup to TCK -- TDI, TMS Input Hold from TCK -- TDI, TMS TDO Valid Delay TDO Float Delay All Outputs (Non-Test) Valid Delay All Outputs (Non-Test) Float Delay Input Setup to TCK -- All Inputs (Non-Test) Input Hold from TCK -- All Inputs (Non-Test) 4 6 3 3 3 3 4 6 30 30 30 30 Min 0 15 15 5 5 Max 0.5TF Units MHz ns ns ns ns ns ns ns ns ns ns ns ns (1) Relative to falling edge of TCK (1,2) Relative to falling edge of TCK (1,2) Relative to falling edge of TCK (1,2) Relative to falling edge of TCK (1,2) (1) (1) Measured at 1.5 V (1) Measured at 1.5 V (1) 0.8 V to 2.0 V (1) 2.0 V to 0.8 V (1) Notes
NOTES: 1. Guaranteed by design. Not tested. 2. Outputs precharged to VCC5 maximum.
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4.4.4
I2C Interface Signal Timings
Table 29. I2C Interface Signal Timings
Std. Mode Symbol FSCL TBUF THDSTA TLOW THIGH TSUSTA THDDAT TSUDAT TR TF TSUSTO Parameter Min SCL Clock Frequency Bus Free Time Between STOP and START Condition Hold Time (repeated) START Condition SCL Clock Low Time SCL Clock High Time Setup Time for a Repeated START Condition Data Hold Time Data Setup Time SCL and SDA Rise Time SCL and SDA Fall Time Setup Time for STOP Condition 4 0 4.7 4 4.7 4 4.7 0 250 1000 300 Max 100 Min 0 1.3 0.6 1.3 0.6 0.6 0 100 20+0.1Cb 20+0.1Cb 0.6 300 300 0.9 Max 400 KHz s s s s s s ns ns ns s (1) (1,3) (1,2) (1,2) (1) (1) (1) (1,4) (1,4) (1) Fast Mode Units Notes
NOTES: 1. See Figure 15, (pg. 48). 2. Not tested. 3. After this period, the first clock pulse is generated. 4. Cb = the total capacitance of one bus line, in pF.
4.5
AC Test Conditions
The AC Specifications in Section 4.4, AC Specifications (pg. 40) are tested with the 50 pF load indicated in .
Figure 8. AC Test Load
Output Ball CL CL = 50 pF for all signals
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45
80960VH
4.6
AC Timing Waveforms
Figure 9. P_CLK, TCLK Waveform
TCR TCF
2.0V
1.5V
0.8V
TCH
TCL
TC
Figure 10. TOV Output Delay Waveform
P_CLK
1.5V
1.5V
TOVX Max
TOVX Min
1.5V
Valid
1.5V
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Preliminary Datasheet
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Figure 11. TOF Output Float Waveform
P_CLK
1.5V
1.5V
TOF
Figure 12. TIS and TIH Input Setup and Hold Waveform
P_CLK
1.5V
1.5V
1.5V
TIHX TISX
1.5V
Valid
Figure 13. TLXL and TLXA Relative Timings Waveform
TA TW/TD
P_CLK
1.5V TLXL
1.5V
1.5V
ALE 1.5V
Valid
1.5V
TLXA AD31:0 1.5V 1.5V
Valid
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80960VH
Figure 14. DT/R# and DEN# Timings Waveform
TA TW/TD
P_CLK
1.5V TOVX
1.5V
1.5V
DT/R#
Valid
TDXD
DEN#
TOVX
Figure 15. I2C Interface Signal Timings
SDA
TBUF TLOW
TR
TF
THDSTA
TSP
SCL
THDSTA THDDAT Stop Start THIGH TSUSTO TSUDAT TSUSTA Repeated Start Stop
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4.7
Memory Controller Output Timing Waveforms
Figure 16. Fast Page-Mode Read Access, Non-Interleaved, 2,1,1,1 Wait State, 32-Bit 80960 Local Bus
TA P_CLK Tw Tw Td Tw Td Tw Td Tw Td Tr
AD31:0
ADDR
DATA In
DATA In
DATA In
DATA In
MA11:0
ROW
COL
COL
COL
COL
ALE
ADS#
W/R#
BLAST#
DT/R#
DEN#
DWE0#
RAS0#
CAS3:0#
LRDYRCV# RDYRCV#
Preliminary Datasheet
49
80960VH
Figure 17. Fast Page-Mode Write Access, Non-Interleaved, 2,1,1,1 Wait States, 32-Bit 80960 Local Bus
TA P_CLK
DATA OUT DATA OUT DATA OUT DATAO UT
Tw
Tw
Td
Tw
Td
Tw
Td
Tw
Td
Tr
AD31:0
ADDR
MA11:0
ROW
COL
COL
COL
COL
ALE
ADS#
BE3:0#
W/R#
BLAST#
DT/R#
MWE0#
DWE0#
RAS0#
CAS3:0# LRDYRCV# RDYRCV#
50
Preliminary Datasheet
80960VH
Figure 18. FPM DRAM System Read Access, Interleaved, 2,0,0,0 Wait States
TA P_CLK TW TW TD TD TD TD TR
AD[31:0]
ADDR
D IN
D IN
D IN
D IN
RAS[n]# RAS[n+1#] COL
MA[11:0]
ROW
COL
DALE[0]#
CAS[3:0]#
LEAF[0]#
DALE[1]#
CAS[7:4]#
LEAF[1]#
DWE[1:0]#
Preliminary Datasheet
51
80960VH
Figure 19. FPM DRAM System Write Access, Interleaved, 1,0,0,0 Wait States
TA P_CLK
TW
TD
TD
TD
TD
TR
TR
AD[31:0]
ADDR
DATA OUT
DATA OUT
DATA OUT
DATA OUT
RAS[n]# RAS[n+1]#
MA[11:0]
ROW
COL
COL
DALE[0]#
CAS[3:0]#
LEAF[0]#
DALE[1]#
CAS[7:4]#
LEAF[1]#
DWE[1:0]#
52
Preliminary Datasheet
80960VH
Figure 20. EDO DRAM, Read Cycle
TA P_CLK TW TW TD TD TD TD TR
RAS#
MA[11:0]
ROW
COL
COL
COL
COL
CAS#
AD[31:0]
ADDR
D IN
D IN
D IN
D IN
Figure 21. EDO DRAM, Write Cycle
TA P_CLK TW TD TD TD TD TR
RAS#
MA[11:0]
ROW
COL
COL
COL
COL
CAS#
AD[31:0]
ADDR
D OUT
D OUT
D OUT
D OUT
Preliminary Datasheet
53
80960VH
Figure 22. 32-Bit Bus, SRAM Read Accesses with 0 Wait States
TA P_CLK TD TD TD TD TR
CE[1]#
MA[11:0]
ADDR
ADDR ADDR ADDR
MWE[3:0]#
AD[31:0]
ADDR
D IN
D IN
D IN
D IN
Figure 23. 32-Bit Bus, SRAM Write Accesses with 0 Wait States
TA P_CLK TD TD TD TD TR
CE[1]#
MA[11:0]
ADDR
ADDR ADDR ADDR
MWE[3:0]#
AD[31:0]
ADDR
D OUT
D OUT
D OUT
D OUT
54
Preliminary Datasheet
80960VH
5.0
Bus Functional Waveforms
Figure 24. Non-Burst Read and Write Transactions without Wait States, 32-Bit 80960 Local Bus
TA P_CLK
TD
TR
TI
TI
TA
TD
TR
TI
TI
AD31:0
ADDR
D In
Invalid
ADDR
D In
DATA Out
ALE
ADS#
BE3:0#
WIDTH1:0
10
10
D/C#
W/R#
BLAST#
DT/R#
DEN#
LRDYRCV# RDYRCV#
Preliminary Datasheet
55
80960VH
Figure 25. Burst Read and Write Transactions without Wait States, 32-Bit 80960 Local Bus
TA P_CLK TD TD TR TA TD TD TD TD TR
AD31:0
ADDR
D In
D In
ADDR
DATA Out
DATA Out
DATA Out
DATA Out
ALE
ADS#
BE3:0#
WIDTH1:0
10
10
D/C#
W/R#
BLAST#
DT/R#
DEN#
LRDYRCV# RDYRCV#
56
Preliminary Datasheet
80960VH
Figure 26. Burst Write Transactions with 2,1,1,1 Wait States, 32-Bit 80960 Local Bus
TA P_CLK TW TW TD TW TD TW TD TW TD TR
AD31:0
ADDR
DATA Out
DATA Out
DATA Out
DATA Out
ALE
ADS#
BE3:0#
WIDTH1:0
10
D/C#
W/R#
BLAST#
DT/R#
DEN#
LRDYRCV# RDYRCV#
Preliminary Datasheet
57
80960VH
Figure 27. Burst Read and Write Transactions without Wait States, 8-Bit 80960 Local Bus
TA P_CLK
TD
TD
TR
TA
TD
TD
TD
TD
TR
AD31:0
ADDR
D In
D In
ADDR
DATA Out
DATA Out
DATA Out
DATA Out
ALE
ADS#
BE1/A1# BE0/A0#
00 or 10
01 or 11
00
01
10
11
WIDTH1:0
00
00
D/C#
W/R#
BLAST#
DT/R#
DEN#
LRDYRCV# RDYRCV#
58
Preliminary Datasheet
80960VH
Figure 28. Burst Read and Write Transactions with 1, 0 Wait States and Extra Tr State on Read, 16-Bit 80960 Local Bus
TA P_CLK TW TD TD TR TR TA TW TD TD TR
AD31:0
ADDR
D In
D In
ADDR
DATA Out
DATA Out
ALE
ADS#
BE1/A1#
0
1
0
1
BE3# BE0#
WIDTH1:0
01
01
D/C#
W/R#
BLAST#
DT/R#
DEN#
LRDYRCV# RDYRCV#
Preliminary Datasheet
59
80960VH
Figure 29. Bus Transactions Generated by Double Word Read Bus Request, Misaligned One Byte From Quad Word Boundary, 32-Bit 80960 Local Bus
TA P_CLK TD TR TA TD TR TA TD TR TA TD TR
AD31:0
A
D In
A
D In
A
D In
A
D In
ALE
ADS#
BE3:0#
1101
0011
0000
1110
WIDTH1:0
10
D/C#
Valid
W/R#
BLAST#
DT/R#
DEN#
LRDYRCV# RDYRCV#
60
Preliminary Datasheet
80960VH
Figure 30. HOLD/HOLDA Waveform For Bus Arbitration
TI or TR TH TH TI or TA
P_CLK
Outputs: AD31:0, ALE, ADS#, BE3:0# D/C#/RSTMODE# LRDYRCV#, FAIL# WIDTH/HLTD1, WIDTH/HLTD1/RETRY, W/R#, DT/R#, DEN#, BLAST#, LOCK#/ONCE#
Valid
Valid
HOLD
HOLDA
(Note)
NOTE: HOLD is sampled on the rising edge of P_CLK. HOLDA is granted after the latency counter in the local bus arbiter expires. The processor asserts HOLDA to grant the bus on the same edge in which it recognizes HOLD if the last state was Ti or the last Tr of a bus transaction. Similarly, the processor deasserts HOLDA on the same edge in which it recognizes the deassertion of HOLD.
Preliminary Datasheet
61

P_CLK VCC ADS#, BE3:0# BLAST#, DEN# LRDYRCV

LOCK#/ ONCE# STEST
Valid (Input)
Valid 1 ms power and clock stable V and P_CLK stable to P_RST# High, minimum CC 100 s for PLL stabilization.
Built-in self test approximately 414,000 P_CLK periods (if selected)

D/C#/RST_MODE#, WIDTH/HLTD0, WIDTH/HLTD1/RETRY

P_RST#
(Output)

AD31:0
Idle (Note 2)

FAIL#

ALE, DT/R#, HOLD, HOLDA, W/R#

62 Preliminary Datasheet
2. If the processor fails built-in self-test, it initiates one dummy load bus access. The load address indicates the point of self-test failure.
80960VH
Figure 31. 80960 Core Cold Reset Waveform
(Note 1)
First Bus Activity
Notes: 1. The processor asserts FAIL# during built-in self-test. If self- test passes, the FAIL# is deasserted.The processor also asserts FAIL# during the bus confidence test. If the bus confidence test passes, FAIL# is deasserted and the processor begins user program execution.
ADS#, BE3:0#,DEN#, BLAST#, D/C#/RST_MODE#, WIDTH/HLTD0, WIDTH/HLTD1/RETRY,LRDYRCV#

FAIL# AD31:0 HOLD
Figure 32. 80960 Local Bus Warm Reset Waveform
LOCK#/ONCE# STEST P_RST# Maximum L_RST# Low to Reset State 4 P_CLK Cycles L_RST#

Minimum L_RST# Low Time 16 P_CLK Cycles NOTE: Local bus warm reset occurs when Bit 5 in the Reset/Retry Control Register (RRCR) is set; L_RST# asserts when all ATU and/or DMA activity ceases on the PCI buses. L_RST# asserts in a minimum of 18 clock cycles after RRCR bit 5 is set.
L_RST# High to First Bus Activity, 46 P_CLK Cycles

Valid

HOLDA

ALE, W/R#,DT/R#

Preliminary Datasheet
P_CLK
80960VH
63
80960VH
6.0
Device Identification On Reset
During the manufacturing process, values characterizing the i960(R) VH processor type and stepping are programmed into the memory-mapped registers. The 80960VH contains two read-only device ID MMRs. One holds the Processor Device ID (PDIDR - 0000 1710H) and the other holds the i960 Core Processor Device ID (DEVICEID - FF00 8710H). During initialization, the PDIDR is placed in g0. The device identification values are compliant with the IEEE 1149.1 specification and Intel standards. Table 30 describes the fields of the two Device IDs.
Table 30. Processor Device ID Register - PDIDR
31 LBA 28 24 20 16 12 8 4 0 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro
PCI
na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na
LBA: PCI: Bit 31:28 27 26:21 20:17 16:12 11:01 0
1710H NA Default X X X X X X X
Legend:NA = Not AccessibleRO = Read Only RV = ReservedPR = PreservedRW = Read/Write RS = Read/SetRC = Read Clear LBA = 80960 Local Bus Address PCI = PCI Configuration Address Offset Description Version - Indicates stepping changes. VCC - Indicates device voltage type. 0 = 5.0 V 1 = 3.3 V Product Type - Indicates the generation or "family member". Generation Type - Indicates the generation of the device. Model Type - Indicates member within a series and specific model information. Manufacturer ID - Indicates manufacturer ID assigned by IEEE. 0000 0001 001 = Intel Corporation Constant
NOTE: Values programmed into this register vary with stepping. Refer to the i960(R) VH processor Specification Update (273174-001) for the correct value.
64
Preliminary Datasheet

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