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QPRO Family of XC1700D QML Configuration PROMs
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DS070 (v2.1) June 1, 2000
Product Specification
Features
* * * Certified to MIL-PRF-38535 Appendix A QML (Qualified Manufacturer Listing.) Also available under the following Standard Microcircuit Drawings (SMD): 5962-94717 and 5962-95617. Configuration one-time programmable (OTP) read-only memory designed to store configuration bitstreams of Xilinx FPGA devices On-chip address counter, incremented by each rising edge on the clock input Simple interface to the FPGA requires only one user I/O pin Cascadable for storing longer or multiple bitstreams Programmable reset polarity (active High or active Low) for compatibility with different FPGA solutions Low-power CMOS EPROM process Available in 5V version only Programming support by leading programmer manufacturers. Design support using the Xilinx Alliance and Foundation series software packages.
Description
The XC1700D QPROTM family of configuration PROMs provide an easy-to-use, cost-effective method for storing Xilinx FPGA configuration bitstreams. When the FPGA is in Master Serial mode, it generates a configuration clock that drives the PROM. A short access time after the rising clock edge, data appears on the PROM DATA output pin that is connected to the FPGA D IN pin. The FPGA generates the appropriate number of clock pulses to complete the configuration. Once configured, it disables the PROM. When the FPGA is in Slave Serial mode, the PROM and the FPGA must both be clocked by an incoming signal. Multiple devices can be concatenated by using the CEO output to drive the CE input of the following device. The clock inputs and the DATA outputs of all PROMs in this chain are interconnected. All devices are compatible and can be cascaded with other members of the family. For device programming, either the Xilinx AllianceTM or the FoundationTM series development systems compiles the FPGA design file into a standard HEX format which is then transferred to most commercial PROM programmers.
* * * * * * * *
VCC
VPP
GND
RESET/ OE or OE/ RESET
CE
CEO
CLK
Address Counter
TC
EPROM Cell Matrix
Output
OE DATA
DS027_01_021500
Figure 1: Simplified Block Diagram (does not show programming circuit)
(c) 2000 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS070 (v2.1) June 1, 2000 Product Specification
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QPRO Family of XC1700D QML Configuration PROMs
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Pin Description
DATA
Data output, 3-stated when either CE or OE are inactive. During programming, the DATA pin is I/O. Note that OE can be programmed to be either active High or active Low.
ation, this pin must be connected to VCC. Failure to do so may lead to unpredictable, temperature-dependent operation and severe problems in circuit debugging. Do not leave VPP floating!
VCC and GND
VCC is positive supply pin and GND is ground pin.
CLK
Each rising edge on the CLK input increments the internal address counter, if both CE and OE are active.
PROM Pinouts
Pin Name DATA CLK RESET/OE (OE/RESET) CE GND CEO VPP VCC 8-pin 1 2 3 4 5 6 7 8
RESET/OE
When High, this input holds the address counter reset and 3-states the DATA output. The polarity of this input pin is programmable as either RESET/OE or OE/RESET. To avoid confusion, this document describes the pin as RESET/OE, although the opposite polarity is possible on all devices. When RESET is active, the address counter is held at zero, and the DATA output is put in a high-impedance state. The polarity of this input is programmable. The default is active High RESET, but the preferred option is active Low RESET, because it can be driven by the FPGAs INIT pin. The polarity of this pin is controlled in the programmer interface. This input pin is easily inverted using the Xilinx HW-130 programmer software. Third-party programmers have different methods to invert this pin.
Capacity
Device XC1736D XC1765D XC17128D XC17256D Configuration Bits 36,288 65,536 131,072 262,144
CE
When High, this pin disables the internal address counter, 3-states the DATA output, and forces the device into low-ICC standby mode.
CEO
Chip Enable output, to be connected to the CE input of the next PROM in the daisy chain. This output is Low when the CE and OE inputs are both active AND the internal address counter has been incremented beyond its Terminal Count (TC) value. In other words: when the PROM has been read, CEO will follow CE as long as OE is active. When OE goes inactive, CEO stays High until the PROM is reset. Note that OE can be programmed to be either active High or active Low.
Number of Configuration Bits, Including Header for Xilinx FPGAs and Compatible PROMs
Device XC3000/A series XC4000 series XQ4005E XQ4010E XQ4013E Configuration Bits 14,819 to 94,984 95,008 to 247,968 95,008 178,144 247,968 PROM XC1765D to XC17128D XC17128D to XC17256D XC17128D XC17256D XC17256D
VPP
Programming voltage. No overshoot above the specified max voltage is permitted on this pin. For normal read oper-
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DS070 (v2.1) June 1, 2000 Product Specification
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QPRO Family of XC1700D QML Configuration PROMs read sequentially, accessed via the internal address and bit counters which are incremented on every valid rising edge of CCLK. If the user-programmable, dual-function DIN pin on the FPGA is used only for configuration, it must still be held at a defined level during normal operation. Xilinx FPGAs take care of this automatically with an on-chip default pull-up resistor.
Controlling PROMs
Connecting the FPGA device with the PROM. * * * * The DATA output(s) of the PROM(s) drives the DIN input of the lead FPGA device. The Master FPGA CCLK output drives the CLK input(s) of the PROM(s). The CEO output of a PROM drives the CE input of the next PROM in a daisy chain (if any). The RESET/OE input of all PROMs is best driven by the INIT output of the lead FPGA device. This connection assures that the PROM address counter is reset before the start of any (re)configuration, even when a reconfiguration is initiated by a VCC glitch. Other methods--such as driving RESET/OE from LDC or system reset--assume the PROM internal power-on-reset is always in step with the FPGA's internal power-on-reset. This may not be a safe assumption. The PROM CE input can be driven from either the LDC or DONE pins. Using LDC avoids potential contention on the DIN pin. The CE input of the lead (or only) PROM is driven by the DONE output of the lead FPGA device, provided that DONE is not permanently grounded. Otherwise, LDC can be used to drive CE, but must then be unconditionally High during user operation. CE can also be permanently tied Low, but this keeps the DATA output active and causes an unnecessary supply current of 10 mA maximum.
Programming the FPGA With Counters Unchanged Upon Completion
When multiple FPGA-configurations for a single FPGA are stored in a PROM, the OE pin should be tied Low. Upon power-up, the internal address counters are reset and configuration begins with the first program stored in memory. Since the OE pin is held Low, the address counters are left unchanged after configuration is complete. Therefore, to reprogram the FPGA with another program, the DONE line is pulled Low and configuration begins at the last value of the address counters. This method fails if a user applies RESET during the FPGA configuration process. The FPGA aborts the configuration and then restarts a new configuration, as intended, but the PROM does not reset its address counter, since it never saw a High level on its OE input. The new configuration, therefore, reads the remaining data in the PROM and interprets it as preamble, length count etc. Since the FPGA is the master, it issues the necessary number of CCLK pulses, up to 16 million (224) and DONE goes High. However, the FPGA configuration will be completely wrong, with potential contentions inside the FPGA and on its output pins. This method must, therefore, never be used when there is any chance of external reset during configuration.
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*
FPGA Master Serial Mode Summary
The I/O and logic functions of the Configurable Logic Block (CLB) and their associated interconnections are established by a configuration program. The program is loaded either automatically upon power up, or on command, depending on the state of the three FPGA mode pins. In Master Serial mode, the FPGA automatically loads the configuration program from an external memory. The Xilinx PROMs have been designed for compatibility with the Master Serial mode. Upon power-up or reconfiguration, an FPGA enters the Master Serial mode whenever all three of the FPGA mode-select pins are Low (M0=0, M1=0, M2=0). Data is read from the PROM sequentially on a single data line. Synchronization is provided by the rising edge of the temporary signal CCLK, which is generated during configuration. Master Serial Mode provides a simple configuration interface. Only a serial data line and two control lines are required to configure an FPGA. Data from the PROM is
Cascading Configuration PROMs
For multiple FPGAs configured as a daisy-chain, or for future FPGAs requiring larger configuration memories, cascaded PROMs provide additional memory. After the last bit from the first PROM is read, the next clock signal to the PROM asserts its CEO output Low and disables its DATA line. The second PROM recognizes the Low level on its CE input and enables its DATA output. See Figure 2. After configuration is complete, the address counters of all cascaded PROMs are reset if the FPGA RESET pin goes Low, assuming the PROM reset polarity option has been inverted. To reprogram the FPGA with another program, the DONE line goes Low and configuration begins where the address counters had stopped. In this case, avoid contention between DATA and the configured I/O use of DIN.
DS070 (v2.1) June 1, 2000 Product Specification
www.xilinx.com 1-800-255-7778
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QPRO Family of XC1700D QML Configuration PROMs
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Vcc
DOUT
OPTIONAL Daisy-chained FPGAs with Different configurations OPTIONAL Slave FPGAs with Identical Configurations VCC
FPGA
MODES*
3.3V 4.7K
VPP VCC DATA CLK CE OE/RESET VPP DATA
DIN RESET RESET CCLK DONE INIT
* For mode pin connections, refer to the appropriate FPGA data sheet.
PROM
CEO
CLK CE
Cascaded Serial Memory
OE/RESET
(Low Resets the Address Pointer) CCLK (Output)
DIN
DOUT (Output)
DS027_02_052200
Figure 2: Master Serial Mode. The one-time-programmable PROM supports automatic loading of configuration programs. Multiple devices can be cascaded to support additional FPGAs. An early DONE inhibits the PROM data output one CCLK cycle before the FPGA I/Os become active.
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DS070 (v2.1) June 1, 2000 Product Specification
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QPRO Family of XC1700D QML Configuration PROMs
Standby Mode
The PROM enters a low-power standby mode whenever CE is asserted High. The output remains in a high impedance state regardless of the state of the OE input.
Programming
The devices can be programmed on programmers supplied by Xilinx or qualified third-party vendors. The user must ensure that the appropriate programming algorithm and the latest version of the programmer software are used. The wrong choice can permanently damage the device.
Table 1: Truth Table for XC1700 Control Inputs Control Inputs RESET Inactive Active Inactive Active CE Low Low High High Internal Address If address < TC: increment If address > TC: don't change Held reset Not changing Held reset DATA Active High-Z High-Z High-Z High-Z Outputs CEO High Low High High High ICC Active reduced Active Standby Standby
Notes: 1. The XC1700 RESET input has programmable polarity 2. TC = Terminal Count = highest address value. TC + 1 = address 0.
Important: Always tie the VPP pin to VCC in your application. Never leave VPP floating.
DS070 (v2.1) June 1, 2000 Product Specification
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QPRO Family of XC1700D QML Configuration PROMs
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XC1736D, XC1765D, XC17128D and XC17256D Absolute Maximum Ratings
Symbol VCC VPP VIN VTS TSTG TSOL Description Supply voltage relative to GND Supply voltage relative to GND Input voltage relative to GND Voltage applied to High-Z output Storage temperature (ambient) Maximum soldering temperature (10s @ 1/16 in.) -0.5 to +7.0 -0.5 to +12.5 -0.5 to VCC + 0.5 -0.5 to VCC + 0.5 -65 to +150 +260 Units V V V V C C
Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.
Operating Conditions
Symbol VCC Description Supply voltage relative to GND (TC = -55C to +125C) Military Min 4.50 Max 5.50 Units V
Note: During normal read operation VPP must be connected to VCC
DC Characteristics Over Operating Condition
Symbol VIH VIL VOH VOL ICCA ICCS High-level input voltage Low-level input voltage High-level output voltage (IOH = -4 mA) Low-level output voltage (IOL = +4 mA) Supply current, active mode (at maximum frequency) Supply current, standby mode XC17128D, XC17256D XC1736D, XC1765D IL CIN COUT Input or output leakage current Input capacitance (VIN = GND, f = 1.0 MHz) sample tested Output capacitance (VIN = GND, f = 1.0 MHz) sample tested Military Description Min 2.0 0 3.7 -10 Max VCC 0.8 0.4 10 50 1.5 10 10 10 Units V V V V mA A mA A pF pF
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DS070 (v2.1) June 1, 2000 Product Specification
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QPRO Family of XC1700D QML Configuration PROMs
AC Characteristics Over Operating Condition(1,2)
CE
TSCE TSCE THCE
RESET/OE
TLC THC THOE TCYC
CLK
TOE TCE TCAC TOH TDF
DATA
TOH
DS027_03_021500
XC1736D XC1765D Symbol TOE TCE TCAC TOH TDF TCYC TLC THC TSCE THCE THOE OE to data delay CE to data delay CLK to data delay Data hold from CE, OE, or CLK(3) CE or OE to data float delay(3,4) Clock periods CLK Low time(3) CLK High time(3) CE setup time to CLK (to guarantee proper counting) CE hold time to CLK (to guarantee proper counting) OE hold time (guarantees counters are reset) Description Min 0 200 100 100 25 0 100 Max 45 60 150 50 -
XC17128D XC17256D Min 0 80 20 20 20 0 20 Max 25 45 50 50 Units ns ns ns ns ns ns ns ns ns ns ns
Notes: 1. AC test load = 50 pF 2. All AC parameters are measured with VIL = 0.0V and VIH = 3.0V. 3. Guaranteed by design, not tested. 4. Float delays are measured with 5 pF AC loads. Transition is measured at 200mV from steady state active levels.
DS070 (v2.1) June 1, 2000 Product Specification
www.xilinx.com 1-800-255-7778
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QPRO Family of XC1700D QML Configuration PROMs
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AC Characteristics Over Operating Condition When Cascading(1,2)
RESET/OE
CE
CLK TCDF DATA Last Bit TOCK CEO TOCE TOCE
DS027_04_021500
First Bit TOOE
XC1736D XC1765D Symbol TCDF TOCK TOCE TOOE Description CLK to data float delay(3,4) CLK to CEO delay(3) CE to CEO delay(3) RESET/OE to CEO delay(3) Min Max 50 65 45 40
XC17128D XC17256D Min Max 50 30 35 30 Units ns ns ns ns
Notes: 1. AC test load = 50 pF 2. All AC parameters are measured with VIL = 0.0V and VIH = 3.0V. 3. Guaranteed by design, not tested. 4. Float delays are measured with 5 pF AC loads. Transition is measured at 200mV from steady state active levels.
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DS070 (v2.1) June 1, 2000 Product Specification
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QPRO Family of XC1700D QML Configuration PROMs
Ordering Information
XC17256D DD8 M
Device Number XC1736D XC1765D XC17128D XC17256D Package Type DD8 = 8-pin Ceramic DIP Operating Range/Processing M = Military (TC = -55 to +125C) B = Military (TC = -55 to +125C) QML certified to MIL-PRF-38535
Valid Ordering Combinations
XC17128DDD8M XC17256DDD8M 5962-9561701MPA XC1736DDD8M XC1765DDD8M 5962-9471701MPA
Marking Information
Due to the small size of the PROM package, the complete ordering part number cannot be marked on the package. The XC prefix is deleted and the package code is simplified. Device marking is as follows.
17256D DD8 M
Device Number XC1736D XC1765D XC17128D XC17256D Package Type DD8 = 8-pin Ceramic DIP Operating Range/Processing M = Military (TC = -55 to +125C) B = Military (TC = -55 to +125C) QML certified to MIL-PRF-38535
Revision History
The following table shows the revision history for this document Date 02/08/99 06/01/00 Version 2.0 2.1 Revision Removed the now obsolete Commercial and Industrial Grade part numbers and design support. Updated format and assigned data sheet number (DS070).
DS070 (v2.1) June 1, 2000 Product Specification
www.xilinx.com 1-800-255-7778
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QPRO Family of XC1700D QML Configuration PROMs
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DS070 (v2.1) June 1, 2000 Product Specification

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