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Semiconductor MSM9841
Recording and Playback IC with Built-in FIFO
Contents
GENERAL DESCRIPTION ........................................................................................ 1 FEATURES ................................................................................................................ 1 BLOCK DIAGRAM .................................................................................................... 2 PIN CONFIGURATION (TOP VIEW) ......................................................................... 3 PIN DESCRIPTIONS ................................................................................................. 4 ABSOLUTE MAXIMUM RATINGS ........................................................................... 6 RECOMMENDED OPERATING CONDITIONS ....................................................... 6 ELECTRICAL CHARACTERISTICS ......................................................................... 6 DC Characteristics ............................................................................................................ 6 Analog Characteristics ..................................................................................................... 7 AC Characteristics ............................................................................................................ 8 TIMING DIAGRAMS ................................................................................................. 9 Reset Timing ..................................................................................................................... 9 Read Timing ....................................................................................................................10 Write Timing ...................................................................................................................11 DMA Transfer Timing ................................................................................................... 12 Recording Timing (When FIFO memory is used) ..................................................... 13 Recording Timing (When FIFO memory is not used) .............................................. 14 Monophonic Playback Timing (When FIFO memory is used) ............................... 15 Monophonic Playback Timing (When FIFO memory is not used)......................... 16 Stereophonic Playback Timing (When FIFO memory is used) ............................... 17 Stereophonic Playback Timing (When FIFO memory is not used) ........................ 18
FUNCTIONAL DESCRIPTION ................................................................................ 19 Voice synthesis method ................................................................................................. 19 Voice synthesis methods and sampling frequencies during recording and playback ...... 19 Data configuration for each voice synthesis method .................................................... 20 Data configuration when 8-bit bus is used ................................................................. 20 Data configuration when 16-bit bus is used ............................................................... 21 FIFO memory configuration ......................................................................................... 22 Recording Data Transfer Flowchart (without DMA transfer) ................................ 25 Playback Data Transfer Flowchart (without DMA transfer) ................................... 26 DMA Control Method ................................................................................................... 27 Recording Data Transfer Flowchart (with DMA transfer in Block mode) ............ 28 Recording Data Transfer Flowchart (with DMA transfer in Single mode) ........... 29 Playback Data Transfer Flowchart (with DMA transfer in Block mode) .............. 30 Playback Data Transfer Flowchart (with DMA transfer in Single mode) ............. 31 Recording time and memory capacity ........................................................................ 32 Connection of power supply ........................................................................................ 32 Analog Input Amplifier Circuit ................................................................................... 33 The process of SG pin .................................................................................................... 34 Frequency characteristics of the input side LPF ........................................................ 35 Frequency characteristics of the output side LPF ..................................................... 36 Using External DAC ...................................................................................................... 37 Using External ADC ...................................................................................................... 37 COMMANDS LIST .................................................................................................. 38 Description of commands ............................................................................................. 40 Description of status ...................................................................................................... 46 CPU INTERFACE EXAMPLES ............................................................................... 47 PACKAGE DIMENSIONS ....................................................................................... 48
E2D1029-39-61 Semiconductor
Semiconductor MSM9841
Recording and Playback LSI with Built-in FIFO
im i This version: Jun. 1999 MSM9841 na ry Previous version: Mar. 1999
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GENERAL DESCRIPTION
The MSM9841 is a mono/stereo record and playback LSI with a built-in 1K bit FIFO for easy interface with external systems or non-semiconductor memory. It utilizes multiple record and playback modes, including the new ADPCM2 algorithm, which allows for even higher quality sound reproduction. The record and playback functions of the MSM9841 is controlled by an MCU via 8/16-bit bus interface.
FEATURES
* 16/8-bit bus interface support * FIFO capacity: User-definable (256/512/1024 bits) (buffering time of 32 ms when using 8 kHz sampling frequency, 4-bit ADPCM2/ADPCM, and in monaural playback) * Supports four compression algorithms for record and playback: 4, 5, 6, 7, 8-bit ADPCM2; 4-bit ADPCM; 8; 16-bit PCM; and 8-bit Nonlinear PCM * Sampling frequency: 4.0 kHz, 6.4 kHz, 8.0 kHz, 12.8 kHz, 16.0 kHz, 32.0 kHz* (fosc=4.096 MHz) * Sampling frequency: 22.05 kHz*, 44.1 kHz* (fosc=5.6448 MHz) * For the built-in ADC, set the sampling frequency at 16 kHz or less. * DMA interface support * Volume control (8 steps: 0 dB to -21 dB) * Built-in 14-bit A/D converter * Built-in 14-bit D/A converter * Built-in low pass filter (LPF) : (input side: analog LPF) : (output side: digital LPF) * Power supply voltage: 2.7 V to 5.5 V * Package: 56-pin plastic QFP (QFP56-P-910-0.65-2K) (Product name: MSM9841GS-2K) *note 32 kHz, 22.05 kHz and 44.1 kHz are available only for playback.
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Semiconductor
MSM9841
BLOCK DIAGRAM
MOUT LOUT AOUTL AOUTR SG AVDD AGND DVDD DGND
MIN
input side
LPF LIN
ADC
output side
LPF
DAC
DAC
output side
LPF
Volume Controller EMP MID FUL/DREQR CH/DACKR FIFO ADSD DASD SIOCK
ADPCM2/ADPCM/PCM Analyzer ADPCM2/ADPCM/PCM/Non-linear PCM Synthesizer
D15 to D0 WR RD CS D/C BUSY
MCU I/F DMA I/F Timing Controller TEST0 TEST1
DREQL DACKL IOW
IOR
VCK XT XT
RESET
External DAC/ADC I/F
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MSM9841
PIN CONFIGURATION (TOP VIEW)
51 DREQL
50 DACKL
43 SIOCK
42 BUSY 41 D/C 40 CS 39 RD 38 WR 37 FUL/DREQR 36 MID 35 EMP 34 CH/DACKR 33 RESET 32 NC 31 DVDD 30 AVDD 29 AOUTR
48 TEST1
47 TEST0
49 DGND
45 ADSD LOUT 26
D0 D1 D2 D3 NC D4 D5 D6 D7
1 2 3 4 5 6 7 8 9
NC 10 D8 11 D9 12 D10 13 D11 14
NC 15
D12 16
D13 17
D14 18
D15 19
NC 20
DGND 21
AGND 22
MIN 23
MOUT 24
LIN 25
SG 27
44 DASD
52 IOW
46 VCK
53 IOR
56 NC
55 XT
54 XT
NC : No Connection 56-pin plastic QFP
AOUTL 28
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Semiconductor
MSM9841
PIN DESCRIPTIONS
Symbol Type Description For 8-bit bus interface, the command allows these pins to be configured to be inputs or outputs to input or output data to and from an external memory. Otherwise, these pins are configured D15-D8 I/O to be inputs only. For 16-bit interface, these pins are a bidirectional data bus to input or output data to and from an external microcontroller and memory. D7-D0 WR RD CS D/C BUSY EMP I/O I I I I O O Birirectional data bus to input or output data and output status to and from an external microcontroller and memory. Write pulse input pin. This pin pulses "L" when command or voice data is input to D15-D0 pins. Read pulse input pin. This pin pulses "L" when status or voice data is output to D15-D0 pins. Accepts write pulse and read pulse when this pin is "L". Does not accept write pulse and read pulse when this pin is "H". Voice data is input or output to and from D15-D0 pins when this pin is "H". Command is input to and status is output from D7-D0 pins when this pin is "L". This pin outputs a "L" level during RECORDING, PLAYBACK or PAUSE. "H" level indicates that there is no data in FIFO memory. Active "H" can be changed to active "L" by command input. "H" level indicates that more than half of the FIFO memory space is filled with data. MID O During playback, voice synthesis starts when MID changes to "H" level. Active "H" can be changed to active "L" by command input. This pin outputs a synchro signal for voice data input/ output when non-use of FIFO is selected. "H" level indicates that FIFO memory is full of data. During playback, this pin is "H" and data FUL/DREQR O cannot be written in FIFO memory. Active "H" can be changed to active "L" by command input. When DMA transfer and stereo playback are selected, "H" level DREQR outputs a signal to request a DMA transfer. Active "H" can be changed to active "L" by command input. When stereo playback is selected and CH is "H", the EMP, MID or FUL pin outputs the status of right FIFO memory. When CH is "L", the EMP, MID or FUL pin outputs the status of left FIFO CH/DACKR I memory. Set this pin to "L" during recording and monophonic playback. When DMA transfer and stereo playback are selected, DACKR is selected. In this case, input a DMA transfer acknowledge signal to DACKR. When DACKR is "L", the IOW signal is accepted. Active "L" can be changed to active "H" by command input. When DMA transfer is selected, "H" level DREQL outputs a signal to request a DMA transfer. DREQL O When stereo playback is selected, "H" level DREQL outputs a signal to request a DMA transfer. Active "H" can be changed to active "L" by command input. Input to DACKL a signal when DMA transfer is permitted by the DMA controller. When DACKL DACKL I is "L", IOR and IOW signals are accepted. When stereo playback is selected, input to DACKL a DMA transfer acknowledge signal for left FIFO memory. Active "L" can be changed to active "H" by command input. If DMA transfer is not used, set this pin to "H" level.
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MSM9841
PIN DESCRIPTIONS
Symbol IOW IOR ADSD DASD SIOCK XT XT VCK RESET TEST0 TEST1 SG MIN LIN MOUT LOUT AOUTL AOUTR DVDD DGND AVDD AGND Type I I I O O I O O I I O I O O O -- -- -- -- Description Write pulse input pin to write external memory data to MSM9841 during DMA transfer. If DMA transfer is not used, set this pin to "H" level. Read pulse input pin to read data of MSM9841 during DMA transfer. If DMA transfer is not used, set this pin to "H" level. 16-bit serial data input pin when external ADC is used. If external ADC is not used, set this pin to "L" level. 16-bit serial data output pin when external DAC is used. Synchronizing clock for 16-bit serial data input/output when external ADC or DAC is used. Oscillator connection pins. When external clock is used, input clock into XT pin and leave XT pin open. Outputs sampling frequency selected at recording or playback. VCK pin is used as a synchronizing signal when external ADC or DAC is used. When this pin is "L" level input, the LSI is initialized. Pins for testing. Set the pins to "L". Analog circuit signal ground output pin. Inverting input pin for built-in OP amplifier. Noninverting input pin is connected to SG (Signal Ground) internally. MOUT is the output of internal OP amplifier to MIN, and LOUT is to LIN. Left analog output pin from built-in LPF. This is the output pin of playback wavefroms, and is connected to the amplifier for driving speakers. Right analog output pin from built-in LPF. This is the output pin of playback wavefroms, and is connected to the amplifier for driving speakers. Digital power supply pin. Insert a minimum 0.1 mF bypass capacitor between this pin and DGND pin. Digital GND pin. Analog power supply pin. Insert a minimum 0.1 mF bypass capacitor between this pin and AGND pin. Analog GND pin.
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MSM9841
ABSOLUTE MAXIMUM RATINGS
Parameter Power Supply Voltage Input Voltage Storage Temperature Symbol VDD VIN TSTG Condition Ta=25C Ta=25C -- Rating -0.3 to +7.0 -0.3 to VDD+0.3 -55 to +155 Unit V V C
RECOMMENDED OPERATING CONDITIONS
Parameter Power Supply Voltage Operating Temperature Master Clock Frequency Symbol VDD TOP fOSC Condition DGND=AGND=0V -- -- Min. 4.0 Range 2.7 to 5.5 -40 to +85 Typ. 4.096 Max. 6.0 Unit V C MHz
ELECTRICAL CHARACTERISTICS
DC Characteristics
DVDD=AVDD=2.7 to 5.5V, DGND=AGND=0V, Ta=-40 to +85C Parameter High-level Input Voltage Low-level Input Voltage High-level output Voltage Low-level output Voltage High-level Input Current (*1) High-level Input Current (*2) High-level Input Current (*3) Low-level Input Current (*1) Low-level Input Current (*2) Symbol VIH VIL VOH VOL IIH1 IIH2 IIH3 IIL1 IIL2 Condition -- -- IOH=-40 mA IOL=2 mA VIH=VDD VIH=VDD DVDD=AVDD=4.5 to 5.5 V, VIH=VDD DVDD=AVDD=2.7 to 3.6 V, VIH=VDD VIL=GND VIL=GND DVDD=AVDD=4.5 to 5.5 V, Operating Current consumption IDD fosc=4.096 MHz, whithout load DVDD=AVDD=2.7 to 3.6 V, fosc=4.096 MHz, whithout load At power down, without load Stanby Current consumption IDDS Ta=-40 to +70C At power down, without load Ta=-40 to +85C Min. VDD0.85 -- VDD-0.3 -- -- -- 30 10 -10 -20 -- -- -- -- Typ. -- -- -- -- -- -- 150 50 -- -- 15 10 -- -- Max. -- VDD0.2 -- 0.45 10 20 300 100 -- -- 30 20 10 50 Unit V V V V mA mA mA mA mA mA mA mA mA mA
*1 Applicable to input pins excluding XT pin. *2 Applicable to XT pin. *3 Applicable to TEST0 pin and TEST1 pin.
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Semiconductor Analog Characteristics
MSM9841
DVDD=AVDD=2.7 to 5.5V, DGND=AGND=0V, Ta=-40 to +85C Parameter D/A Output Relative Error
LOUT Allowable Voltage Range
Symbol VDAE VLOUT Gop RINA ROUTA RAOL RAOR RDAO RSAO
Condition No load DVDD=AVDD=4.5 V to 5.5 V DVDD=AVDD=2.7 V to 3.6 V fIN=0 to 4 kHz -- -- -- -- When DAC output is selected. During standby mode or power down mode
Min. -- 1 0.25VDD 40 1 200 50 50 15 15
Typ. -- -- -- -- -- -- -- -- 25 25
Max. 10 VDD-1 0.75VDD -- -- -- -- -- 35 35
Unit mV V V dB MW kW kW kW kW kW
OP Amplifier Open Loop Gain OP Amplifier Input Impedance OP Amplifier Output Load AOUTL Output Load AOUTR Output Load DAC Output Impedance AOUTL, AOUTR output impedance during standby mode
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Semiconductor AC Characteristics
MSM9841
DVDD=AVDD=2.7 to 5.5V, DGND=AGND=0V, Ta=-40 to +85C Parameter RESET Pulse Width Setup Time after Rise of Power Supply for Fall of RESET Time to Active First RD, WR after Fall of RESET RD Pulse Width CS, D/C, CH Setup and Hold Time for RD Time from Fall of RD till Data and Status Definition Time from Fall of RD till Data Float Time from Rise of RD till Fall of Next RD (1) during status read Time from Rise of RD till Fall of Next RD (2) during data read WR Pulse Width CS, D/C, CH Setup and Hold Time for WR Setup Time of Data, and Command for Rise of WR Setup Time of REC and PLAY Command for Rise of WR Hold Time of Data, and Command for Rise of WR Time from Rise of WR till Fall of Next WR (1) during command write Time from Rise of WR till Fall of Next WR (2) during data write Time from Rise of MID till rise of RD (For synchro timing when FIFO memory is not used) Time from Rise of MID till rise of WR (For synchro timing when FIFO memory is not used) MID pulse width (For synchro timing when FIFO memory is not used) IOR Pulse Width Setup and Hold Time of DACKL/R for IOR Time from Fall of IOR till Data Definition Time from Fall of IOR till Data Float Time from Rise of IOR till Fall of Next IOR IOW Pulse Width Setup and Hold Time of DACKL/R for IOW Setup Time of Data for Rise of IOW Hold Time of Data for Rise of IOW Time from Rise of IOW till Fall of Next IOW Symbol tRSTW tRSTD tRSTS tRR tCR tDRE tDRF tCRC tCRC tWW tCW tDWS tDWS tDWH tCWC tCWC tMR tMW tMM tIORW tDR tIORE tIORF tIORC tIOWW tDW tIOWS tIOWH tIOWC Min. 300 500 200 160 30 -- -- 500 200 160 30 100 tWW+50 10 500 200 2 2 15.6 160 10 -- -- 200 160 10 100 10 200 Typ. -- -- -- -- -- -- 10 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 10 -- -- -- -- -- -- Max. -- -- -- -- -- 120 50 -- -- -- -- -- -- -- -- -- 15 15 125 -- -- 160 50 -- -- -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ms ms ns ns ns ns ns ns ns ns ns ns
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Semiconductor
MSM9841
TIMING DIAGRAMS
Reset Timing
VDD
tRSTD tRSTW
RESET (I) tRSTS RD, WR(I)
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Semiconductor Read Timing
D15 to D8 (I/O)
,, , , ,,
1. Data Read Timing
CH (I) CS (I) D/C (I) tCR tCR RD (I) tRR tDRE tDRF D7 to D0 (I/O)
MSM9841
2. Status Read Timing
CS (I)
D/C (I)
tCR
tCR
RD (I)
tRR
tDRE
tDRF
D7 to D0 (I/O)
don't care
3. Read Cycle Timing
tCRC
RD (I)
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Semiconductor Write Timing
,, , , , ,,
1. Data Write Timing
CH (I) CS (I) D/C (I) tCW tCW WR (I) tWW tDWS tDWH D7 to D0 (I/O) D15 to D8 (I/O)
MSM9841
2. Command Write Timing
CS (I)
D/C (I)
tCW
tCW
WR (I)
tWW
tDWS
tDWH
D7 to D0 (I/O)
don't care
3. Write Cycle Timing
tCWC
WR (I)
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Semiconductor DMA Transfer Timing
MSM9841
1. IOR (during recording and 2-byte reading)
DACKL (I) or DACKR
IOR (I)
D7 to D0 (I/O) D15 to D8 (I/O)
2. IOW (during playback and 2-byte writing)
DACKL (I) or DACKR
IOW (I)
D7 to D0 (I/O) D15 to D8 (I/O)

tDR tDR tDR tIORC tDR tIORW tIORE tIORF
tDW tDW tDW tIOWC tDW tIOWW tIOWS tIOWH
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Semiconductor
Recording Timing (When FIFO memory is used)
RESET (I)
WR (I)
RD (I)
D15 to D0 (I/O) Condition setting command D/C (I) Recording command ADPCM/PCM data output Status output ADPCM/PCM data output Stop command
CH/DACKR (I)
MID (O)
FUL/DREQR (O)
EMP (O)
Note 1) 16-bit PCM recording is impossible when 8-bit Bus is selected. 8-bit PCM recording and 8-bit OKI non-linear PCM recording are impossible when 16-bit Bus is selected. Note 2) Enter a condition setting command for every item to be set. Note 3) When you selected 64 words FIFO, you need to transfer 32 words during one sampling clock after FUL and DREQR go "H" level.
MSM9841
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Semiconductor
Recording Timing (When FIFO memory is not used)
RESET (I)
WR (I) tMR RD (I)
D15 to D0 (I/O) Condition setting command D/C (I) Recording command ADPCM/PCM data output Stop command
CH/DACKR (I) tMM MID (O)
FUL/DREQR (O)
EMP (O)
MSM9841
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Note) Enter a condition setting command for every item to be set.
Semiconductor
Monaural Playback Timing (When FIFO memory is used)
RESET (I)
WR (I)
RD (I)
D15 to D0 (I/O) Condition setting command D/C (I) Playback command ADPCM/PCM data input Status output ADPCM/PCM data input Stop command
CH/DACKR (I)
MID (O)
FUL/DREQR (O)
EMP (O)
MSM9841
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Note) Enter a condition setting command for every item to be set.
Semiconductor
Monaural Playback Timing (When FIFO is not used)
RESET (I) tMW WR (I)
D15 to D0 (I/O) Condition setting command D/C (I) Playback command ADPCM/PCM data input Stop command
CH/DACKR (I) tMM MID (O)
FUL/DREQR (O)
EMP (O)
BUSY (O)
MSM9841
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Note) Enter a condition setting command for every item to be set.
Semiconductor
Stereo Playback Timing (When FIFO memory is used)
RESET (I)
WR (I)
RD (I)
D15 to D0 (I/O) Condition setting command Playback command ADPCM/PCM input ADPCM/PCM input D/C (I)
Left side Right side Left side Right side Left side Right side Left side Right side ADPCM/ ADPCM/ status status ADPCM/ ADPCM/ PCM input PCM input output output PCM input PCM input
Stop command
CH/DACKR (I)
Left side Right side Left side Right side Left side Right side
MID (O)
FUL/DREQR (O)
EMP (O)
BUSY (O)
MSM9841
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Note) Enter a condition setting command for every item to be set.
Semiconductor
Stereo Playback Timing (When FIFO memory is not used)
RESET (I) tMW WR (I)
RD (I)
D15 to D0 (I/O) Condition setting command Playback command D/C (I)
Left side Right side Left side Right side ADPCM/ ADPCM/ ADPCM/ ADPCM/ PCM input PCM input PCM input PCM input Left side Right side Left side Right side status status ADPCM/ ADPCM/ output output PCM input PCM input
Stop command
CH/DACKR (I)
VCK (O) tMM MID (O)
FUL (O)
EMP (O)
MSM9841
BUSY (O)
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Note) Enter a condition setting command for every item to be set.
Semiconductor
MSM9841
FUNCTIONAL DESCRIPTION
Voice synthesis method The MSM9841 supports four PCM methods to process various kinds of voices :4-bit ADPCM; 4-, 5-, 6-, 7-, or 8-bit ADPCM2; 8- or 16-bit straight PCM; and 8-bit non-linear PCM methods. 1. 4-bit ADPCM method (Adaptive Differential Pulse Code Modulation) This method encodes 4-bit data while adaptively varying the basic quantization width "D" at each sampling. This method reduces storage requirements by storing differences between successive digital samples rather than full values. This method very effectively processes human and animal voices and natural sounds, reducing voice data storage space. This method offers high sound reproduction quality. 2. 4-, 5-, 6-, 7-, or 8-bit ADPCM2 method This method has higher sound reproduction quality than the ADPCM method. The ADPCM2 method offers five compression methods (4-, 5-, 6-, 7-, or 8-bit). Note that data used in the 4bit ADPCM method is not compatible with data in the 4-bit ADPCM2 method. Data conversion for these methods can be made by a development tool, AR204. 3. 8- or 16-bit straight PCM method This method has the highest sound reproduction characteristics in all frequencies (of the above four PCM methods). This method is suitable for sound effects having high frequencies and sounds having pulse-like waveforms. 4. 8-bit non-linear PCM method The method emphasizes the value of the center of each sound wave and processes it with 10 bit perceived accuracy. It is effective in improving the tone quality of frequency low voices and sounds. Voice synthesis methods and sampling frequencies during recording and playback The voice synthesis methods available during recording and playback and sampling frequency not available during recording with internal ADC are shown below.
Setup Voice synthesis method 4-bit ADPCM 4- to 8-bit ADPCM2 8-bit PCM 16-bit PCM 8-bit non-linear PCM Sampling frequency 4.0 to 16.0kHz 22.05 kHz, 32 kHz, 44.1 kHz Recording Monaural 4 * Monaural 4 4 Recording Monaural 8bit Bus 4 4 4 4 16bit Bus 4 4 8bit Bus 4 4 4 4 4 Playback Monaural 16bit Bus 4 4 4 4 4 Stereo 8bit Bus 4 4 4 4 4 16bit Bus 4 4 4 4 4
Playback Stereo 4 4
*note
It is available with an external ADC
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Semiconductor
MSM9841
Data configuration for each voice synthesis method Input/output data configuration are shown as bellows at recording and playback. When you selected 8-bit bus, you select which you use D15 to D8 pins or D7 to D0 pins. If you want to use D15 to D8 pins, please refer to replacing D7 to D0.
Data configuration when 8-bit bus is used "X" outputs "L" level during recording and is "don't care" during playback. 1. 4-bit ADPCM method and 4-bit ADPCM2 method
D7 MSB1 D6 3SB1 D5 2SB1 D4 LSB1 D3 MSB2 D2 3SB2 D1 2SB2 D0 LSB2
2. 5-bit ADPCM2 method
D7 D6 D5 D4 MSB1 D3 4SB1 D2 3SB1 D1 2SB1 D0 LSB1
3. 6-bit ADPCM2 method
D7 D6 D5 MSB1 D4 5SB1 D3 4SB1 D2 3SB1 D1 2SB1 D0 LSB1
4. 7-bit ADPCM2 method
D7 D6 MSB1 D5 6SB1 D4 5SB1 D3 4SB1 D2 3SB1 D1 2SB1 D0 LSB1
5. 8-bit ADPCM2 method, 8-bit straight PCM method, and 8-bit non-linear PCM method
D7 MSB1 D6 7SB1 D5 6SB1 D4 5SB1 D3 4SB1 D2 3SB1 D1 2SB1 D0 LSB1
6. 16-bit straight PCM method
D7 MSB1 8SB1 D6 15SB1 7SB1 D5 14SB1 6SB1 D4 13SB1 5SB1 D3 12SB1 4SB1 D2 11SB1 3SB1 D1 10SB1 2SB1 D0 9SB1 LSB1 1st transfer 2nd transfer
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Semiconductor
MSM9841
Data configuration when 16-bit bus is used "X" outputs "L" level during recording and is "don't care" during playback. 1. 4-bit ADPCM method and 4-bit ADPCM2 method
D15 MSB1 D7 MSB3 D14 3SB1 D6 3SB3 D13 2SB1 D5 2SB3 D12 LSB1 D4 LSB3 D11 MSB2 D3 MSB4 D10 3SB2 D2 3SB4 D9 2SB2 D1 2SB4 D8 LSB2 D0 LSB4
2. 5-bit ADPCM2 method
D15 D7 D14 D6 D13 D5 D12 MSB1 D4 MSB2 D11 4SB1 D3 4SB2 D10 3SB1 D2 3SB2 D9 2SB1 D1 2SB2 D8 LSB1 D0 LSB2
3. 6-bit ADPCM2 method
D15 D7 D14 D6 D13 MSB1 D5 MSB2 D12 5SB1 D4 5SB2 D11 4SB1 D3 4SB2 D10 3SB1 D2 3SB2 D9 2SB1 D1 2SB2 D8 LSB1 D0 LSB2
4. 7-bit ADPCM2 method
D15 D7 D14 MSB1 D6 MSB2 D13 6SB1 D5 6SB2 D12 5SB1 D4 5SB2 D11 4SB1 D3 4SB2 D10 3SB1 D2 3SB2 D9 2SB1 D1 2SB2 D8 LSB1 D0 LSB2
5. 8-bit ADPCM2 method, 8-bit straight PCM method, and 8-bit non-linear PCM method
D15 MSB1 D7 MSB2 D14 7SB1 D6 7SB2 D13 6SB1 D5 6SB2 D12 5SB1 D4 5SB2 D11 4SB1 D3 4SB2 D10 3SB1 D2 3SB2 D9 2SB1 D1 2SB2 D8 LSB1 D0 LSB2
6. 16-bit straight PCM method
D15 MSB1 D7 8SB1 D14 15SB1 D6 7SB1 D13 14SB1 D5 6SB1 D12 13SB1 D4 5SB1 D11 12SB1 D3 4SB1 D10 11SB1 D2 3SB1 D9 10SB1 D1 2SB1 D8 9SB1 D0 LSB1
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Semiconductor
MSM9841
FIFO memory configuration The configuration of FIFO memory can be changed with command on the D7 to D0 pins. Select FIFO memory configuration for bus width, monaural/stereo, and buffering times. Initially, the FIFO memory is 512 bits (64 words by 8 bits).
(1) FIFO memory configuration when an 8-bit bus and at monaural reproduction are selected The following three FIFO memory sizes are selectable by commands : 1024 bits (128 words by 8 bits) 512 bits (64 words by 8 bits, initial value) 256 bits (32 words by 8 bits ) (2) FIFO memory configuration when 16-bit bus and at monaural reproduction are selected The following three FIFO memory sizes are selectable by commands : 1024 bits (64 words by 16 bits) 512 bits (32 words by 16 bits) 256 bits (16 words by 16 bits ) (3) FIFO memory configuration when an 8-bit bus and at stereo reproduction are selected The following two FIFO memory sizes are selectable by commands : 512 bits (64 words by 8 bits) 2 256 bits (32 words by 8 bits) 2 (4) FIFO memory configuration when 16-bit bus and at stereo reproduction are selected The following two FIFO memory sizes are selectable by commands : 512 bits (32 words by 16 bits) 2 256 bits (16 words by 16 bits) 2 Voice synthesis methods and maximum buffering times FIFO capacity of 1024 bits and sampling frequency of 8 kHz (1) 8-bit bus selected (Monaural) (Stereo) 4-bit ADPCM2 or ADPCM : 32 ms 16 ms 5-, 6-, 7-, and 8-bit ADPCM2 : 16 ms 8 ms 8-bit PCM : 16 ms 8 ms (2) 16-bit bus selected (Monaural) (Stereo) 16-bit PCM : 16 ms 8 ms The other methods are the same as those when the 8-bit bus is used.
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Semiconductor Recording operation (8-bit bus, 512-bit FIFO configuration) (1)
MSM9841
Voice synthesis, sampling frequncy, and bus length are set with commands. In the recording mode, the 8-bit non-linear PCM method is not available. The 16-bit PCM method when 8-bit Bus is selected and 8-bit PCM method when 16-bit Bus is selected are not available. Recording is started by a command. During recording, when the voice analyzer has written one word in FIFO, the EMP pin goes low. Status indication by EMP, MID, and FUL pins * EMP="H", MID="L", FUL="L" No data is written in FIFO memory. * EMP="L", MID="L," FUL="L" Data of 1 word to 31 words has been written in FIFO memory. In this state, data cannot be read from FIFO memory. * EMP="L", MID="H", FUL="L" Data of 32 words to 63 words has been written in FIFO memory. While the MID pin is "H," you can read data from FIFO memory. When 32 words have been read from the FIFO memory, if MID="L", additional data can not be continuously read from the FIFO memory. If MID="H", additional 32 words can be continuously read from the FIFO memory. * EMP="L," MID="H," FUL="H" Data of 64 words is written in FIFO memory In this state, it is required to set the FUL pin to "L" before next data is transfered to the FIFO memory. If the FUL pin fails to be set to "L", the data transfer error flag is set. The data transfer error flag can be monitored by status read. End of recording Recording is terminated by a command. After Stop command is entered, the contents of the FIFO memory are cleared. Therefore, monitor the status of the EMP, MID and FUL pins before terminating recording after reading all FIFO memory data.
Change of FIFO memory status during recording Block from which data is being read Empty block Block to which data is being transfered Block to which data has been transfered
(2) (3)
(4)
(5)
EMP=H MID=L FUL=L
EMP=L MID=L FUL=L
EMP=L MID=H FUL=L
EMP=L MID=H FUL=L
EMP=L MID=H FUL=H
EMP=L MID=H FUL=L
EMP=L MID=H FUL=L
EMP=L MID=L FUL=L
EMP=H MID=L FUL=L
Recording data is transferable to external memory.
Enter the Stop command
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Semiconductor Playback operation (8-bit bus, 512-bit FIFO configuration) (1)
MSM9841
Voice synthesis, sampling frequncy, bus length, and stereo playback modes can be set by commands. When a Playback Start command is entered or when data of 1 word is written in FIFO, the MSM9841 recognizes the start of playback and starts synthesizing voices when the MID pin goes high ("H"). Status indication by EMP, MID, and FUL pins (64 words FIFO memory configuration) * EMP="H", MID="L", FUL="L" No data is written in FIFO memory. * EMP="L", MID="L", FUL="L" Data of 1 word to 31 words has been written in FIFO memory. In this state, the voice synthesizer cannot read data from FIFO memory. * EMP="L", MID="H", FUL="L" Data of 32 words to 63 words has been written in FIFO memory. While the MID pin is "H," the voice synthesizer can read data from FIFO memory. If the MID and FUL pins fail to be set to "H", when the voice synthesizer has completed reading 32 words from FIFO, the MID pin goes low. * EMP="L," MID="H," FUL="H" Data of 64 words is written in FIFO memory In this state, writing of 32 words into FIFO is completed before the voice synthesizer reads 32 words from FIFO and no data can be written in FIFO memory. End of playback In the case of EMP="L", MID="H", and FUL="L", if data is not written into the FIFO memory, playback is autimatically terminated. Playback also can be terminated with the Stop command. However, the FIFO memory data is cleared by input of the Stop command. The Stop command also can stop the playback the way.
Change of FIFO memory status during playback Block to which data is being written Block to which data has been written Block to which data is being transfered Empty block
(2)
(3)
(4)
EMP=H MID=L FUL=L
EMP=L MID=L FUL=L
EMP=L MID=H FUL=L Playback
EMP=L MID=H FUL=H
EMP=L MID=H FUL=L
EMP=L MID=H FUL=L
EMP=L MID=H FUL=L
EMP=L MID=L FUL=H
EMP=H MID=L FUL=L
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Semiconductor
MSM9841
Recording Data Transfer Flowchart (without DMA transfer)
Initial setting Set Voice Synthesis Method. Set Analog Mode. Set Bus width and DMA Transfer. Set FIFO Byte Configuration. Set Signal Output Format.
This flowchart shows that operations until entered STOP command after read out data in FIFO less than half. Therefore, actually enter STOP command after confirmed the status of MID "L" level.
Set RECORDING (START) Command. Set Sampling Frequency. No MID="H" ? Yes No STOP ? Yes
Read FIFO Data.
Yes
FUL="H" ? No
STOP ? Yes
No
MID="H" ? No STOP command input
Yes Read FIFO Data.
End of Recording
Note : At the STOP command is entered, EMP pin goes "H" and all data in FIFO is cleared.
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Semiconductor Playback Data Transfer Flowchart (without DMA transfer)
Initial setting Set Voice Synthesis Method. Set Analog Mode. Set Bus width and DMA Transfer. Set FIFO Byte Configuration. Set Signal Output Format.
MSM9841
Set PLAY (START) Command. Set Sampling Frequency.
Write FIFO Data.
FUL="H" ? No
Yes
STOP or Data End ? Yes Note2:
No
Note1 : When the EMP pin is "H" during playback, the MSM9841 goes to stop playback.
No
EMP="H" ? Yes Note1:
End of Playback
Note2 : When a stop command is entered or when data writing ends, the last data is transferred to the LSI and the EMP pin goes high. With this, all data transfer is completed. There are two cases to stop playback. One case is by STOP command. The other case is playback automatically stops after finishing data transfer.
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Semiconductor DMA Control Method
MSM9841
The MSM9841 sends a DMA Transfer request to the DMA controller and waits for a DMA transfer permission from the DMA controller. Upon reception of the permission, the MSM9841 starts data transfer at a transfer cycle of the DMA controller. The DMA Transfer function is enabled or disabled by commands. Default setting is disable. DREQL and DREQR pins (8-bit bus, 512-bit FIFO configuration) These pins are used to send a DMA Transfer request to the DMA controller. The amount of DMA transfer data is 32 words or 64 words, selected by commands. (1) Playback. When the PLAY (START) command is entered, the DREQL or DREQR pin goes high to request a cycle to write data into FIFO memory. After playback status, the DREQL/ R pins remain high until the 64-word write cycle is completed. When a 32-word write cycle is completed, voice synthesis starts. From now on, each time the amount of data in FIFO memory becomes half, the DREQL/R pins go high to send a request to DMA-transfer 32 words. (2) Recording. Recording starts with a command. When data of 32 words has been transfered to FIFO memory from the voice analyzer, the DREQL/R pins go high to request a cycle to read 32 words from FIFO memory. From now on, each time 32 words has been transfered to FIFO memory, the DREQL/R pins go high to send a request to DMA-transfer of 32 words. DACKL and DACKR Connect these pins to a DMA Transfer acknowledge signal from the DMA controller. When the DACKL/DACKR pins are at a low level ("L"), the IOW and IOR pins are enabled. IOW and IOR The IOW and IOR pins are enebled when the DACKL or DACKR pin goes low and their states are controlled by the DMA controller. The IOW pin is an input pin to transfer data from external memory to the MSM9841. The IOR pin is an input pin to transfer data from the MSM9841 to external memory.
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Semiconductor Recording Data Transfer Flowchart (with DMA transfer in Block mode)
MSM9841
Initial setting Set Voice Synthesis Method. Set Analog Mode. Set Bus width and DMA Transfer. Set FIFO Byte Configuration. Set Signal Output Format.
Note: Regarding DMA transfer in Block mode, refer to following "13. DMA TRANSFER SET Command".
RECORD (START) Command. Set Sampling Frequency.
STOP ? No
Yes
DREQL="H" ? Yes DACKL="H" DACKL="L"
No
No
DREQL="H" ? Yes DACKL="L"
IOR cycle (32 bytes)
IOR cycle
No 32 bytes transferred ?
End of transfer ? Yes
No
Yes STOP command
End of recording
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Semiconductor Recording Data Transfer Flowchart (with DMA transfer in Single mode)
MSM9841
Initial setting Set Voice Synthesis Method. Set Analog Mode. Set Bus width and DMA Transfer. Set FIFO Byte Configuration. Set Signal Output Format.
Note: Regarding DMA transfer in single mode, refer to following "13. DMA TRANSFER SET Command".
RECORD (START) command. Set Sampling Frequency.
STOP ? No
Yes
No DREQL="H" ? Yes No
DREQL="H" ? Yes
DACKL="L" DACKL="L" IOR cycle IOR cycle (32 bytes)
STOP command
End of recording
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Semiconductor
MSM9841
Playback Data Transfer Flowchart (with DMA transfer in Block mode)
Initial setting Set Voice Synthesis Method. Set Analog Mode. Set Bus width and DMA Transfer. Set FIFO Byte Configuration. Set Signal Output Format.
Note: Regarding DMA transfer in Block mode, refer to following "13. DMA TRANSFER SET Command".
PLAY (START) command. Set Sampling Frequency.
No
STOP ? Yes
DREQL="H" ? Yes
No Forced stop ? Yes No
DACKL="H"
DACKL="L" STOP command Yes First ? No Status reading IOW cycle (64 bytes) IOW cycle (32 bytes) EMP="H" ? Yes 64 bytes transfered ? Yes No 32 bytes transfered ? Yes No End of playback
No
Note 1 : The above flowchart assumes that FIFO memory is 64 bytes long. The MSM9841 writes data 64 bytes as a block in the first write-operation and writes a 32-byte block in the second and later write operations. A time period between the input of a DREQ request and the end of block writing depends upon a sampling frequency and the voice synthesis method. For example, when a 8 kHz sampling frequency and a 8-bit ADPCM2 voice synthesis method are set, a 32-byte block writing must be completed within 2 ms. Note 2 : The MSM9841 supports two kinds of Playback Stop sequence:Forced stop by a STOP command and stop by status reading. When Playback is forcibly stopped by a STOP command, data in FIFO memory is all cleared. When status reading is made, Playback is stopped after all data left in FIFO memory is processed (EMP="H").
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Semiconductor
MSM9841
Playback Data Transfer Flowchart (with DMA transfer in Single mode)
Initial setting Set Voice Synthesis Method. Set Analog Mode. Set Bus width and DMA Transfer. Set FIFO Byte Configuration. Set Signal Output Format.
Note: Regarding DMA transfer in single mode, refer to following "13. DMA TRANSFER SET Command".
PLAY (START) command. Set Sampling Frequency.
No
STOP ? Yes
DREQL="H" ? Yes
No Forced stop ? Yes No
DACKL="L" STOP command Yes First ? No Status reading IOW cycle (64 bytes) IOW cycle (32 bytes) EMP="H" ? Yes End of playback
No
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Semiconductor Recording time and memory capacity
MSM9841
The recording time of the MSM9841 is dependent on the storage capacitance of external memory, the sampling frequency, and the width of ADPCM bits that have been specified. The recording time of the MSM9841 is expressed by
Recording time= 1.024 Memory size (in K bits) Sampling frequency (kHz) Width of ADPCM bits (seconds)
For example, when 8.0 kHz of sampling frequency, 4 bit of ADPCM 2, and 8 M bit of memory size are set, the recording time is calculated as follows:
Recording time= 1.024 8000 8.0 4 =256 (second) = 4 minutes 16 seconds
Connection of power supply The MSM9841 contains a single power supply as shown below. The power supply is connected to the analog unit and digital unit separately.
+5V
DVDD
AVDD
MSM9841
DGND AGND
Avoid following power supply connections:
Power supply for the analog circuit Power supply for the digital circuit DVDD AVDD
Power supply DVDD AVDD
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Semiconductor Analog Input Amplifier Circuit
The MSM9841 contains two OP amplifiers to amplify a voice signal from a microphone. Each OP amplifier is provided with the inverting input pin and output pin. The analog circuit reference voltage SG (signal ground) is input internally to the non-inverting input of each OP amplifier.
For amplification, form an inverting amplifier circuit and adjust the amplification ratio by using external resistors as shown below.
VIN
- +
VMO R1 MIN
- +
VLO R3 R4 LOUT
-
R2 MOUT
LIN
OP amplifier 1
+
OP amplifier 2
SG
VLO=
R4 R3
VMO=
R2 * R4 R1 * R3
VIN (V)
During recording, the output VLO of the OP amplifier 2 is fed to LPF. Adjust the amplification ratio by an external resistor so that the output voltage VLOUT may be in the LOUT-permissible input voltage range. If VLOUT is not in this range, the waveform of the LPF output may be deformed.
The table below shows an examples of LOUT- permissible input voltage ranges of the MSM9841.
Model name Supply Voltage VDD 5V 3V LOUT-permissible voltage range VLOUT min max 1V 0.75 V 4V 2.25 V LOUTpermissible voltage 3Vp-p 1.5Vp-p
MSM9841
The load resistance ROUTA of the OP amplifier is 200 kW (minimum). Therefore, the feedback resistors R2 and R4 of the inversion type amplifying circuit must be 200 kW or higher. If you use only OP amplifier 2, connect MIN pin to AGND, and leave MOUT pin open as bellows. If you don't need to amplify, you must use OP amplifier 2. The bellows figure shows the circuit example of one times the amplification ratio with setting R3 and R4 to 200 kW.
VIN (200kW) R3 + (200kW) R4
,,
MSM9841
VDD VLO VLOUT (max.) 1/2VDD VLOUT (min.) GND
AVDD or AGND MIN - + SG
-
MOUT
LIN - +
LOUT
OP amplifier 1
OP amplifier 2 MSM9841
device name
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Semiconductor
MSM9841
The process of SG pin SG signal indicades the reference voltage SG (Signal Ground) for internal OP amplifiers and input LPF. To avoid the noise on this signal, insert capacitors to SG pin as bellows. We recommend capacitance of 0.1 mF, and to fix the value of capacitor after sound quality evaluation.
AVDD 0.1mF MSM9841 SG 0.1mF AGND or MSM9841 SG 0.1mF
The figure shows the internal equivalence circuit of SG pin.
AVDD Power-down or standby signals
Approximately 50kW (TYP) SG Approximately 50kW (TYP)
AGND
After canceled the Power Down states or Standby states, it takes about scores millisecond until DC level for SG pin and Analog circuit stabilize. It takes longer in proportion to the value of capacitance. Start to read or write operation after DC level stabilized.
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Semiconductor Frequency characteristics of the input side LPF
MSM9841
The MSM9841 contains a 4-order low path filter (LPF) produced in the switch capacitor filter technology in the input of a analog signal during recording. The attenuation characteristic is -40 dB/oct. The cut-off frequency and frequency characteristic vary in proportion to the sampling frequency (fs). The cut-off frequency is always 0.4 times the sampling frequency. Below is shown the frequency characteristics of the input side LPF (at fs = 8 kHz).
[dB]
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 100 1000 10000 40000
[Hz] Frequency characteristics of the input side LPF (at fs = 8 kHz)
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Semiconductor
MSM9841
Frequency characteristics of the output side LPF The MSM9841 contains two low path filters (LPF) produced in the digital filter technology in the output of the DA converter during playback. Below are shown the frequency characteristics of the output side LPF (at fs = 8 kHz and 16 kHz).
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 100 1000 10000 40000 [Hz]
Frequency characteristics of the output side LPF (at fs = 8 kHz)
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 100 1000 10000 40000 [Hz]
Frequency characteristics of the output side LPF (at fs = 16 kHz)
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Semiconductor
MSM9841
Using an External DAC Select the External DAC mode and, 2's Complementary or Binary by commands. The MSM9841 interfaces to the external DAC through the DASD, SIOCK, and VCK pins. In monaural playback, the MSM9841 outputs data when the VCK pin is at a high level ("H"). In stereo playback, the MSM9841 outputs left data when the VCK pin is at a high level ("H") and right data when the VCK pin is at a low level ("L"). Figure 6 shows stereo playback timing of the external DAC at a sampling frequency of 32 kHz (maximum). Data is valid in back justification. Left voice data is valid if it is entered before the VCK signal falls. Right voice data is valid if it is entered before the VCK signal rises.
VCK SIOCK DASD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 MSB LSB MSB LSB Left voice data Right voice data
Stereo playback timing of the external DAC at VCK=32 kHz
Using External ADC Select the External ADC mode and, 2's Complementary or Binary by commands. The MSM9841 interfaces to the external ADC through the ADSD, SIOCK, and VCK pins. Figure 7 shows playback timing of the external ADC at a sampling frequncy of 32 kHz (maximum). Data is valid in back justification. Data is valid if it is entered before the VCK signal falls.
VCK SIOCK ADSD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 MSB LSB
Recording timing of the external ADC at VCK=32 kHz
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Semiconductor
MSM9841
COMMAND LIST D7 0 0 0 0 0 0 0 0 1 1 1 1 1 D6 0 0 0 0 1 1 1 1 0 0 0 0 1 D5 0 0 1 1 0 0 1 1 0 0 1 1 0 D4 0 1 0 1 0 1 0 1 0 1 0 1 0 D3 0 C3 C3 C3 C3 W3 P3 R3 A3 F3 G2 D2 0 S2 S2 C2 C2 V2 W2 P2 R2 A2 0 D2 G1 D1 0 S1 S1 C1 V1 P1 R1 E1 B1 D1 G0 D0 0 S0 S0 V0 P0 R0 E0 B0 D0 NOP (No Operation) RECORDING START PLAY START STOP PAUSE VOLUME SETTING POWER-DOWN MODE VOICE SYNTHESIS METHOD Analog specification 1 Analog specification 2 and bus width FIFO memory configuration Signal output format DMA Transfer =don't care Function
Voice synthesis method P3 0 0 0 0 0 0 0 0 1 P2 0 0 0 0 1 1 1 1 0 P1 0 0 1 1 0 0 1 1 0 P0 0 1 0 1 0 1 0 1 0 Function 4-bit Oki ADPCM2 5-bit Oki ADPCM2 6-bit Oki ADPCM2 7-bit Oki ADPCM2 8-bit Oki ADPCM2 4-bit Oki ADPCM 8-bit PCM 8-bit Oki non-linear PCM 16-bit PCM *
Volume Setting V2 0 0 0 0 1 1 1 1 V1 0 0 1 1 0 0 1 1 V0 0 1 0 1 0 1 0 1 0dB * -3dB -6dB -9dB -12dB -15dB -18dB -21dB
Sampling frequency S2 0 0 0 0 1 1 S1 0 0 1 1 0 0 S0 0 1 0 1 0 1 fSAM 8.0 kHz * 12.8 kHz 16.0 kHz 32.0 kHz 6.4 kHz 4.0 kHz
Voice Output Setting C3 0 1 C2 0 0 1 Function Left voice Right voice Common to both left and right sides *
Pause Setting C1 0 1 Function Starts pausing Cancels pausing
* : initial status
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Semiconductor
MSM9841
FIFO memory configuration B1 0 Note 0 1 1 B0 0 1 0 1 512 bits 1024 bits 256 bits FIFO not used Function *
Analog specification 2 and data bus transfer setting A3 0 1 A2 0 1 E1 0 1 E0 0 1 Function With output amplifier Without output amplifier Function With LPF Without LPF Function 8-bit bus width 16-bit bus width Function D15 to D8 not used for 8-bit bus D15 to D8 used for 8-bit bus * * * *
Note : Disable in the stereo playback mode
Analog specification 1 R3 0 1 R2 0 1 R1 0 1 R0 0 1 Function Output in 2's complementary. Output in binary. Function Use internal DAC. Use external DAC. Function Use internal ADC. Use external ADC. Function Monaural playback Stereo playback * * * *
Signal output format F3 0 1 D2 0 1 D1 0 1 D0 0 1 *Default Function EMP, MID, and FUL outputs : Active high EMP, MID, and FUL outputs : Active low Function DREQL and DREQR outputs : Active high DREQL and DREQR outputs : Active low Function DACKL and DACKR outputs : Active low DACKL and DACKR outputs : Active high Function No function For tesing. Don't use * * * *
Power-down W3 0 1 W2 0 1 Function Cancel power-down. Start power-down. Function Retain LSI internal setting. Initialize LSI internal setting * *
DMA transfer G3 0 1 1 G2 0 0 G1 0 1 Function Without DMA transfer Single mode transfer Block mode transfer *
* : initial status
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Semiconductor Description of commands 1. NOP command
D7 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 0
MSM9841
No function
2. RECORDING command
D7 0 D6 0 D5 0 D4 1 D3 D2 S2 D1 S1 D0 S0
This command starts recording. Bits D2 to D0 specify a sampling frequency.
S2 0 0 0 0 1 1 S1 0 0 1 1 0 0 S0 0 1 0 1 0 1 Sampling frequency 8.0 kHz 12.8 kHz 16.0 kHz 32.0 kHz (Note) 6.4 kHz 4.0 kHz *
Note : This command can not be used when internal ADC is selected.
3. PLAYBACK command
D7 0 D6 0 D5 1 D4 0 D3 C3 D2 S2 D1 S1 D0 S0
This command starts playback. Bits D2 to D0 specify a sampling frequency. Bit D3 selects left or right voice data to be played back. For stereo playback, left and right sampling frequencies must be the same. For monaural playback, when you specify to play continuously phrases of difference sampling frequency, STOP command needs before the next phrase playback.
C3 0 1 Function Playback of left voice. Playback of right voice. *
* : initial status
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Semiconductor 4. STOP command
D7 0 D6 0 D5 1 D4 1 D3 C3 D2 C2 D1 D0
MSM9841
In the recording mode, this command ends recording and the setting of bits D3 and D2 is ignored. After this command is entered, FIFO data is cleared. In the playback mode, this command aborts playback. When this command is entered, data in FIFO memory is cleared. Bit D3 selects left or right voice whose playback is aborted. Turn on bit D2 to abort playback of both left and right voices at a time.
C3 0 1
C2 0 0 1
Function Aborts playback of left voice Aborts playback of right voice Aborts playback of left and reight voices.
5. PAUSE command
D7 0 D6 1 D5 0 D4 0 D3 C3 D2 C2 D1 C1 D0
This command pauses the current playback or recording operation. Bit D1 enables or disables pausing. When recording is paused, the setting of bits D3 and D2 is ignored. When playback is paused, bit D3 selects left or right voice whose playback is paused. Turn on bit D2 to pause playback of both left and right voices.
C1 0 1 Function Starts pausing. Cancels pausing.
C3 0 1
C2 0 0 1
Function Pauses playback of left voice Pauses playback of right voice Pauses playback of both left and reight voices.
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Semiconductor 6. VOLUME command
D7 0 D6 1 D5 0 D4 1 D3 C3 D2 V2 D1 V1 D0 V0
MSM9841
This command controls the volumes of playback voices. Bit D3 selects a left or right voice to be volume-controleled during playback. Bits D2 to D0 set a volume.
C3 0 1
V2 0 0 0 0 1 1 1 1
Function Sets the volume of left voice. Sets the volume of right voice.
V1 0 0 1 1 0 0 1 1 V0 0 1 0 1 0 1 0 1 Volume 0 dB -3 dB -6 dB -9 dB -12 dB -15 dB -18 dB -21 dB *
7. POWER-DOWN command
D7 0 D6 1 D5 1 D4 0 D3 W3 D2 W2 D1 D0
When receiving this command, the MSM9841 stops oscillation, minimizes the current consumption, and enters the power-down mode. The AOUTL and AOUTR outputs immediately fall to the GND level. Bit D3 enables or disables the powerdown function and bit D2 enables or disables initialization of the internal circuit of the MSM9841.
W3 0 1 Enter the power-down mode W2 0 1 Function Disables initialization of the internal circuit of the LSI. Enables initialization of the internal circuit of the LSI. Function Concel the power-down mode
* : initial status
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Semiconductor 8. VOICE SYNTHESIS METHOD command
D7 0 D6 1 D5 1 D4 1 D3 P3 D2 P2 D1 P1 D0 P0
MSM9841
This command selects a voice synthesis method. Bits D3 to D0 select a method. A total of nine voice synthesis methods are selectable. The selected voice synthesis method cannot be changed while playback or recording is in progress.
P3 0 0 0 0 0 0 0 0 1 P2 0 0 0 0 1 1 1 1 0 P1 0 0 1 1 0 0 1 1 0 P0 0 1 0 1 0 1 0 1 0 Voice synthesis method 4-bit ADPCM2 5-bit ADPCM2 6-bit ADPCM2 7-bit ADPCM2 8-bit ADPCM2 4-bit ADPCM 8-bit straight PCM 8-bit non-linear PCM 16-bit straight PCM *
9. ANALOG SPECIFICATION 1 command
D7 1 D6 0 D5 0 D4 0 D3 R3 D2 R2 D1 R1 D0 R0
This command selects the built-in ADC or DAC, the external ADC or DAC, indication of 2's complement or binary, and stereo or monaural playback. When the MSM9841 is turned on, the AOUTL and AOUTR pin voltages immediately rise to 1/2 VDD.
R3 0 1 R2 0 1 R1 0 1 R0 0 1 Function 2's complement complementary Binary Function Internal DAC External DAC Function Internal ADC External ADC Function Monaural playback mode Stereo playback mode * * * *
* : initial status
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Semiconductor 10. ANALOG SPECIFICATION DATA BUS WIDTH SET command
D7 1 D6 0 D5 0 D4 1 D3 A3 D2 A2 D1 E1 D0 E0
MSM9841
D3 selects use or disuse of the internal output amplifiers to the AOUTL Pin and the AOUTR Pin. D2 selects use or disuse of the internal LPFs to the AOUTL Pin and the AOUTR Pin. D1 and D0 set a data bus width and select use or disuse of D15 to D8 for voice data transfer when the 8-bit bus is selected. D1 and D0 select "D15 to D8 not used for 8-bit bus width'' when D7 to D0 pins are used to transfer (input or output) all data including commands, status, and data. D1 and D0 select "D15 to D8 used for 8-bit bus width'' when D15 to D8 pins are used to input or output data and D7 to D0 pins are used to input or output commands and statuses.
A3 0 1 A2 0 1 E1 0 0 1 E0 0 1 Function With output amplifier Without output amplifier Function With LPF Without LPF Function D15 to D8 not used for 8-bit bus width D15 to D8 used for 8-bit bus width 16-bit bus width * * *
* : initial status 11. FIFO MEMORY SPECIFICATION command
D7 1 D6 0 D5 1 D4 0 D3 D2 0 D1 B1 D0 B0
This command selects a bit configuration (word configuration) of the FIFO memory. When stereo playback is selected, this command selects a left side or right side bit configuration (word configuration). Therefore, the 1024-bit configuration can not be selected because the MSM9841 contains 1024 bits of FIFO memory.
B1 * Note 0 0 1 1
B0 0 1 0 1
8-bit bus configuration 512 bits (64 words) 1024 bits (128 words) 256 bits (32 words)
16-bit bus configuration 512 bits (32 words) 1024 bits (64 words) 256 bits (16 words)
FIFO memory not used
Note: For stereo playback, the word configuration cannot be selected. * : initial status
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Semiconductor 12. SIGNAL OUTPUT FORMAT CONTROL command
D7 1 D6 0 D5 1 D4 1 D3 F3 D2 D2 D1 D1 D0 D0
MSM9841
This command sets the output formats of the EMP, MID, FUL, DREQL, and DREQR pins and the input formats of the DACKL and DACKR pins.
F3 0 1 D2 0 1 D1 0 1 D0 0 1 Function EMP, MID, FUL outputs : Active high EMP, MID, FUL outputs : Active low Function DREQL and DREQR outputs : Active high DREQL and DREQR outputs : Active low Function DACKL and DACKR inputs : Active low DACKL and DACKR inputs : Active high Function No function For test. Not used * * *
13. DMA TRANSFER SET Command
D7 1 D6 1 D5 0 D4 0 D3 G3 D2 G2 D1 G1 D0
This command sets use or disuse of DMA transfer or selects DMA transfer mode. When the Single mode DMA transfer is selected, if the DREQL pin or stereo playback is selected, the DREQL pin is active while DMA transfer is being requested. The Single mode DMA transfer is selected when transfering data monitoring the status of the DREQL or DREQR pin without controlling the number of bytes to be transfered. When the Block mode DMA transfer is selected, if the DREQL pin or stereo playback is selected, the DREQR sends a DMA request signal and becomes inactive when the DACKL pin or DACKR pin is active. The Block mode DMA transfer is selected when the number of bytes to be transfered can be controlled and the DREQL or DREQR pin is set to be inactive.
G3 0 1 1 G2 0 0 G1 0 1 Function Without transfer Single mode DMA transfer Block mode DMA transfer *
* : initial status
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Semiconductor Description of Status The MSM9841 supports the following seven status flags :
D7 D6 D5 D4 D3 D2 D1 D0 Left Data Recording/Playing flag Right Data Playing flag Left Pause flag Right Pause flag EMP Information Output flag MID Information Output flag FUL Information Output flag Data Transfer Error flag
MSM9841
High when recording or playback is in progress High when playback is in progress High when playback of left voice is paused High when playback of right voice is paused Output the same signal as the EMP pin. Output the same signal as the MID pin. Output the same signal as the FUL pin. See the explanation below.
Note: EMP, MID, and FUL output the High Active signals. These bits don't be feedback to the output format by command. The MSM9841 supports the following three data transfer errors : When FIFO memory is used (1) "H" when a read operation is mode while EMP is "H" (2) "H" when a read operation is mode while MID is "L" (3) "H" when a write operation is mode while FUL is "H"
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Semiconductor
MSM9841
CPU INTERFACE EXAMPLES
1) Interface when DMA controller is used (16-bit bus)
Memory M9841
DMA Controller
D15 to D0 DREQL DACKL IOW IOR DREQR DACKR
MCU RD WR CS D/C
Data bus
2) MCU & external memory interface (16-bit bus)
Memory M9841 D15 to D0 DACKL IOW IOR MCU RD WR CS D/C CH EMP MID FUL
Data bus
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Semiconductor
MSM9841
PACKAGE DIMENSIONS
(Unit : mm)
QFP56-P-910-0.65-2K
Mirror finish
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 0.43 TYP.
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, TQFP, LQFP, SOJ, QFJ (PLCC), SHP, and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person on the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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E2Y0002-29-62
NOTICE
1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. Neither indemnity against nor license of a third party's industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party's right which may result from the use thereof. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. No part of the contents contained herein may be reprinted or reproduced without our prior permission. MS-DOS is a registered trademark of Microsoft Corporation.
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Copyright 1999 Oki Electric Industry Co., Ltd.
Printed in Japan

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