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19-2539; Rev 1; 1/03
Low-Power, Low-Distortion, Central-Office ADSL Drivers and Integrated Drivers/Receivers
General Description
The MAX9480/MAX9481/MAX9482 low-power, low-distortion, class-G, high-current asymmetric digital subscriber line (ADSL) drivers offer Rail-to-Rail(R) output and are ideal for ADSL in central-office applications. Operating from 5V and 2.5V supplies, the drivers incorporate two high-speed current-feedback preamplifiers driving two fixed-gain class-G buffers. The buffers can deliver 20.4dBm average line power with a signal crest factor of 5.3, and are designed to be directly DC or AC bridged across a 1:2.5 transformer. The MAX9480/MAX9481/MAX9482 employ an active line termination scheme for incoming signals that eliminates the need for back-match resistors, reducing line-card power consumption at full rate to less than half of that required by conventional class-AB line-driver circuits. The MAX9480 includes a hybrid network and two lownoise, fixed-gain-of-4.6V/V receive amplifiers. The part is designed to recover the receive signal to the same level as that of a conventional line interface circuit that incorporates a 1:2 transformer and standard back-matched hybrid, without degrading signal-to-noise ratio (SNR) or line-impedance sensitivity. The MAX9481 provides only the preamplifiers and buffers without the hybrid or receivers. The MAX9482 provides preamplifiers, buffers, and uncommitted receive amplifiers. All devices have a low-output-impedance shutdown function for saving power when not transmitting. At full-rate 20.4dBm discrete multitone data transmission (DMT), the total dynamic power dissipation is only 680mW (MAX9480/MAX9482) or 655mW (MAX9481). The MAX9480/MAX9481 are available in a 20-pin TSSOP package and the MAX9482 is available in 28-pin TSSOP and 32-pin QFN packages. All devices operate over the extended -40C to +85C temperature range.
Features
o Dissipate Only 655mW While Driving 20.4dBm ADSL Full-Rate DMT-Modulated Signal o Operate with 5.0V and 2.5V Power Supplies o Complete ADSL Central-Office Line Interface (MAX9480/MAX9482) Two Preamplifiers plus Class-G Rail-to-Rail Buffers Active Line Termination plus Integrated Hybrid (MAX9480) Low-Noise Uncommitted Receive Amplifiers (MAX9482) Fixed-Gain Receive Amplifiers (MAX9480) Low-Output-Impedance Shutdown Mode o Preamplifiers, Buffers, and Active Line Termination Functions (MAX9481) o High-Output-Drive Capability 15VP-P Differential Output Voltage Swing at RL = 16 500mA Output-Drive o Low Distortion: -71dBc Highest Harmonic at 1MHz and 14VP-P o High Speed: 250V/s Slew Rate, 80MHz -3dB Bandwidth (G = -3) o Thermal Shutdown o Exposed Pads Improve Thermal Performance
MAX9480/MAX9481/MAX9482
Ordering Information
PART MAX9480CUP MAX9481CUP MAX9482CUI MAX9482CGJ* TEMP RANGE -40C to +85C -40C to +85C -40C to +85C -40C to +85C PIN-PACKAGE 20 TSSOP-EP** 20 TSSOP-EP 28 TSSOP-EP 32 QFN
Applications
Full-Rate ADSL HDSL Central Office DSLAM
*Future product--contact factory for availability. **EP = Exposed pad.
Pin Configurations
20 VLM 19 VLP 18 VCC 17 OUT1
TOP VIEW
POUT1 1 IN1- 2 IN1+ 3 RXP 4 DGND 5 SHDN 6 RXM 7 IN2+ 8
MAX9480
16 VEE 15 VEE 14 OUT2 13 VCC 12 VLP 11 VLM
Typical Operating Circuits appear at end of data sheet. Rail-to-Rail is a registered trademark of Nippon Motorola, Ltd.
IN2- 9 POUT2 10
TSSOP
Pin Configurations continued at end of data sheet. ________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Low-Power, Low-Distortion, Central-Office ADSL Drivers and Integrated Drivers/Receivers MAX9480/MAX9481/MAX9482
ABSOLUTE MAXIMUM RATINGS
VCC to VEE ...........................................................................+12V VLP to VLM ............................................................................+12V VCC or VLP to DGND ................................................-0.3V to +6V VCC to VLP ................................................................-0.3V to +6V VEE or VLM to DGND ................................................-6V to +0.3V VEE to VLM ................................................................-6V to +0.3V Current into VLP or VLM ..................................................250mA IN1+, IN1-, IN2+, IN2-......................(VCC + 0.3V) to (VEE - 0.3V) SHDN ...............................................(VCC + 0.3V) to (VEE - 0.3V) BOUT1/BOUT2 Output Short-Circuit Duration to VCC/VEE/VLP/VLM ....................................................Momentary BOUT1/BOUT2 Output Current...........................................20mA OUT1/OUT2 Output Short-Circuit Duration to VCC/VEE/VLP/VLM ....................................................Momentary OUT1/OUT2 Output Current ....................................................1A OUT1 to OUT2 Short-Circuit Duration ........................Continuous POUT1/POUT2 Output Short-Circuit Duration to VCC/VEE/VLP/VLM ................................................................10s POUT1/POUT2 Output Current .........................................100mA RXP/RXM Output Short-Circuit Duration to VCC/VEE/VLP/VLM ................................................................10s RXP/RXM Output Current..................................................100mA Continuous Power Dissipation (TA = +70C) 20-Pin TSSOP with Pad Connected to VEE (derate 21.7mW/C above +70C) ..............................1739mW 20-Pin TSSOP with Floating Pad (derate 11.0mW/C above +70C) ................................879mW 28-Pin TSSOP with Pad Connected to VEE (derate 23.8mW/C above +70C) ..............................1905mW 28-Pin TSSOP with Floating Pad (derate 12.8mW/C above +70C) ..............................1026mW 32-Pin QFN (derate 23.3mW/C above +70C) .........1860mW* Operating Temperature Range (TMIN, TMAX) .....................................................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C *Refer to Application Note HFAN-08-1.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC = +5V, VEE = -5V, VLP = +2.5V, VLM = -2.5V, DGND = 0, RL = 16 is connected from OUT1 to OUT2, SHDN = 0, TA = TMIN to TMAX, unless otherwise noted. Typical values specified at TA = +25C. Preamp configured for AV = +1 with 1k from POUT_ to IN_-.) (Note 1)
PARAMETER Dynamic Power Dissipation SYMBOL PDISS CONDITIONS VOUT(DIFF) = 1.327VRMS, crest factor = 5.3 MAX9480/ MAX9482 MAX9481 Dynamic Power Consumption PCONS VCC Supply Voltage Range VEE VLP VLM VOUT(DIFF) = 1.327VRMS, crest factor = 5.3 (Note 2) (Note 2) (Note 2) (Note 2) MAX9480, RL = Quiescent Supply Current (Including Preamps) ICC, IEE, ILP, ILM MAX9481, RL = MAX9482, RL = VCC, VEE VLP, VLM VCC, VEE VLP, VLM VCC, VEE VLP, VLM MAX9480/ MAX9482 MAX9481 4.75 -4.75 2.25 -2.25 MIN TYP 680 655 790 765 5.00 -5.00 2.50 -2.50 21.5 22.0 20.0 21.0 21.5 22.0 5.25 -5.25 2.75 -2.75 35.0 40.0 34.0 39.0 35.0 40.0 mA V mW MAX UNITS mW
2
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Low-Power, Low-Distortion, Central-Office ADSL Drivers and Integrated Drivers/Receivers
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +5V, VEE = -5V, VLP = +2.5V, VLM = -2.5V, DGND = 0, RL = 16 is connected from OUT1 to OUT2, SHDN = 0, TA = TMIN to TMAX, unless otherwise noted. Typical values specified at TA = +25C. Preamp configured for AV = +1 with 1k from POUT_ to IN_-.) (Note 1)
PARAMETER SYMBOL CONDITIONS MAX9480, RL = Shutdown Supply Current ISD MAX9481, RL = MAX9482, RL = Transmit Path Power-Supply Rejection Ratio (Single Ended) Common-Mode Rejection Hybrid Rejection Ratio (MAX9480 Only) Driver-to-Receiver Crosstalk (MAX9482 Only) SHDN Logic Low SHDN Logic High SHDN Input Current Shutdown Delay Time Shutdown Enable Time Intermodulation Distortion DRIVER Maximum RMS Output Power (Typical Operating Circuit) (Note 3) Closed-Loop Gain Second Harmonic Distortion Third Harmonic Distortion Differential Output Voltage Swing OUT_ Voltage Swing (per Amplifier) (Note 4) DMT modulation (crest factor, Cr = 5.33) POUT CAP modulation (crest factor, Cr = 4.00) G VOUT(DIFF) = 1.2VP-P f = 1MHz, VOUT(DIFF) = 14VP-P, Typical Operating Circuit (Note 4) f = 1MHz, VOUT(DIFF) = 14VP-P, Typical Operating Circuit (Note 4) VOUT(DIFF) Typical Operating Circuit (Note 4) RL = 100 VOH, VOL RL = 16 BOUT_ Voltage Swing (per Amplifier) (Note 4) Peak Output Current Differential Output Offset Voltage VBOH, VBOL IOUT VOS(DIFF) IN1+ = IN2+ = 0 VCC - VOH |VEE - VOL| VCC - VOH |VEE - VOL| VCC - VBOH |VEE - VBOL| 24.3 -2.7 -3 -71 -74 15.0 0.5 0.5 1.27 1.21 0.45 0.42 500 5 V mA mV V -3.3 V/V dB dB VP-P 21.4 dBmW PSRR CMR HRR XTALK VIL VIH IIH, IIL tSHDN tENABLE IMD f1 = 1MHz, f2 = 900kHz, Typical Operating Circuit, VOUT(DIFF) = 2.0VP-P SHDN = 0 or SHDN = VCC 4.8 4 -66 2.0 5.0 VCC - VEE = 4.75V to 5.25V VLP - VLM = 2.25V to 2.75V -200mV VCM +200mV VOUT(DIFF) = 1.2V f = 100kHz VCC, VEE VLP, VLM VCC, VEE VLP, VLM VCC, VEE VLP, VLM 50 50 MIN TYP 2.1 1.5 0.6 0.05 2.1 1.5 76 81 46 35 -69 0.8 MAX 6.0 5.0 1.2 0.1 6.0 5.0 dB dB dB dB V V A s s dB mA UNITS
MAX9480/MAX9481/MAX9482
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Low-Power, Low-Distortion, Central-Office ADSL Drivers and Integrated Drivers/Receivers MAX9480/MAX9481/MAX9482
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +5V, VEE = -5V, VLP = +2.5V, VLM = -2.5V, DGND = 0, RL = 16 is connected from OUT1 to OUT2, SHDN = 0, TA = TMIN to TMAX, unless otherwise noted. Typical values specified at TA = +25C. Preamp configured for AV = +1 with 1k from POUT_ to IN_-.) (Note 1)
PARAMETER Differential Output Offset-Voltage Drift Output Resistance (per Amplifier) -3dB Bandwidth Slew Rate Output Noise PSD Capacitive Load Stability PREAMPS AND RECEIVERS (Note 5) Open-Loop Transimpedance Power-Supply Rejection Ratio Input Offset Voltage IN1+, IN2+, RXIN1+, RXIN2+ Bias Current IN1+, IN2+, RXIN1+, RXIN2+ Bias Current Matching IN1-, IN2-, RXIN1-, RXIN2Bias Current IN1-, IN2-, RXIN1-, RXIN2Bias Current Matching Input Resistance Input Capacitance ZOL PSRR VOS IB+ IOS+ IBIOSRIN CIN IN1+, IN2+, RXIN1+, RXIN2+ IN1-, IN2-, RXIN1-, RXIN2IN1+, IN2+, IN1-, IN2-, RXIN1+, RXIN2+, RXIN1-, RXIN2-2V POUT +2V VCC - VEE = 4.75V to 5.25V VLP - VLM = 2.25V to 2.75V 50 50 300 87 100 2 1 0.7 2.6 1.2 1.1 200 2 20 10 20 k dB mV A A A A M pF SYMBOL VOS(DRIFT) ROUT BW SR PN VOUT(DIFF) = 14VP-P step f = 100kHz to 1.1MHz, referred to 100 line No sustained oscillations -200mV VOUT +200mV SHDN = VCC 6 CONDITIONS MIN TYP 12 8 8 80 250 -127 1000 10 MAX UNITS V/C MHz V/s dBm/Hz pF
Note 1: All devices are 100% production tested at TA = +25C. Specifications over temperature limits are guaranteed by design. Note 2: Guaranteed by the PSRR test. Note 3: Implied by worst-case output voltage swing (VOUT(DIFF)), crest factor (Cr), and load impedance (RL):
250 x V2 OUT(DIFF) PDRIVER = 10 log10 dBmW Cr 2 x RL
Note 4: Device may exceed absolute maximum ratings for power dissipation if unit is subjected to full-scale sinusoids for long periods. See the Applications Information section. Note 5: Receiver specifications guaranteed for MAX9482 only.
4
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Low-Power, Low-Distortion, Central-Office ADSL Drivers and Integrated Drivers/Receivers
Typical Operating Characteristics
(VCC = +5V, VEE = -5V, VLP = +2.5V, VLM = -2.5V, DGND = 0, RXIN1+ = RXIN2+ = 0, IN1+ = IN2+ = 0, RL = 16 is connected from OUT1 to OUT2, SHDN = 0, TA = +25C, unless otherwise noted. Preamp configured for AV = +1 with 1k from RXOUT_- to RXIN_-. Receiver configured for AV = +1 with 1k from POUT_ to IN_-.)
SUPPLY CURRENT vs. OUTPUT VOLTAGE
= 5V SUPPLY = 2.5V SUPPLY INPUT = DC
MAX9480 toc01
MAX9480/MAX9481/MAX9482
SUPPLY CURRENT vs. TEMPERATURE
MAX9480 toc02
SHUTDOWN CURRENT vs. TEMPERATURE
MAX9481 SHUTDOWN CURRENT (mA) 2.4 2.5V SUPPLY
MAX9480 toc03
600 500 SUPPLY CURRENT (mA) 400 300 200 100 0 0 1
30 MAX9481 26 SUPPLY CURRENT (mA) 2.5V SUPPLY 5V SUPPLY
3.0
IDC
fINPUT = 1MHz IAVG IAVG
22
1.8
18
1.2 5V SUPPLY
fINPUT = 100kHz
14
0.6
10 2 3 4 5 6 7 8 9 10 -40 -15 10 35 60 85 VOUTP-P (V) TEMPERATURE (C)
0 -40 -15 10 35 60 85 TEMPERATURE (C)
TRANSMIT PATH FREQUENCY RESPONSE
80 60 40 GAIN (dB) 20 0 -20 -40 -60 -80 0.01 = GAIN = PHASE 0.1 1 FREQUENCY (MHz) 10 OVERALL GAIN = -3V/V PREAMP GAIN = +1V/V OVERALL GAIN = -9V/V PREAMP GAIN = +3V/V
MAX9480 toc04
DRIVER HARMONIC DISTORTION vs. FREQUENCY
VOUTP-P = 2.0V -160 HARMONIC DISTORTION (dBc) -20 -180 -200 -220 -240 -260 -280 -300 100 -100 0.01 0.1 1 10 FREQUENCY (MHz) PHASE (DEGREES)
MAX9480 toc05
-140
0
-40 2ND HARMONIC -60
-80 2ND HARMONIC 3RD
DRIVER HARMONIC DISTORTION vs. OUTPUT VOLTAGE
-10 HARMONIC DISTORTION (dBc) -20 -30 GAIN (dB) -40 -50 -60 -70 -80 -90 -100 2 4 6 8 10 12 14 16 18 VOUT (DIFF) (VP-P) SUPPLY CROSSOVER REGION -30 -40 0.01 2ND HARMONIC 3RD 2ND HARMONIC f = 1MHz
MAX9480 toc06
RECEIVER AMPLIFIER FREQUENCY RESPONSE
30 20 10 0 -10 A -20 = GAIN = PHASE 0.1 1 10 100 C 0 B C -45 -90 -135 1000 A B 90 45 PHASE (DEGREES)
MAX9480 toc07
0
135
FREQUENCY (MHz) C: GAIN = 1V/V A: GAIN = 10V/V B: GAIN = 5V/V
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Low-Power, Low-Distortion, Central-Office ADSL Drivers and Integrated Drivers/Receivers MAX9480/MAX9481/MAX9482
Typical Operating Characteristics (continued)
(VCC = +5V, VEE = -5V, VLP = +2.5V, VLM = -2.5V, DGND = 0, RXIN1+ = RXIN2+ = 0, IN1+ = IN2+ = 0, RL = 16 is connected from OUT1 to OUT2, SHDN = 0, TA = +25C, unless otherwise noted. Preamp configured for AV = +1 with 1k from RXOUT_- to RXIN_-. Receiver configured for AV = +1 with 1k from POUT_ to IN_-.)
RECEIVER INPUT NOISE vs. FREQUENCY
100 inCURRENT NOISE (pA/Hz) VOLTAGE NOISE (nV/Hz) DISTORTION (dBc)
MAX9480 toc08
RECEIVER AMPLIFIER HARMONIC DISTORTION vs. FREQUENCY
RLOAD = 150 VOUT = 1VP-P AV = 10V/V
MAX9480 toc09
100
-40 -50 -60 3RD HARMONIC -70 2ND HARMONIC -80 -90
10
in+
10
en 1 0.001 1 0.01 0.1 1 FREQUENCY (MHz)
-100 0.001
0.01
0.1
1
FREQUENCY (MHz)
RECEIVER AMPLIFIER HARMONIC DISTORTION vs. OUTPUT AMPLITUDE
RLOAD = 150 f = 100kHz AV = 1V/V 3RD HARMONIC
MAX9480 toc10
OUTPUT NOISE vs. FREQUENCY
MAX9480 toc11
-40 -50 DISTORTION (dBc) -60 -70 2ND HARMONIC -80 -90 -100 0 1 2 3 4 OUTPUT VOLTAGE (VP-P)
-100 -110 OUTPUT NOISE (dBm/Hz) -120 -130 -140 -150 -160 0.0001 PREAMP GAIN = 3 PREAMP GAIN = 1
0.001
0.01
0.1
1
FREQUENCY (MHz)
VOH AND VOL vs. TEMPERATURE
MAX9480 toc12
POWER DISSIPATION vs. LINE POWER
750 POWER DISSIPATION (mW) 700 650 MAX9480/MAX9482 600 550 500 450 400 12 13 14 15 16 17 18 19 20 21 22 LINE POWER (dBm) MAX9481
MAX9480 toc13
1.40 1.35 1.30 VOH AND VOL (V) 1.25 1.20 1.15 1.10 1.05 1.00 -40 -15 10 35 60 |VCC - VOL| VCC - VOL
800
85
TEMPERATURE (C)
6
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Low-Power, Low-Distortion, Central-Office ADSL Drivers and Integrated Drivers/Receivers
Pin Description
PIN MAX9480 1 2 3 4 5 6 7 8 9 10 11, 20 12, 19 13, 18 14 15, 16 17 -- -- -- -- -- -- -- EP MAX9481 2 3 4 -- 5 6 -- 7 8 9 11, 20 12, 19 13, 18 14 15, 16 17 1 10 -- -- -- -- -- EP MAX9482 TSSOP 2 3 4 11 5 6 16 7 8 9 18, 28 19, 27 20, 25 21 22, 23 24 1 10 12 13 14 15 17, 26 EP QFN 31 1 2 10 3 4 15 5 6 7 17, 28 18, 27 19, 24 20 21, 22 23 30 8 11 12 13 14 9, 16, 25, 26, 29, 32 EP POUT1 IN1IN1+ RXP DGND SHDN RXM IN2+ IN2POUT2 VLM VLP VCC OUT2 VEE OUT1 BOUT1 BOUT2 RXIN1RXIN1+ RXIN2+ RXIN2N.C. VEE First Preamp Output First Inverting Input First Noninverting Input Positive Receiver Output from Internal Hybrid Ground Shutdown Control Pin Negative Receiver Output from Internal Hybrid Second Preamp Noninverting Input Second Preamp Inverting Input Second Preamp Output -2.5V Negative Power-Supply Voltage +2.5V Positive Power-Supply Voltage +5V Positive Power-Supply Voltage Second Driver Output -5V First Negative Power-Supply Voltage First Driver Output First Driver Output Sense Second Driver Output Sense First Receiver Inverting Input First Receiver Noninverting Input Second Receiver Noninverting Input Second Receiver Inverting Input Not Internally Connected Exposed pad internally connected to VEE. See the Applications Information section. NAME FUNCTION
MAX9480/MAX9481/MAX9482
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Low-Power, Low-Distortion, Central-Office ADSL Drivers and Integrated Drivers/Receivers MAX9480/MAX9481/MAX9482
Detailed Description
The MAX9480/MAX9481/MAX9482 are fully differential line transceivers for ADSL applications. Each transmit path has a high-bandwidth, low-distortion, current-feedback operational amplifier followed by a fixed-gain class-G output buffer. The MAX9480/MAX9481/MAX9482 are class-G devices and require two dual power supplies, 5V and 2.5V. All preamplifier inputs and outputs are available to allow external gain configuration. The MAX9480 contains an internal hybrid echo cancellation circuit with receiver amplifiers set to a fixed gain of 4.6V/V. The MAX9482 has no internal hybrid, but contains two uncommitted low-noise op amps for coupling to an external hybrid network. The MAX9481 has only the preamp and line-driver circuits. The two class-G output buffers are internally configured for an inverting gain of three, and employ an active termination scheme that presents an 8 load to incoming signals. The buffers are designed for use with a 1:2.5 line transformer and can deliver 20.4dBm average line power with a signal crest factor of 5.3 into a standard 100 line. The outputs are designed to be directly DCor AC-bridged across the transformer. The MAX9480/MAX9481/MAX9482 have a low-output impedance, low-power shutdown mode that is activated by driving SHDN high. Transmit path amplifiers and buffers are disabled while the part is in shutdown, and an 8 resistor is coupled directly between OUT_ and the output of a three-state buffer referenced to DGND (0V). The receive amplifiers remain active in shutdown mode.
Applications Information
Theory of Operation
The preamplifiers and receivers are current-feedback amplifiers; thus, their open-loop transfer function is expressed as a transimpedance, VOUT/IIN, or ZOL. The frequency behavior of their open-loop transimpedance is similar to the open-loop gain of a voltage-feedback amplifier; that is, they have a large DC value that decreases at approximately 6dB per octave. Analyzing the follower with gain, as shown in Figure 1, yields the following transfer function: ZOL(S) VOUT = Gx VIN ZOL(S) + G x (RIN + RF )
[Equation 1]
where G = AVCL = 1 + (RF/RG), and RIN = 1/gM 200. At low gains, G x RIN << RF. Therefore, the closed-loop bandwidth is essentially independent of closed-loop gain. Similarly, ZOL >> RF at low frequencies, so that: VOUT R = G = 1+ F VIN RG
[Equation 2]
Shutdown
Forcing SHDN high puts the MAX9480/MAX9481/ MAX9482 into low-power shutdown mode. In shutdown mode, OUT1 and OUT2 are low impedance, and the power-supply currents drop to less than 10% of their normal quiescent operating values. When coming out of shutdown, allow about 1.5s before commencing operation.
PC Board Layout
RG RF
RIN +1 +1 ZOL VOUT
VIN
MAX9480 MAX9481 MAX9482
Figure 1. Current Feedback Amplifier Block Diagram
Power-Supply Bypassing The MAX9480/MAX9481/MAX9482 are wide-bandwidth devices and require careful board layout, including the possible use of constant-impedance microstrip or stripline techniques. To realize the full AC performance of these high-speed amplifiers, pay careful attention to power-supply bypassing. The PC board should have at least two layers: a signal and power layer on one side, and a large, low-impedance ground plane on the other side. The ground plane should be as free of voids as possible. With multilayer boards, locate the ground plane on a layer that incorporates no signal or power traces. Observe the following guidelines when designing the board. IC sockets increase parasitic capacitance and inductance, and should not be used. Do not make 90 turns; round all corners. Observe high-frequency bypassing techniques to maintain the amplifier's
8
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Low-Power, Low-Distortion, Central-Office ADSL Drivers and Integrated Drivers/Receivers
accuracy. The bypass capacitors should include a 0.1F ceramic capacitor between each supply pin and the ground plane, located as close to the package as possible. Additionally, place a 1F to 10F ceramic or tantalum capacitor in parallel with each 0.1F capacitor, and as close to them as possible. Place a 10F to 15F low-ESR tantalum capacitor at the VCC, VLM, and VLP power-supply points of entry to the PC board. Place a 100F to 220F low-ESR tantalum capacitor at the VEE power-supply point of entry to the PC board. The powersupply traces should lead directly from the board input capacitors to VCC and VEE. To minimize parasitic inductance, keep PC traces short and use surface-mount components. Wire-wrapped boards are much too inductive, and breadboards are much too capacitive; neither should be used. Power-supply sequencing is required; apply 5.0 before applying 2.5V. Exposed-Pad Connection For optimum electrical performance, the EP of the MAX9480/MAX9481/MAX9482 should be soldered to the PC board and electrically connected to VEE with as wide a trace as possible. If using the EP, the 100F to 220F low-ESR tantalum capacitor should be used to decouple the EP to the ground plane of the PC board as close to the EP region as possible. For optimum thermal performance, the EP should be additionally connected to a heat sink, as described in the Thermal Protection and Power Dissipation section. Preamp Output Bypassing In addition to the above layout considerations, and independent of the gain setting, some high-frequency bypassing of the preamp outputs is necessary to prevent instability arising from the high-frequency input impedance characteristics of the buffers. A 50 resistor in series with a 2200pF ceramic capacitor should be connected between POUT_ and DGND, with a 47pF capacitor connected directly between POUT_ and DGND.
DC and Noise Errors
There are several error sources to consider when using any operational amplifier, and this applies to the MAX9480/MAX9481/MAX9482 as well. Offset-error terms are given by equations 3 and 4. Voltage and current-noise errors are root-square summed and therefore computed separately. In Figure 3, the total output offset voltage is determined by: * The input offset voltage, VOS, times the closed-loop gain (1 + (RF / RG)). * The positive input bias current, IB+, times the source resistor, RS (typically less than 10), plus the negative input bias current, IB-, times the parallel combination of R G and R F . In current-mode feedback amplifiers, the input bias currents may flow into or out of the device. For this reason, there is no benefit to matching the resistance at both inputs, as is common in voltage-feedback amplifiers.
MAX9480/MAX9481/MAX9482
VIN RG RT RF
MAX9480 MAX9481 MAX9482 RS
VOUT
(a)
VOUT = -
RF ( RG ) (VIN )
RG
RF
Choosing Feedback and Gain Resistors
The MAX9480/MAX9481/MAX9482 use current-feedback amplifiers. Figure 2 shows the standard inverting and noninverting configurations. Notice that the gain of the noninverting circuit, Figure 2(b), is 1 plus the magnitude of the inverting closed-loop gain. Increasing feedback resistor values decreases peaking. Use the input resistor, RG, to change the magnitude of the gain. Do not use feedback capacitance.
(b) MAX9480 MAX9481 MAX9482 RT VOUT
VIN
VOUT = 1+ RF RG
[ ( )] (VIN )
Figure 2. Inverting Gain Configuration and Noninverting Gain Configuration _______________________________________________________________________________________ 9
Low-Power, Low-Distortion, Central-Office ADSL Drivers and Integrated Drivers/Receivers MAX9480/MAX9481/MAX9482
R7 800 RG RF R8 667 IBIB+ RS MAX9480 MAX9481 MAX9482 VOUT R1 1.6 ZOUT
Figure 3. Input Offset Voltage and Current
R10 540
R9 945
The equation for total DC error is: [Equation 3] R VOUT = (IB + )RS + (IB - )(RF || RG ) + VOS 1 + F RG
Figure 4. Active Line Termination Scheme, Single Side
[
]
Driving Capacitive Loads
The MAX9480/MAX9481/MAX9482 receive amplifiers are optimized for AC performance. They are not designed to drive highly capacitive loads. Reactive loads decrease phase margin and can produce excessive ringing and oscillation.
The total output-referred noise voltage is: [Equation 4] R en(OUT) = 1+ F RG
[(in+ )Rs] + [(in- )RF || RG ]
2
2
+ (en )2
Output-Impedance Synthesis
To help meet the contradictory requirements of high output power and low-power use, the active termination circuit shown in Figure 5 is used. This circuit is designed to present a line termination of 8. R1 is a physical 1.6 resistor voltage feedback from the outboard end of R1 to the noninverting input of the amplifier, introduces positive feedback, which increases the effective output-impedance value from 1.6 to 8. Hence, the impedance looking into the port matches the line impedance reflected through the transformer. Assuming an ideal amplifier, the following equation expresses the output impedance: ZOUT = R1 R7 R10 1 - 1 + R8 R9 + R10
The MAX9480/MAX9481/MAX9482 have very low noise input voltage (en), 3.5nV/Hz (typ). The current noise at the noninverting input (in+) is 4.0pA/Hz (typ), and the current noise at the inverting input, in-, is 15pA/Hz (typ). An example of the DC error calculations, using the MAX9480 data and the Typical Operating Circuit where RF = RG = 1k (RF || RG = 500) and RS = 50, gives the following, using equation 3: 1000 x 1000 -6 50 + 2.6 x 10-6 1.0 x 10 1000 + 1000 VOUT = 1000 + 0.002 x 1 + 1000 where VOUT = 6.7mV at the preamp outputs. Calculating total preamp output noise using equation 4 yields 16.6nV/Hz, which then contributes 50nV/Hz at the driver output. The driver noise contributes an additional 35mV/Hz, to the overall output noise.
(
)(
)
[Equation 5]
Substituting the values of the resistors shown in Figure 4 into equation 5, we obtain ZOUT = 8. The output equivalent circuit for the line driver is shown in Figure 5.
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Low-Power, Low-Distortion, Central-Office ADSL Drivers and Integrated Drivers/Receivers
ZOUT = 8 1:2.5 LINE + ZOUT = 100
Tx PORT
LINE PORT
ZIN = 16
ZOUT = 8
LINE -
Figure 5. Output Equivalent Circuit
With a 1:2.5 transformer, the two 8 impedances realized by the active-feedback network form a perfect line termination. The MAX9480 family's active termination design makes it possible to use a 5V power supply instead of 12V or 15V, significantly increasing driver efficiency.
In this pseudo-class-G amplifier, there is no abrupt supply switchover between the higher voltage and the lower voltage amplifiers, as in a traditional class G. It is a seamless transition that depends only on the amplitude of the input signal and the gain. The lower voltage amplifier has a high conversion conductance, GA, and the higher voltage amplifier has a low conductance, GB. With a low input voltage, the lower voltage amplifier provides most of the output current to the load. As the voltage of the input signal increases, the lower voltage amplifier starts to saturate and the higher voltage amplifier begins to drive the output.
MAX9480/MAX9481/MAX9482
0.8Rx MAX9480 R4 1.2k Tx R1 1.6 R3 1k
Rx 0.8Tx OUT1 LINE PORT
Hybrid Considerations
The MAX9480 includes an internal hybrid coupling circuit to realize the receive function with no external components. The hybrid couples the transmitted signal from the line-driver port (Tx port) to the line port and cancels the echo in the receiving port (Rx port). The hybrid circuit is detailed in Figure 6. If using the MAX9481 or the MAX9482, external circuitry must be added to realize a receive function. The MAX9482 includes two uncommitted op amps for this purpose. A traditional hybrid network with a 2:1 resistor ratio must be replaced with a 1.2:1 ratio to achieve nominal echo cancellation. Additionally, the use of a synthesized output impedance has the side effect of preventing a "virtual-ground" condition at the driver output (BOUT), as seen by the receive signal. Hence, the resulting hybrid circuit exhibits an increased attenuation of the receive signal with respect to a traditional case with no synthesis. For central-office ADSL applications, the noise specifications allow this trade-off to be made.
RXM 0Tx + 0.18Rx Tx PORT Rx PORT 0Tx - 0.18Rx RXP R6 1.2k R2 1.6 -0.8Rx -Tx (a) HYBRID CIRCUIT IN MAX9480 R5 1k OUT2 -Rx -0.8Tx
0Rx Tx 8 2k 1k
Rx 0.5Tx OUT1 LINE PORT
RXM 0Tx + 0.67Rx Tx PORT Rx PORT 0Tx - 0.67Rx RXP 2k 8 -0.0Rx -Tx (b) TRADITIONAL HYBRID CIRCUIT 1k OUT2 -Rx -0.5Tx
Pseudo-Class-G Amplifier
The driver consists of two stages: the current-feedback preamplifier and the voltage-feedback buffer. To save power, the preamplifier uses a power supply of only 2.5V. The output swing of the preamplifier is about 3.0VP-P. The buffer is designed as a pseudo-class-G amplifier with a fixed gain of -3V/V. This buffer stage employs two power supplies: a lower voltage supply, 2.5V, and a higher voltage supply, 5V. In the differential driver, two parallel amplifiers provide the output current to the load, as shown in Figure 7.
Figure 6. Hybrid Circuit in the MAX9480
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Low-Power, Low-Distortion, Central-Office ADSL Drivers and Integrated Drivers/Receivers MAX9480/MAX9481/MAX9482
This smooth transition between the lower voltage amplifier and the higher voltage amplifier guarantees no glitch on the output signal, and ensures high linearity for high output power, while at the same time consuming minimum power. The relation between the input voltage and the output current of this pseudo-class-G buffer is illustrated in Figure 8. Typical Operating Circuit, the MAX9480 is coupled to the phone line through just such a transformer. The total differential load for the MAX9480 is therefore 16. Active termination is included on all devices in the MAX9480 family (as explained above in the OutputImpedance Synthesis section).
Receiver Channel Considerations
A step-up transformer at the output of the differential line driver has a step-down effect on signals received from the line. A voltage attenuation equal to the inverse of the turns ratio is realized in the receive channel. This is an addition to the attenuation due to the hybrid circuitry itself (see the Hybrid Considerations section).
Thermal Protection and Power Dissipation
The MAX9480/MAX9481/MAX9482 are available in the EP version of the TSSOP. The EP facilitates heat transfer out of the package if the pad is soldered to a heat sink made from an area of circuit board copper. Connect this copper dissipation area to V EE . For a DMT-modulated signal with a crest factor greater than or equal to 5.3, the power dissipation of the MAX9480/MAX9481/MAX9482 should not exceed 700mW; the 20-pin TSSOP-EP package with its EP floating allows 714mW peak power at +85C. Hence, heat sinking is not essential, but is desirable for attaining optimal electrical performance. Note that the part is capable of 500mA peak output current, which could cause thermal shutdown in applications with elevated ambient temperatures and/or signals with low crest factors. The thermal shutdown feature prevents the die temperature from exceeding +150C. See Figure 9 for a guide to power derating for each of the packages.
I
IOUT
IOUTB IOUTA
Transformer Selection
Full-rate, central-office ADSL requires the transmission of a +20.4dBm (110mW) DMT signal. The DMT signal has a typical crest factor of 5.3, requiring the line driver to provide peak line power of 35.4dBm (3.4W). The 35.4dBm peak line power translates to a 36V peak-topeak differential voltage on a 100 line. The output swing available from the MAX9480 family of line drivers with a 5V supply is 15.0VP-P, and hence a step-up transformer with turns ratio of 1:2.5 is needed. In the
+2.5V LOWER VOLTAGE AMPLIFIER -2.5V VIN +5V HIGHER VOLTAGE AMPLIFIER -5V LOAD IOUTA
VIN
Figure 8. Amplifier Output Characteristics
5000 28-TSSOP, PAD TO VEE MAXIMUM DISSIPATION (mW) 4000 QFN 20-TSSOP, PAD TO VEE
3000
IOUT
2000
1000 28-TSSOP, PAD FLOATING 20-TSSOP, PAD FLOATING -40 -15 10 35 60 85
IOUTB
0
TEMPERATURE (C)
Figure 7. Output Stage of Pseudo-Class-G Amplifier
Figure 9. Maximum Power Dissipation vs. Temperature
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Low-Power, Low-Distortion, Central-Office ADSL Drivers and Integrated Drivers/Receivers
Typical Operating Circuits
RCVP
MAX9480/MAX9481/MAX9482
5V 1.00k IN1POUT1 VCC
2.5V VLP
MAX9480
IN1+ OUT1
SHDN
8
RXM 1:2.5
DGND INPUT
PHONE LINE 100
8
RXP
IN2+
OUT2
IN21.00k
POUT2
VEE
VLM
RCVN
-5V
-2.5V
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Low-Power, Low-Distortion, Central-Office ADSL Drivers and Integrated Drivers/Receivers MAX9480/MAX9481/MAX9482
Typical Operating Circuits (continued)
1.0k 250 RCVP
5V 1.00k IN1POUT1 VCC
2.5V VLP
1.20k
1.00k
BOUT1
IN1+ OUT1
SHDN
8 1:2.5
DGND INPUT 8
PHONE LINE 100
MAX9481
IN2+
OUT2
BOUT2 IN21.00k POUT2 VEE -5V VLM -2.5V 1.20k 1.00k
RCVN 250k
1.0k
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Low-Power, Low-Distortion, Central-Office ADSL Drivers and Integrated Drivers/Receivers
Typical Operating Circuits (continued)
RCVP 5V VCC 2.5V 1.0k VLP RXP RXIN1250
MAX9480/MAX9481/MAX9482
POUT1 RXIN1+ 1.00k 1.20k IN1BOUT1 1.00k
IN1+ OUT1
SHDN
8
1:2.5 PHONE LINE 100
DGND INPUT 8
MAX9482
IN2+
OUT2
BOUT2 IN21.00k POUT2 RXIN2VEE -5V VLM -2.5V RXM 1.0k RCVN 250 1.20k RXIN2+ 1.00k
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Low-Power, Low-Distortion, Central-Office ADSL Drivers and Integrated Drivers/Receivers MAX9480/MAX9481/MAX9482
Pin Configurations (continued)
POUT1 N.C. N.C. N.C. VLM VLP N.C.
TOP VIEW
BOUT1
32
31
30
29
28
27
BOUT1 1 POUT1 2 IN1- 3 IN1+ 4 DGND 5 SHDN 6 IN2+ 7 IN2- 8 POUT2 9 BOUT2 10
20 VLM 19 VLP 18 VCC 17 OUT1
BOUT1 1 POUT1 2 IN1- 3 IN1+ 4 DGND 5 SHDN 6 IN2+ 7 IN2- 8 POUT2 9 BOUT2 10 RXP 11
28 VLM 27 VLP 26 N.C. 25 VCC IN1IN1+ DGND SHDN IN2+ IN2POUT2 BOUT2
26
25 24 23 22 21
1 2 3 4 5 6 7 8 10 11 12 13 14 15 16
VCC OUT1 VEE VEE OUT2 VCC VLP VLM
MAX9481
16 VEE 15 VEE 14 OUT2 13 VCC 12 VLP 11 VLM
MAX9482
24 OUT1 23 VEE 22 VEE 21 OUT2 20 VCC 19 VLP 18 VLM 17 N.C. 16 RXM 15 RXIN2-
MAX9482
20 19 18 17
N.C.
RXIN1-
RXIN1+
RXIN2+
RXIN2-
RXM
RXIN1+ 13 RXIN2+ 14
QFN
TSSOP
Chip Information
MAX9480 TRANSISTOR COUNT: 2557 MAX9481 TRANSISTOR COUNT: 2557 MAX9482 TRANSISTOR COUNT: 2607 PROCESS: Bipolar
16
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N.C.
RXP
TSSOP
RXIN1- 12
9
Low-Power, Low-Distortion, Central-Office ADSL Drivers and Integrated Drivers/Receivers
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
TSSOP, 4.0,EXP PADS.EPS
MAX9480/MAX9481/MAX9482
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Low-Power, Low-Distortion, Central-Office ADSL Drivers and Integrated Drivers/Receivers MAX9480/MAX9481/MAX9482
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
32L QFN.EPS
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
18 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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