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19-2688; Rev 0; 1/03
Differential 8:1 ECL/PECL Multiplexer with Dual Output Buffers
General Description
The MAX9389 is a fully differential, high-speed, low-jitter, 8-to-1 ECL/PECL multiplexer (mux) with dual output buffers. The device is designed for clock and data distribution applications, and features extremely low propagation delay (310ps typ) and output-to-output skew (30ps max). Three single-ended select inputs, SEL0, SEL1, and SEL2, control the mux function. The mux select inputs are compatible with ECL/PECL logic, and are internally referenced to the on-chip reference output (VBB1, VBB2), nominally VCC - 1.425V. The select inputs accept signals between VCC and VEE. Internal pulldowns to VEE ensure a low default condition if the select inputs are left open. The differential inputs D_, D_ can be configured to accept a single-ended signal when the unused complementary input is connected to the on-chip reference output (V BB1, V BB2). All the differential inputs have internal bias and clamping circuits that ensure a low output state when the inputs are left open. The MAX9389 operates with a wide supply range VCC VEE of 2.375V to 5.5V. The device is offered in 32-pin TQFP and thin QFN packages, and operates over the -40C to +85C extended temperature range. o 310ps Propagation Delay o Guaranteed 2.7GHz Operating Frequency o 0.3psRMS Random Jitter o <30ps Output-to-Output Skew o -2.375V to -5.5V Supplies for Differential LVECL/ECL o +2.375V to +5.5V Supplies for Differential LVPECL/PECL o Outputs Low for Open Inputs o Dual Output Buffers o >2kV ESD Protection (Human Body Model)
Features
MAX9389
Ordering Information
PART MAX9389EHJ MAX9389ETJ* TEMP RANGE -40C to +85C -40C to +85C PIN-PACKAGE 32 TQFP 32 Thin QFN
*Future product--contact factory for availability.
Applications
High-Speed Telecom and Datacom Applications Central-Office Backplane Clock Distribution DSLAM/DLC
D0 D0 D1
Functional Diagram
MAX9389
Pin Configurations
SEL2
D1 D2 VCC VEE
TOP VIEW
VCC VCC VEE Q0 Q0 Q1 Q1 32 VCC VBB2 VBB1 D0 D0 D1 D1 VCC 1 2 3 4 5 6 7 8 9 D2 10 D2 11 D3 12 D3 13 D4 14 D4 15 D5 31 30 29 28 27 26
D2 D3 D3 24 SEL1 23 SEL0 D5 22 VCC D5 21 D7 D4 D4 MUX 8:1
25
Q0 Q0 Q1 Q1 VBB1 VBB2
MAX9389
D6 D6 D7 D7 SEL0 232k D_ D_ 165k 180k VEE 180k VCC 180k
20 D7 19 D6 18 D6 17 VEE 16 D5
SEL1 SEL2
TQFP
VEE
Pin Configurations continued at end of data sheet. ________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Differential 8:1 ECL/PECL Multiplexer with Dual Output Buffers MAX9389
ABSOLUTE MAXIMUM RATINGS
VCC - VEE ..............................................................-0.3V to +6.0V Inputs (D_, D_, SEL_) to VEE ......................-0.3V to (VCC + 0.3V) D_ to D_...............................................................................3.0V Continuous Output Current .................................................50mA Surge Output Current........................................................100mA VBB_ Sink/Source Current ..............................................600A Continuous Power Dissipation (TA = +70C) 32-Lead TQFP (derate 13.1mW/C above +70C) ...1047mW JA in Still Air..........................................................+76C/W JC .........................................................................+25C/W 32-Lead QFN (derate 21.3mW/C above +70C) .....1702mW JA in Still Air..........................................................+47C/W JC ...........................................................................+2C/W Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C ESD Protection Human Body Model (D_, D_, Q_, Q_, SEL_, VBB_) .............2kV Soldering Temperature (10s) ...........................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC - VEE = 2.375V to 5.5V, outputs loaded with 50 1% to VCC - 2V. Typical values are at VCC - VEE = 3.3V, VIHD = VCC - 1V, VILD = VCC - 1.5V, unless otherwise noted.) (Notes 1-4)
PARAMETER SYMBOL CONDITIONS -40C MIN TYP MAX MIN +25C TYP MAX MIN +85C TYP MAX UNITS
INPUT (D_, D_, SEL_) Single-Ended Input High Voltage Single-Ended Input Low Voltage Differential Input High Voltage Differential Input Low Voltage VIH VBB_ connected to the unused input, Figure 1 VCC 1.225 VCC 0.880 VCC 1.225 VCC 0.880 VCC 1.225 VCC 0.880 V
VIL
VBB_ connected to the unused input, Figure 1 Figure 1 Figure 1 VCC - VEE < 3.0V Figure 1 VCC - VEE 3.0V
VCC 1.945 VEE + 1.2 VEE 0.095 0.095 -60
VCC 1.625 VCC VCC 0.095 VCC VEE 3.000 +60
VCC 1.945 VEE + 1.2 VEE 0.095 0.095 -60
VCC 1.625 VCC VCC 0.095 VCC VEE 3.000 +60
VCC 1.945 VEE + 1.2 VEE 0.095 0.095 -60
VCC 1.625 VCC VCC 0.095 VCC VEE 3.000 +60
V
VIHD VILD
V V
Differential Input Voltage Input Current OUTPUT (Q_, Q_) Single-Ended Output High Voltage
VIHD VILD IIN
V
VIH, VIL, VIHD, VILD
A
VOH
Figure 2
VCC 1.145
VCC 0.895
VCC 1.145
VCC 0.895
VCC 1.145
VCC 0.895
V
2
_______________________________________________________________________________________
Differential 8:1 ECL/PECL Multiplexer with Dual Output Buffers
DC ELECTRICAL CHARACTERISTICS (continued)
(VCC - VEE = 2.375V to 5.5V, outputs loaded with 50 1% to VCC - 2V. Typical values are at VCC - VEE = 3.3V, VIHD = VCC - 1V, VILD = VCC - 1.5V, unless otherwise noted.) (Notes 1-4)
PARAMETER Single-Ended Output Low Voltage Differential Output Voltage SYMBOL CONDITIONS -40C MIN VCC 1.945 650 830 TYP MAX VCC 1.695 MIN VCC 1.945 650 840 +25C TYP MAX VCC 1.695 MIN VCC 1.945 650 840 +85C TYP MAX VCC 1.695 UNITS
MAX9389
VOL VOH VOL VBB1 VBB2 IEE
Figure 2
V
Figure 2
mV
REFERENCE OUTPUT (VBB_ ) Reference Voltage Output POWER SUPPLY Supply Current (Note 6) 50 70 53 70 55 70 mA IBB1 + IBB2 = 0.5mA (Note 5) VCC 1.525 VCC 1.425 VCC 1.325 VCC 1.525 VCC 1.425 VCC 1.325 VCC 1.525 VCC 1.425 VCC 1.325 V
AC ELECTRICAL CHARACTERISTICS
(VCC - VEE = 2.375V to 5.5V, outputs loaded with 50 1% to VCC - 2V, VIHD - VILD = 0.15V to 1V, fIN 2.5GHz, input duty cycle = 50%, input transition time = 125ps (20% to 80%). Typical values are at VCC - VEE = 3.3V, VIHD = VCC - 1V, VILD = VCC - 1.5V, fIN = 622 MHz, input duty cycle = 50%, input transition time = 125ps (20% to 80%.)) (Note 7)
PARAMETER Differential Inputto-Output Delay SEL_-to-Output Delay Output-to-Output Skew Input-to-Output Skew Part-to-Part Skew Added Random Jitter (Note 12) Added Deterministic Jitter (Note 12) SYMBOL tPLHD, tPHLD tPLH2, tPHL2 tSKOO tSKIO tSKPP CONDITIONS Figure 2 Figure 4, input transition time = 500ps (20% to 80%) (Note 8) Figure 5 (Note 9) Figure 6 (Note 10) (Note 11) fIN = 156MHz Clock fIN = 622MHz pattern fIN = 2.5GHz PRBS 223 - 1 fIN = 156Mbps fIN = 622Mbps 0.3 0.3 0.3 33 21 -40C MIN 216 TYP 301 MAX 370 MIN 237 +25C TYP 310 MAX 416 MIN 255 +85C TYP 329 MAX 456 UNITS ps
1.34
2
1.25
2
1.44
2
ns
15 50 125 1.15 1.15 1.15 95 61 0.3 0.3 0.3 33 21
15 50 150 1.15 1.15 1.15 95 61 0.3 0.3 0.3 33 21
30 55 160 1.15 1.15 1.15 95
ps ps ps
tRJ
psRMS
TDJ
psP-P 61
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3
Differential 8:1 ECL/PECL Multiplexer with Dual Output Buffers MAX9389
AC ELECTRICAL CHARACTERISTICS (continued)
(VCC - VEE = 2.375V to 5.5V, outputs loaded with 50 1% to VCC - 2V, VIHD - VILD = 0.15V to 1V, fIN 2.5GHz, input duty cycle = 50%, input transition time = 125ps (20% to 80%). Typical values are at VCC - VEE = 3.3V, VIHD = VCC - 1V, VILD = VCC - 1.5V, fIN = 622 MHz, input duty cycle = 50%, input transition time = 125ps (20% to 80%.)) (Note 7)
PARAMETER Switching Frequency Select Toggle Frequency Output Rise and Fall Time (20% to 80%) SYMBOL fMAX fSEL CONDITIONS VOH - VOL 300mV, Figure 2 VOH - VOL 300mV, Figure 4 Figure 2 -40C MIN 2.7 100 TYP MAX MIN 2.7 100 +25C TYP MAX MIN 2.7 100 +85C TYP MAX UNITS GHz MHz
tR, tF
67
105
138
74
117
155
81
128
165
ps
Note 1: Measurements are made with the device in thermal equilibrium. Note 2: Current into an I/O pin is defined as positive. Current out of an I/O pin is defined as negative. Note 3: DC parameters production tested at TA = +25C and guaranteed by design over the full operating temperature range. Note 4: Single-ended data input operation using VBB_ is limited to (VCC - VEE) 3.0V. Note 5: Use VBB_ only for inputs that are on the same device as the VBB_ reference. Note 6: All pins open except VCC and VEE. Note 7: Guaranteed by design and characterization. Limits are set at 6 sigma. Note 8: Measured from the 50% point of the input signal with the 50% point equal to VBB, to the 50% point of the output signal. Note 9: Measured between outputs of the same part at the signal crossing points for a same-edge transition. Note 10: Measured between input-to-output paths of the same part at the signal crossing points for a same-edge transition of the differential input signal. Note 11: Measured between outputs of different parts at the signal crossing points under identical conditions for a same-edge transition. Note 12: Device jitter added to the differential input signal.
Typical Operating Characteristics
(VCC - VEE = 3.3V, VIHD = VCC - 1V, VILD = VCC - 1.5V, outputs loaded with 50 1% to VCC - 2V, fIN = 622MHz, input duty cycle = 50%, input transition time = 125ps (20% to 80%), unless otherwise noted.)
DIFFERENTIAL OUTPUT VOLTAGE (VOH - VOL) vs. FREQUENCY
MAX9389 toc01
SUPPLY CURRENT vs. TEMPERATURE
60.0 57.5 SUPPLY CURRENT (mA) 55.0 52.5 50.0 47.5 45.0 42.5 40.0 -40 -15 10 35 60 85 TEMPERATURE (C) ALL PINS ARE OPEN EXCEPT VCC AND VEE DIFFERENTIAL OUTPUT VOLTAGE (mV)
OUTPUT RISE/FALL TIME vs. TEMPERATURE
MAX9389 toc03
800 700 600 500 400 300 200 0 0.5 1.0 1.5 2.0 2.5
MAX9389 toc02
900
150 140 RISE/FALL TIME (ps) 130 120 110 RISE 100 90 FALL
3.0
-40
-15
10
35
60
85
FREQUENCY (GHz)
TEMPERATURE (C)
4
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Differential 8:1 ECL/PECL Multiplexer with Dual Output Buffers
Typical Operating Characteristics (continued)
(VCC - VEE = 3.3V, VIHD = VCC - 1V, VILD = VCC - 1.5V, outputs loaded with 50 1% to VCC - 2V, fIN = 622MHz, input duty cycle = 50%, input transition time = 125ps (20% to 80%), unless otherwise noted.)
PROPAGATION DELAY vs. HIGH VOLTAGE OF DIFFERENTIAL INPUT (VIHD)
MAX9389 toc04
MAX9389
PROPAGATION DELAY vs. TEMPERATURE
MAX9389 toc05
340
VIHD - VILD = 150mV
350
PROPAGATION DELAY (ps)
308
PROPAGATION DELAY (ps)
324
330
tPHL
310 tPLH 290
292
276
270
260 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3 VIHD (V)
250 -40 -15 10 35 60 85 TEMPERATURE (C)
Pin Description
PIN 1, 8, 22, 26, 29 2 NAME VCC FUNCTION Positive Supply Input. Bypass each VCC to VEE with 0.1F and 0.01F ceramic capacitors. Place the capacitors as close to the device as possible with the smaller value capacitor closest to the device. Reference Output Voltage 2. Connect to the inverting or noninverting data input to provide a reference for single-ended operation. When used, bypass VBB2 to VCC with a 0.01F ceramic capacitor. Otherwise leave open. Reference Output Voltage 1. Connect to the inverting or noninverting data input to provide a reference for single-ended operation. When used, bypass VBB1 to VCC with a 0.01F ceramic capacitor. Otherwise leave open. Noninverting Differential Input 0. Internal 232k to VCC and 180k to VEE. Inverting Differential Input 0. Internal 180k to VCC and 180k to VEE. Noninverting Differential Input 1. Internal 232k to VCC and 180k to VEE. Inverting Differential Input 1. Internal 180k to VCC and 180k to VEE. Noninverting Differential Input 2. Internal 232k to VCC and 180k to VEE. Inverting Differential Input 2. Internal 180k to VCC and 180k to VEE. Noninverting Differential Input 3. Internal 232k to VCC and 180k to VEE. Inverting Differential Input 3. Internal 180k to VCC and 180k to VEE. Noninverting Differential Input 4. Internal 232k to VCC and 180k to VEE. Inverting Differential Input 4. Internal 180k to VCC and 180k to VEE. Noninverting Differential Input 5. Internal 232k to VCC and 180k to VEE. Inverting Differential Input 5. Internal 180k to VCC and 180k to VEE. Negative Supply Input Noninverting Differential Input 6. Internal 232k to VCC and 180k to VEE. Inverting Differential Input 6. Internal 180k to VCC and 180k to VEE.
VBB2
3 4 5 6 7 9 10 11 12 13 14 15 16 17, 32 18 19
VBB1 D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 VEE D6 D6
_______________________________________________________________________________________
5
Differential 8:1 ECL/PECL Multiplexer with Dual Output Buffers MAX9389
Pin Description (continued)
PIN 20 21 23 24 25 27 28 30 31 -- NAME D7 D7 SEL0 SEL1 SEL2 Q1 Q1 Q0 Q0 EP FUNCTION Noninverting Differential Input 7. Internal 232k to VCC and 180k to VEE. Inverting Differential Input 7. Internal 180k to VCC and 180k to VEE. Select Logic Input 0. Internal 165k pulldown to VEE. Select Logic Input 1. Internal 165k pulldown to VEE. Select Logic Input 2. Internal 165k pulldown to VEE. Inverting Output 1. Typically terminate with 50 resistor to VCC - 2V. Noninverting Output 1. Typically terminate with 50 resistor to VCC - 2V. Inverting Output 0. Typically terminate with 50 resistor to VCC - 2V. Noninverting Output 0. Typically terminate with 50 resistor to VCC - 2V. Exposed Pad (QFN Package Only). Connect to VEE.
D_ VIHD - VILD VCC VIHD (MAX) VIHD - VILD VILD (MAX) VBB VIL Q_ VIH Q_ VOH - VOL VCC D_ tPLHD tPHLD
VIHD
VILD
VOH
VOL
VIHD (MIN) VIHD - VILD VEE VILD (MIN) VEE
80% DIFFERENTIAL OUTPUT WAVEFORM 20% Q_ - Q_ tR
VOH - VOL
80% 0V (DIFFERENTIAL)
DIFFERENTIAL INPUT VOLTAGE DEFINITION
SINGLE-ENDED INPUT VOLTAGE DEFINITION
VOH - VOL
20%
tF
Figure 1. Input Definitions
Figure 2. Differential Input-to-Output Propagation Delay Timing Diagram
D_, D1 D_ WHEN D_ = VBB VBB OR VBB D_ WHEN D_ = VBB tPLH1 Q_ VOH - VOL Q_ VOL Q_ tPHL1 VOH Q_ VOH - VOL VIL SEL_ = VIL OR OPEN SELO tPLH2 VBB VIH D_, D1 VIHD - VILD
VIHD
VILD VIH
VIL tPHL2 VOH
VOL
Figure 3. Single-Ended Input-to-Output Propagation Delay Timing Diagram 6
Figure 4. Select Input (SEL0) to Output (Q_, Q_) Delay Timing Diagram
_______________________________________________________________________________________
Differential 8:1 ECL/PECL Multiplexer with Dual Output Buffers MAX9389
D0
D0 Q0
Q0
Q0 tPLHD* D1-D7 tPHLD*
Q0 Q1
Q1 tSKOO tSKOO
D1-D7 Q0
Q0 tPLHD** tSKIO = | tPLHD* - tPLHD** | OR | tPHLD* - tPHLD** | tPHLD**
Figure 5. Output-to-Output Skew (tSKOO) Definition
Figure 6. Input-to-Output Skew (tSKIO) Definition
Detailed Description
The MAX9389 is a fully differential, high-speed, low-jitter 8-to-1 ECL/PECL mux with dual output buffers. The device is designed for clock and data distribution applications, and features extremely low propagation delay (310ps typ) and output-to-output skew (30ps max). Three single-ended select inputs, SEL0, SEL1, and SEL2, control the mux function (see Table 1). The mux select inputs are compatible with ECL/PECL logic, and are internally referenced to the on-chip reference output (VBB1, VBB2), nominally VCC - 1.425V. The select inputs accept signals between VCC and VEE. Internal 165k pulldowns to VEE ensure a low default condition if the select inputs are left open. Leaving SEL0, SEL1, and SEL2 open selects the D0, D0 inputs by default. The differential inputs D_, D_ can be configured to accept a single-ended signal when the unused complementary input is connected to the on-chip reference voltage (VBB1, VBB2). Voltage reference outputs VBB1 and VBB2 provide the reference voltage needed for single-ended operations. A single-ended input of at least VBB_ 100mV or a differential input of at least 100mV switches the outputs to the VOH and VOL levels specified in the DC Electrical Characteristics table. The maximum magnitude of the differential input from D_ to D_ is 3.0V. This limit also applies to the difference between a single-ended input and any reference voltage input.
Table 1. Mux Select Input Truth Table
DATA OUTPUT D0* D1 D2 D3 D4 D5 D6 D7 SEL0 L or open H L or open H L or open H L or open H SEL1 L or open L or open H H L or open L or open H H SEL2 L or open L or open L or open L or open H H H H
*Default output when SEL0, SEL1, and SEL2 are left open.
Single-Ended Operation
The recommended supply voltage for single-ended operation is 3.0V to 3.8V. The differential inputs (D_, D_) can be configured to accept single-ended inputs when operating at supply voltages greater than 2.725V. In single-ended mode operation, the unused complementary input needs to be connected to the on-chip reference voltage, VBB1 or VBB2, as a reference. For example, the differential D_, D_ inputs are converted to a noninverting, single-ended input by connecting VBB1 or VBB2 to D_ and connecting the single-ended input to D_. Similarly, an inverting input is obtained by connecting V BB1 or V BB2 to D_ and connecting the singleended input to D_. The single-ended input can be driven to V CC or V EE or with a single-ended LVPECL/LVECL signal.
_______________________________________________________________________________________
7
Differential 8:1 ECL/PECL Multiplexer with Dual Output Buffers
In single-ended operation, ensure that the supply voltage (VCC -VEE) is greater than 2.725V. The input high minimum level must be at least (VEE + 1.2V) or higher for proper operation. The reference voltage VBB must be at least (VEE + 1.2V) because it becomes the highlevel input when a single-ended input swings below it. The minimum VBB output for the MAX9389 is (VCC 1.525V). Substituting the minimum VBB output for (VBB = VEE + 1.2V) results in a minimum supply (VCC - VEE) of 2.725V. Rounding up to standard supplies gives the recommended single-ended operating supply ranges (VCC - VEE) of 3.0V to 5.5V. When using the VBB reference output, bypass it with a 0.01F ceramic capacitor to VCC. If VBB is not being used, leave it unconnected. The VBB reference can source or sink a total of 0.5mA (shared between VBB1 and VBB2), which is sufficient to drive eight inputs.
MAX9389
Traces
Circuit board trace layout is very important to maintain the signal integrity of high-speed differential signals. Maintaining integrity is accomplished in part by reducing signal reflections and skew, and increasing commonmode noise immunity. Signal reflections are caused by discontinuities in the 50 characteristic impedance of the traces. Avoid discontinuities by maintaining the distance between differential traces, not using sharp corners or using vias. Maintaining distance between the traces also increases common-mode noise immunity. Reducing signal skew is accomplished by matching the electrical length of the differential traces.
Applications Information
Output Termination
Terminate each output with a 50 to VCC - 2V or use an equivalent Thevenin termination. Terminate each Q_ and Q_ output with identical termination for minimal distortion. When a single-ended signal is taken from the differential output, terminate both Q_ and Q_. Ensure that the output current does not exceed the current limits specified in the Absolute Maximum Ratings table. Under all operating conditions, the device's total thermal limits should not be exceeded.
Pin Configurations (continued)
VCC VEE
VCC
Q0
Q1
Q0
Q1
32
31
30
29
28
27
26
25 24 23 22 21
SEL2
TOP VIEW
VCC VBB2 VBB1 D0 D0 D1 D1 VCC
1 2 3 4 5 6 7 8 10 11 12 13 14 15 16
SEL1 SEL0 VCC D7 D7 D6 D6 VEE
MAX9389
20 19 18 17
Supply Bypassing
Bypass each VCC to VEE with high-frequency surfacemount ceramic 0.1F and 0.01F capacitors. For PECL, bypass each VCC to VEE. For ECL, bypass each VEE to VCC. Place the capacitors as close to the device as possible with the 0.01F capacitor closest to the device pins. Use multiple vias when connecting the bypass capacitors to ground. When using the VBB1 or VBB2 reference outputs, bypass each one with a 0.01F ceramic capacitor to VCC. If the VBB1 or VBB2 reference outputs are not used, they can be left open.
9
D3
D4
D5
D3
D2
D2
THIN QFN
NOTE: VEE IS CONNECTED TO THE UNDERSIDE METAL SLUG.
Chip Information
TRANSISTOR COUNT: 716 PROCESS: Bipolar
8
_______________________________________________________________________________________
D4
D5
Differential 8:1 ECL/PECL Multiplexer with Dual Output Buffers
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
32L TQFP, 5x5x01.0.EPS
MAX9389
_______________________________________________________________________________________
9
Differential 8:1 ECL/PECL Multiplexer with Dual Output Buffers MAX9389
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
QFN THIN.EPS
L
REV.
0.15 C A
D2
C L
D
b D2/2
0.10 M C A B
PIN # 1 I.D.
D/2
0.15 C B
k
PIN # 1 I.D. 0.35x45
E/2 E2/2 E (NE-1) X e
C L
E2
k L
DETAIL A
e (ND-1) X e
C L
C L
L
e 0.10 C A 0.08 C
e
C
A1 A3
PROPRIETARY INFORMATION TITLE:
PACKAGE OUTLINE 16, 20, 28, 32L, QFN THIN, 5x5x0.8 mm
APPROVAL DOCUMENT CONTROL NO.
21-0140
C
1 2
COMMON DIMENSIONS
EXPOSED PAD VARIATIONS
NOTES: 1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES. 3. N IS THE TOTAL NUMBER OF TERMINALS. 4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE. 5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm FROM TERMINAL TIP. 6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY. 7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION. 8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. 9. DRAWING CONFORMS TO JEDEC MO220. 10. WARPAGE SHALL NOT EXCEED 0.10 mm.
PROPRIETARY INFORMATION TITLE:
PACKAGE OUTLINE 16, 20, 28, 32L, QFN THIN, 5x5x0.8 mm
APPROVAL DOCUMENT CONTROL NO. REV.
21-0140
C
2 2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
10 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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