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19-3346; Rev 0; 7/04
4A, 20ns, MOSFET Driver
General Description
The MAX5078A/MAX5078B high-speed MOSFET drivers source and sink up to 4A peak current. These devices feature a fast 20ns propagation delay and 20ns rise and fall times while driving a 5000pF capacitive load. Propagation delay time is minimized and matched between the inverting and noninverting inputs. High sourcing/sinking peak currents, low propagation delay, and thermally enhanced packages make the MAX5078A/ MAX5078B ideal for high-frequency and high-power circuits. The MAX5078A/MAX5078B operate from a 4V to 15V single power supply and consume 40A (typ) of supply current when not switching. These devices have an internal logic circuitry that prevents shoot-through during output state changes to minimize the operating current at a high switching frequency. The logic inputs are protected against voltage spikes up to +18V, regardless of the VDD voltage. The MAX5078A has CMOS input logic levels while the MAX5078B has TTL-compatible input logic levels. The MAX5078A/MAX5078B feature both inverting and noninverting inputs for greater flexibility in controlling the MOSFET. They are available in a 6-pin TDFN (3mm x 3mm) package and operate over the automotive temperature range of -40C to +125C. 4V to 15V Single Power Supply 4A Peak Source/Sink Drive Current 20ns (typ) Propagation Delay Matching Delay Between Inverting and Noninverting Inputs VDD / 2 CMOS (MAX5078A)/TTL (MAX5078B) Logic Inputs 0.1 x VDD (CMOS) and 0.3V (TTL) Logic-Input Hysteresis Up to +18V Logic Inputs (Regardless of VDD Voltage) Low Input Capacitance: 2.5pF (typ) 40A (typ) Quiescent Current -40C to +125C Operating Temperature Range 6-Pin TDFN Package
Features
MAX5078
Ordering Information
PART MAX5078AATT MAX5078BATT TEMP RANGE -40C to +125C -40C to +125C PINPACKAGE 6 TDFN-EP* 6 TDFN-EP* TOP MARK AHL AHM
Applications
Power MOSFET Switching Switch-Mode Power Supplies DC-DC Converters Motor Control Power-Supply Modules
*EP = Exposed pad.
Selector Guide
PART MAX5078AATT MAX5078BATT PIN-PACKAGE 6 TDFN-EP 6 TDFN-EP LOGIC INPUT VDD / 2 CMOS TTL
Typical Operating Circuit
4V TO 15V VDD
Pin Configuration
TOP VIEW MAX5078
MAX5078A MAX5078B
IN+ OUT N
IN-
1
6
IN+
GND
2
5
OUT
GND 3 PWM IN INGND
4
VDD
TDFN-EP ________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
4A, 20ns, MOSFET Driver MAX5078
ABSOLUTE MAXIMUM RATINGS
(Voltages referenced to GND.) VDD...............................................................................-0.3V to +18V IN+, IN- ........................................................................-0.3V to +18V OUT .................................................................-0.3V to (VDD + 0.3V) OUT Short-Circuit Duration.......................................................10ms Continuous Source/Sink Current at OUT_ (PD < PDMAX) .....200mA Continuous Power Dissipation (TA = +70C) 6-Pin TDFN-EP (derate 24.4mW/C above +70C)........1951mW Junction-to-Case Thermal Resistance (JC) ..........................2C/W Operating Temperature Range..............................-40C to +125C Storage Temperature Range .................................-65C to +150C Junction Temperature ...........................................................+150C Lead Temperature (soldering, 10s)......................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = 4V to 15V, TA = -40C to +125C, unless otherwise noted. Typical values are at VDD = 15V and TA = +25C.) (Note 1)
PARAMETER POWER SUPPLY VDD Operating Range VDD Undervoltage Lockout VDD Undervoltage Lockout Hysteresis VDD Undervoltage Lockout to Output Delay VDD Supply Current DRIVER OUTPUT (SINK) Driver Output Resistance Pulling Down Peak Output Current (Sinking) Output-Voltage Low Latchup Protection DRIVER OUTPUT (SOURCE) Driver Output Resistance Pulling Up Peak Output Current (Sourcing) VDD = 15V, IOUT = 100mA VDD = 4.5V, IOUT = 100mA TA = +25C TA = +125C TA = +25C TA = +125C 1.5 1.9 2.75 3.75 4 2.1 2.75 4 5.5 A ILUP VDD = 15V, IOUT = -100mA VDD = 4.5V, IOUT = -100mA TA = +25C TA = +125C TA = +25C TA = +125C VDD = 4.5V VDD = 15V 400 1.1 1.5 2.2 3.0 4 0.45 0.24 1.8 2.4 3.3 4.5 A V mA IDD IDD-SW VDD rising IN+ = 0V, IN- = VDD (not switching) VDD = 4V VDD = 15V 0.5 VDD UVLO VDD rising 4 3.00 3.5 200 12 28 40 1.2 55 75 2.2 15 3.85 V V mV s A mA SYMBOL CONDITIONS MIN TYP MAX UNITS
Switching at 250kHz, CL = 0
RON-N
IPK-N
VDD = 15V, CL = 10,000pF IOUT = -100mA
Reverse current IOUT (Note 2)
RON-P
IPK-P
VDD = 15V, CL = 10,000pF
2
_______________________________________________________________________________________
4A, 20ns, MOSFET Driver
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 4V to 15V, TA = -40C to +125C, unless otherwise noted. Typical values are at VDD = 15V and TA = +25C.) (Note 1)
PARAMETER SYMBOL CONDITIONS VDD = 4.5V Output-Voltage High IOUT = 100mA VDD = 15V LOGIC INPUT (Note 3) Logic 1 Input Voltage VIH MAX5078A MAX5078B (Note 4) Logic 0 Input Voltage VIL MAX5078A MAX5078B Logic-Input Hysteresis Logic-Input-Current Leakage Input Capacitance CIN CL = 1000pF OUT Rise Time tR CL = 5000pF CL = 10,000pF CL = 1000pF OUT Fall Time Turn-On Delay Time Turn-Off Delay Time tF tD-ON tD-OFF CL = 5000pF CL = 10,000pF CL = 10,000pF (Note 2) CL = 10,000pF (Note 2) CL = 1000pF OUT Rise Time tR CL = 5000pF CL = 10,000pF CL = 1000pF OUT Fall Time Turn-On Delay Time Turn-Off Delay Time tF tD-ON tD-OFF CL = 5000pF CL = 10,000pF CL = 10,000pF (Note 2) CL = 10,000pF (Note 2) 18 18 10 10 VHYS MAX5078A MAX5078B IN+ = IN- = 0V or VDD -1 0.1 x VDD 0.3 +0.1 2.5 4 18 32 4 15 26 20 20 7 37 85 7 30 75 35 35 70 70 ns ns ns ns 34 34 ns ns ns ns +1 A pF 0.7 x VDD 2.1 0.3 x VDD 0.8 V V V MIN VDD 0.55 V VDD 0.275 TYP MAX UNITS
MAX5078
SWITCHING CHARACTERISTICS FOR VDD = 15V (Figure 1)
SWITCHING CHARACTERISTICS FOR VDD = 4.5V (Figure 1)
_______________________________________________________________________________________
3
4A, 20ns, MOSFET Driver MAX5078
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 4V to 15V, TA = -40C to +125C, unless otherwise noted. Typical values are at VDD = 15V and TA = +25C.) (Note 1)
PARAMETER MATCHING CHARACTERISTICS Mismatch Propagation Delays from Inverting and Noninverting Inputs to Output tON-OFF VDD = 15V, CL = 10,000pF VDD = 4.5V, CL = 10,000pF 2 ns 4 SYMBOL CONDITIONS MIN TYP MAX UNITS
Note 1: Note 2: Note 3: Note 4:
All devices are 100% tested at TA = +25C. Specifications over -40C to +125C are guaranteed by design. Limits are guaranteed by design, not production tested. The logic-input thresholds are tested at VDD = 4V and VDD = 15V. TTL compatible with reduced noise immunity.
Typical Operating Characteristics
(TA = +25C, unless otherwise noted.)
RISE TIME vs. SUPPLY VOLTAGE (CL = 5000pF)
MAX5078 toc01
FALL TIME vs. SUPPLY VOLTAGE (CL = 5000pF)
MAX5078 toc02
PROPAGATION DELAY TIME, LOW-TO-HIGH vs. SUPPLY VOLTAGE (CL = 5000pF)
TA = +125C
MAX5078 toc03
60 50 TA = +125C RISE TIME (ns) 40 30 20 10 TA = -40C 0 4 6 8 10 12 14 TA = +25C
60 50 TA = +125C FALL TIME (ns) 40 30 20 10 TA = -40C 0 TA = +25C
60 50 PROPAGATION DELAY (ns) 40 TA = +25C 30 20 10 0 TA = -40C
16
4
6
8
10
12
14
16
4
6
8
10
12
14
16
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
PROPAGATION DELAY TIME, HIGH-TO-LOW vs. SUPPLY VOLTAGE (CL = 5000pF)
MAX5078 toc04
IDD-SW SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX5078 toc05
SUPPLY CURRENT vs. SUPPLY VOLTAGE
90 80 SUPPLY CURRENT (mA) 70 60 50 40 30 20 10 0 100kHz 50kHz 1MHz 500kHz DUTY CYCLE = 50% VDD = 15V, CL = 4700pF
MAX5078 toc06
60 50 PROPAGATION DELAY (ns) 40 30 20 10 0 4 6 8 10 12 14 TA = -40C TA = +25C TA = +125C
6 IDD-SW SUPPLY CURRENT (mA) 5 4 3 2 1 0
100
DUTY CYCLE = 50% VDD = 15V, CL = 0
1MHz 500kHz
100kHz
50kHz
16
4
6
8
10
12
14
16
4
6
8
10
12
14
16
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
4
_______________________________________________________________________________________
4A, 20ns, MOSFET Driver
Typical Operating Characteristics (continued)
(TA = +25C, unless otherwise noted.)
INPUT THRESHOLD VOLTAGE vs. SUPPLY VOLTAGE
MAX5078 toc07
MAX5078
INPUT THRESHOLD VOLTAGE vs. SUPPLY VOLTAGE
MAX5078 toc08
SUPPLY CURRENT vs. LOGIC-INPUT VOLTAGE (INPUT LOW-TO-HIGH)
MAX5078B (TTL INPUT) VDD = 15V 400 SUPPLY CURRENT (A)
MAX5078 toc09
10 9 INPUT THRESHOLD VOLTAGE (V) 8 7 6 5 4 3 2 1 0 4 6 8 10 12 14 VIN FALLING VIN RISING MAX5078A (CMOS INPUT)
3.0 INPUT THRESHOLD VOLTAGE (V) 2.5 2.0 1.5 1.0
MAX5078B (TTL INPUT) VIN RISING
500
300
200
VIN FALLING 0.5 0
100
0 4 6 8 10 12 14 16 0 2 4 6 8 10 12 14 16 SUPPLY VOLTAGE (V) LOGIC-INPUT VOLTAGE (V)
16
SUPPLY VOLTAGE (V)
SUPPLY CURRENT vs. LOGIC-INPUT VOLTAGE (INPUT HIGH-TO-LOW)
MAX5078 toc10
SUPPLY CURRENT vs. LOGIC-INPUT VOLTAGE (INPUT LOW-TO-HIGH)
MAX5078 toc11
SUPPLY CURRENT vs. LOGIC-INPUT VOLTAGE (INPUT HIGH-TO-LOW)
MAX5078A (CMOS INPUT) VDD = 15V 4 SUPPLY CURRENT (mA)
MAX5078 toc12
500 MAX5078B (TTL INPUT) VDD = 15V 400 SUPPLY CURRENT (A)
5 MAX5078A (CMOS INPUT) VDD = 15V 4 SUPPLY CURRENT (mA)
5
300
3
3
200
2
2
100
1
1
0 0 2 4 6 8 10 12 14 16 LOGIC-INPUT VOLTAGE (V)
0 0 2 4 6 8 10 12 14 16 LOGIC-INPUT VOLTAGE (V)
0 0 2 4 6 8 10 12 14 16 LOGIC-INPUT VOLTAGE (V)
DELAY MISMATCH BETWEEN IN+ AND IN- TO OUT vs. TEMPERATURE
MAX5078 toc13
DELAY MISMATCH BETWEEN IN+ AND IN- TO OUT vs. TEMPERATURE
MAX5078 toc14
LOGIC-INPUT VOLTAGE vs. OUTPUT VOLTAGE (VDD = 4V, CL = 5000pF)
MAX5078 toc15
6 OUTPUT FALLING 4 DELAY MISMATCH (ns) 2 0 -2 -4 -6 -50 -25 0 25 50 75 100 OUTPUT RISING
6 4 DELAY MISMATCH (ns) 2 0 -2 -4 -6 OUTPUT FALLING OUTPUT RISING
IN2V/div
OUT 2V/div
MAX5078A (CMOS INPUT) VDD = 4.5V, CL = 10,000pF 125
MAX5078A (CMOS INPUT) VDD = 15V, CL = 10,000pF -50 -25 0 25 50 75 100 125 20ns/div
IN+ = VDD
TEMPERATURE (C)
TEMPERATURE (C)
_______________________________________________________________________________________
5
4A, 20ns, MOSFET Driver MAX5078
Typical Operating Characteristics (continued)
(TA = +25C, unless otherwise noted.)
LOGIC-INPUT VOLTAGE vs. OUTPUT VOLTAGE (VDD = 4V, CL = 10,000pF)
MAX5078 toc16
LOGIC-INPUT VOLTAGE vs. OUTPUT VOLTAGE (VDD = 4V, CL = 5000pF)
MAX5078 toc17
MAX5078B (TTL INPUT) IN2V/div
MAX5078B (TTL INPUT) IN2V/div
OUT 2V/div
OUT 2V/div
IN+ = VDD 40ns/div 20ns/div
IN+ = VDD
LOGIC-INPUT VOLTAGE vs. OUTPUT VOLTAGE (VDD = 4V, CL = 10,000pF)
MAX5078 toc18
LOGIC-INPUT VOLTAGE vs. OUTPUT VOLTAGE (VDD = 15V, CL = 5000pF)
MAX5078 toc19
MAX5078B (TTL INPUT) IN2V/div IN2V/div
OUT 2V/div IN+ = VDD 40ns/div MAX5078B (TTL INPUT) 20ns/div IN+ = VDD
OUT 5V/div
LOGIC-INPUT VOLTAGE vs. OUTPUT VOLTAGE (VDD = 15V, CL = 10,000pF)
MAX5078 toc20
IN2V/div
OUT 5V/div
MAX5078B (TTL INPUT) 40ns/div
IN+ = VDD
6
_______________________________________________________________________________________
4A, 20ns, MOSFET Driver
Typical Operating Characteristics (continued)
(TA = +25C, unless otherwise noted.)
MAX5078
LOGIC-INPUT VOLTAGE vs. OUTPUT VOLTAGE (VDD = 15V, CL = 5000pF)
MAX5078 toc21
LOGIC-INPUT VOLTAGE vs. OUTPUT VOLTAGE (VDD = 15V, CL = 10,000pF)
MAX5078 toc22
MAX5078B (TTL INPUT) IN2V/div
MAX5078B (TTL INPUT) IN2V/div
OUT 5V/div
OUT 5V/div
IN+ = VDD 20ns/div 40ns/div
IN+ = VDD
VDD vs. OUTPUT VOLTAGE
MAX5078B (TTL INPUT)
VDD vs. OUTPUT VOLTAGE
VDD 5V/div MAX5078B (TTL INPUT)
MAX5078 toc23
MAX5078 toc24
IN+ = 15V IN- = GND CL = 10,000pF
OUT 5V/div
VDD 5V/div
IN+ = 15V IN- = GND CL = 10,000pF 2ms/div 2ms/div
OUT 5V/div
_______________________________________________________________________________________
7
4A, 20ns, MOSFET Driver MAX5078
Pin Description
PIN 1 2, 3 4 5 6 -- NAME INGND VDD OUT IN+ EP Ground Power Supply. Bypass to GND with one or more 0.1F ceramic capacitors. Driver Output. Sources or sinks current to turn the external MOSFET on or off. Noninverting Logic-Input Terminal. Connect to VDD when not used. Exposed Pad. Internally connected to GND. Do not use the exposed pad as the only electrical ground connection. FUNCTION Inverting Logic-Input Terminal. Connect to GND when not used.
Detailed Description
VDD Undervoltage Lockout (UVLO)
The MAX5078A/MAX5078B have internal undervoltage lockout (UVLO) for VDD. When VDD is below the UVLO threshold, OUT is pulled low independent of the state of the inputs. The undervoltage lockout is typically 3.5V with 200mV typical hysteresis to avoid chattering. When VDD rises above the UVLO threshold, the output goes high or low depending upon the logic-input levels. Bypass VDD using a low-ESR ceramic capacitor for proper operation (see the Applications Information section).
Driver Output
The MAX5078A/MAX5078B have low RDS(ON) p-channel and n-channel devices (totem pole) in the output stage for the fast turn-on/turn-off, high-gate-charge switching MOSFETs. The peak source or sink current is typically 4A. The output voltage (VOUT) is approximately equal to VDD when in high state and is ground when in low state. The driver RDS(ON) is lower at higher VDD resulting in higher source-/sink-current capability and faster switching speeds. The propagation delays from the noninverting and inverting logic inputs to OUT are matched to 2ns typically. The break-before-make logic avoids any crossconduction between the internal p- and n-channel devices, and eliminates shoot-through, thus reducing the quiescent supply current.
Logic Inputs
The MAX5078A has CMOS logic inputs while the MAX5078B has TTL-compatible logic inputs. The logic inputs are protected against the voltage spikes up to 18V, regardless of the VDD voltage. The TTL and CMOS logic inputs have 300mV and 0.1 x V DD hysteresis, respectively, to avoid double pulsing during transition. The low 2.5pF input capacitance reduces loading and increases switching speed. The logic inputs are high impedance and must not be left floating. If the inputs are left open, OUT can go to an undefined state as soon as VDD rises above the UVLO threshold. Therefore, the PWM output from the controller must assume proper state when powering up the device. The MAX5078A/MAX5078B have two logic inputs, providing greater flexibility in controlling the MOSFET. Use IN+ for noninverting logic and IN- for inverting logic operation. Connect IN+ to V DD and IN- to GND, if not used. Alternatively, the unused input can be used as an ON/OFF function. Use IN+ for active-low shutdown logic and IN- for active-high shutdown logic (see Figure 3). See Table 1 for all possible input combinations.
Applications Information
RLC Series Circuit
The driver's RDS(ON) (RON), internal bond/lead inductance (LP), trace inductance (LS), gate inductance (LG), and gate capacitance (C G ) form a series RLC circuit with a second-order characteristic equation. The series RLC circuit has an undamped natural frequency (0) and a damping ratio () where: 0 = 1 (LP + LS + LG ) x CG RON 2x (LP + LS + LG ) CG
=
The damping ratio needs to be greater than 0.5 (ideally 1) to avoid ringing. Add a small resistor (RGATE) in series with the gate when driving a very low gatecharge MOSFET, or when the driver is placed away from the MOSFET.
8
_______________________________________________________________________________________
4A, 20ns, MOSFET Driver MAX5078
VIH VIL
IN+
VDD
MAX5078A MAX5078B
90% OUT 10% tD-OFF1 tF INVIH VIL tD-OFF2 RISING MISMATCH = tD-ON2 - tD-ON1 FALLING MISMATCH = tD-OFF2 - tD-OFF1 tD-ON2 tD-ON1 tR
INBREAKBEFOREMAKE CONTROL IN+
P OUT N
GND
Figure 1. Timing Diagram
Figure 2. MAX5054 Simplified Diagram (1 Driver)
Use the following equation to calculate the series resistor: (LP + LS + LG ) - RON CG
RGATE
The current required to charge and discharge the internal nodes is frequency dependent (see the I DD-SW Supply Current vs. Supply Voltage graph in the Typical Operating Characteristics). The power dissipation (PQ) due to the quiescent switching supply current (IDD-SW) can be calculated as: PQ = VDD x IDD-SW For capacitive loads, use the following equation to estimate the power dissipation: PCLOAD = CLOAD x (VDD)2 x fSW where CLOAD is the capacitive load, VDD is the supply voltage, and fSW is the switching frequency. Calculate the total power dissipation (PT) as follows: PT = PQ + PCLOAD Use the following equations to estimate the MAX5078A/ MA5078B total power dissipation when driving a groundreferenced resistive load: PT = PQ + PRLOAD PRLOAD = D x RON(MAX) x ILOAD2 where D is the fraction of the period the MAX5078A/ MA5078B's output pulls high, RON(MAX) is the maximum on-resistance of the device with the output high, and I LOAD is the output load current of the MAX5078A/ MAX5078B.
LP can be approximated as 2nH for the TDFN package. LS is on the order of 20nH/in. Verify LG with the MOSFET vendor.
Supply Bypassing and Grounding
Pay extra attention to bypassing and grounding the MAX5078A/MAX5078B. Peak supply and output currents may exceed 4A when driving large external capacitive loads. Supply voltage drops and ground shifts create negative feedback for inverters and may degrade the delay and transition times. Ground shifts due to poor device grounding may also disturb other circuits sharing the same AC ground return path. Any series inductance in the VDD, OUT, and/or GND paths can cause oscillations due to the very high di/dt when switching the MAX5078A/MAX5078B with any capacitive load. Place one or more 0.1F ceramic capacitors in parallel as close to the device as possible to bypass VDD to GND. Use a ground plane to minimize ground return resistance and series inductance. Place the external MOSFET as close as possible to the MAX5078A/MAX5078B to further minimize board inductance and AC path impedance.
Power Dissipation
Power dissipation of the MAX5078A/MAX5078B consists of three components: caused by the quiescent current, capacitive charge/discharge of internal nodes, and the output current (either capacitive or resistive load). Maintain the sum of these components below the maximum power dissipation limit.
Layout Information
The MAX5078A/MAX5078B MOSFET drivers source and sink large currents to create very fast rising and falling edges at the gate of the switching MOSFET. The high di/dt can cause unacceptable ringing if the trace lengths and impedances are not well controlled.
_______________________________________________________________________________________
9
4A, 20ns, MOSFET Driver MAX5078
Table 1. MAX5078 Truth Table
IN+ Low Low High High INLow High Low High OUT Low Low High Low
OFF ON INGND PWM INPUT IN+ VDD
MAX5078
OUT
Use the following PC board layout guidelines when designing with the MAX5078A/MAX5078B: * Place one or more 0.1F decoupling ceramic capacitors from VDD to GND as close to the device as possible. Connect VDD and GND to large copper areas. Place one bulk capacitor of 10F (min) on the PC board with a low resistance path to the VDD input and GND of the MAX5078A/MAX5078B. * Two AC current loops form between the device and the gate of the driven MOSFET. The MOSFET looks like a large capacitance from gate to source when the gate pulls low. The active current loop is from the MOSFET gate to OUT of the MAX5078A/MAX5078B, to GND of the MAX5078A/MAX5078B, and to the source of the MOSFET. When the gate of the MOSFET pulls high, the active current is from the VDD terminal of the decoupling capacitor, to V DD of the MAX5078A/MAX5078B, to OUT of the MAX5078A/ MAX5078B, to the MOSFET gate, to the MOSFET source, and to the negative terminal of the decoupling capacitor. Both charging current and discharging current loops are important. Minimize the physical distance and the impedance in these AC current paths. * * Keep the device as close to the MOSFET as possible. In a multilayer PC board, the inner layers should consist of a GND plane containing the discharging and charging current loops. Pay extra attention to the ground loop and use a low-impedance source when using a TTL logicinput device. Fast fall time at OUT may corrupt the input during transition.
Figure 3. Unused Input as an ON/OFF Function
Additional Application Circuits
VS
VDD VDD
MAX5078A MAX5078B
IN+ OUT N
IN-
GND
Figure 4. Noninverting Application
VS
*
4V TO 15V VDD
Exposed Pad
The TDFN-EP package has an exposed pad on the bottom of its package. This pad is internally connected to GND. For the best thermal conductivity, solder the exposed pad to the ground plane in order to dissipate 1.9W. Do not use the ground-connected pad as the only electrical ground connection or ground return. Use GND (pins 2 and 3) as the primary electrical ground connection.
IN+ FROM PWM CONTROLLER (BOOST) IN-
MAX5078A MAX5078B
OUT N
VOUT
GND
Figure 5. Boost Converter 10 ______________________________________________________________________________________
4A, 20ns, MOSFET Driver
4V TO 15V
Chip Information
VDD IN+
MAX5078
TRANSISTOR COUNT: 258 PROCESS: CMOS
MAX5078A MAX5078B OUT
P
INFROM PWM CONTROLLER (BOOST) GND
VDD IN+ VOUT
MAX5078A MAX5078B OUT
N
INGND
Figure 6. MAX5078A/MAX5078B In High-Power Synchronous Buck Converter
VIN VOUT
4V TO 15V VDD 4V TO 15V VDD OUT VDD
MAX5078
PWM IN IN+
MAX5078
OUT INGND OUT
MAX5078
IN+
IN+ INGND
GND
IN-
SIGNAL FROM PRIMARY
Figure 7. Forward Converter with Secondary-Side Synchronous Rectification ______________________________________________________________________________________ 11
4A, 20ns, MOSFET Driver MAX5078
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)
6, 8, &10L, DFN THIN.EPS
C L
D
N
PIN 1 INDEX AREA
E
DETAIL A
E2
C L
L A e e
L
PACKAGE OUTLINE, 6, 8, 10 & 14L, TDFN, EXPOSED PAD, 3x3x0.80 mm
NUMBER OF LEADS SHOWN ARE FOR REFERENCE ONLY
21-0137
F
1
2
COMMON DIMENSIONS SYMBOL A D E A1 L k A2 MIN. 0.70 2.90 2.90 0.00 MAX. 0.80 3.10 3.10 0.05
0.40 0.20 0.25 MIN. 0.20 REF.
PACKAGE VARIATIONS PKG. CODE T633-1 T833-1 T1033-1 T1433-1 T1433-2 N 6 8 10 14 14 D2 1.500.10 1.500.10 1.500.10 1.700.10 1.700.10 E2 2.300.10 2.300.10 2.300.10 2.300.10 2.300.10 e 0.95 BSC 0.65 BSC 0.50 BSC 0.40 BSC 0.40 BSC JEDEC SPEC MO229 / WEEA MO229 / WEEC MO229 / WEED-3 ------b 0.400.05 0.300.05 0.250.05 0.200.03 0.200.03 [(N/2)-1] x e 1.90 REF 1.95 REF 2.00 REF 2.40 REF 2.40 REF
PACKAGE OUTLINE, 6, 8, 10 & 14L, TDFN, EXPOSED PAD, 3x3x0.80 mm
21-0137
F
2
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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