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ispLSI 2032/A
In-System Programmable High Density PLD Features
* ENHANCEMENTS -- ispLSI 2032A is Fully Form and Function Compatible to the ispLSI 2032, with Identical Timing Specifcations and Packaging -- ispLSI 2032A is Built on an Advanced 0.35 Micron E2CMOS(R) Technology * HIGH DENSITY PROGRAMMABLE LOGIC
Output Routing Pool (ORP)
(R)
Functional Block Diagram
A0
1000 PLD Gates 32 I/O Pins, Two Dedicated Inputs 32 Registers High Speed Global Interconnect Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. -- Small Logic Block Size for Random Logic * HIGH PERFORMANCE E2CMOS(R) TECHNOLOGY -- -- -- -- -- -- --
-- -- -- -- --
Input Bus
A2
GLB
Logic Array
DQ
DQ
A5
DQ
fmax = 180 MHz Maximum Operating Frequency tpd = 5.0 ns Propagation Delay
TTL Compatible Inputs and Outputs Electrically Erasable and Reprogrammable Non-Volatile 100% Tested at Time of Manufacture Unused Product Term Shutdown Saves Power
N
EW
A3
A4
0139Bisp/2000
* IN-SYSTEM PROGRAMMABLE
Copyright (c) 2002 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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-- Complete Programmable Device Can Combine Glue Logic and Structured Designs -- Enhanced Pin Locking Capability -- Three Dedicated Clock Input Pins -- Synchronous and Asynchronous Clocks -- Programmable Output Slew Rate Control to Minimize Switching Noise -- Flexible Pin Placement -- Optimized Global Routing Pool Provides Global Interconnectivity
LS
I2
* OFFERS THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FIELD PROGRAMMABLE GATE ARRAYS
03
2E
-- In-System Programmable (ISPTM) 5V Only -- Increased Manufacturing Yields, Reduced Time-toMarket and Improved Product Quality -- Reprogram Soldered Devices for Faster Prototyping
is p
FO
The ispLSI 2032 and 2032A are High Density Programmable Logic Devices. The devices contain 32 Registers, 32 Universal I/O pins, two Dedicated Input Pins, three Dedicated Clock Input Pins, one dedicated Global OE input pin and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 2032 and 2032A feature 5V insystem programmability and in-system diagnostic capabilities. The ispLSI 2032 and 2032A offer nonvolatile reprogrammability of the logic, as well as the interconnect to provide truly reconfigurable systems. The basic unit of logic on these devices is the Generic Logic Block (GLB). The GLBs are labeled A0, A1 .. A7 (Figure 1). There are a total of eight GLBs in the ispLSI 2032 and 2032A devices. Each GLB is made up of four macrocells. Each GLB has 18 inputs, a programmable AND/OR/Exclusive OR array, and four outputs which can be configured to be either combinatorial or registered. Inputs to the GLB come from the GRP and dedicated inputs. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any GLB on the device.
R
Description
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
January 2002
2032_10
1
Input Bus
A1
DQ
A6
Output Routing Pool (ORP)
Global Routing Pool (GRP)
D ES IG N
A7
S
Specifications ispLSI 2032/A
Functional Block Diagram
Figure 1. ispLSI 2032/A Functional Block Diagram
GOE 0
Output Routing Pool (ORP)
Output Routing Pool (ORP)
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 SDI/IN 0 SDO/IN 1
A0
A7
A1
Input Bus
EW
Input Bus
Global Routing Pool (GRP)
A6
A2
A5
N
A3
R
A4
FO
ispEN
2E
MODE
Notes: *Y1 and RESET are multiplexed on the same pin
03
Y0 *Y1/RESET SCLK/Y2
0139B(1)isp/2000
Eight GLBs, 32 I/O cells, two dedicated inputs and two ORPs are connected together to make a Megablock (Figure 1). The outputs of the eight GLBs are connected to a set of 32 universal I/O cells by the ORP. Each ispLSI 2032 and 2032A device contains one Megablock. The GRP has as its inputs, the outputs from all of the GLBs and all of the inputs from the bi-directional I/O cells. All of these signals are made available to the inputs of the
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The devices also have 32 I/O cells, each of which is directly connected to an I/O pin. Each I/O cell can be individually programmed to be a combinatorial input, output or bi-directional I/O pin with 3-state control. The signal levels are TTL compatible voltages and the output drivers can source 4 mA or sink 8 mA. Each output can be programmed independently for fast or slow output slew rate to minimize overall output switching noise.
I2
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GLBs. Delays through the GRP have been equalized to minimize timing skew. Clocks in the ispLSI 2032 and 2032A devices are selected using the dedicated clock pins. Three dedicated clock pins (Y0, Y1, Y2) or an asynchronous clock can be selected on a GLB basis. The asynchronous or Product Term clock can be generated in any GLB for its own clock.
is
2
CLK 0 CLK 1 CLK 2
D ES IG N
I/O 31 I/O 30 I/O 29 I/O 28 I/O 27 I/O 26 I/O 25 I/O 24 I/O 23 I/O 22 I/O 21 I/O 20 I/O 19 I/O 18 I/O 17 I/O 16
S
Specifications ispLSI 2032/A
Absolute Maximum Ratings 1
Supply Voltage Vcc ...................................-0.5 to +7.0V Input Voltage Applied ........................ -2.5 to VCC +1.0V Off-State Output Voltage Applied ..... -2.5 to VCC +1.0V
Max. Junction Temp. (TJ) with Power Applied ... 150C
1. Stresses above those listed under the "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications).
SYMBOL
PARAMETER Supply Voltage Input Low Voltage Input High Voltage Commercial Industrial
EW
DC Recommended Operating Condition
D ES IG N
MIN. 4.75 4.5 0 2.0 MAX. 5.25 5.5 0.8 Vcc+1
Case Temp. with Power Applied .............. -55 to 125C
VCC VIL VIH
N
TA = 0C to + 70C
TA = -40C to + 85C
R
FO
Capacitance (TA=25C, f=1.0 MHz)
SYMBOL
03
2E
PARAMETER Dedicated Input Capacitance
TYPICAL 6 7 10
UNITS pf pf pf
TEST CONDITIONS VCC = 5.0V, VIN = 2.0V VCC = 5.0V, VI/O = 2.0V VCC = 5.0V, VY = 2.0V
Table 2-0006/2032
is
Data Retention Specifications
Data Retention
SE
PARAMETER
pL S
C1 C2 C3
I/O Capacitance
Clock Capacitance
I2
MINIMUM 20 10000
MAXIMUM - -
UNITS Years Cycles
Table 2-0008A-isp
Erase/Reprogram Cycles
U
3
S
UNITS V V V V
Table 2 - 0005/2032
Storage Temperature ................................ -65 to 150C
Specifications ispLSI 2032/A
Switching Test Conditions
Input Pulse Levels Input Rise and Fall Time 10% to 90% Input Timing Reference Levels Output Timing Reference Levels Output Load 3-state levels are measured 0.5V from steady-state active level. GND to 3.0V -135, -150, -180 -80, -110 1.5V 1.5V See Figure 2
Table 2-0003/2032
Figure 2. Test Load
+ 5V R1 Device Output R2 C L* Test Point
1.5 ns 3 ns
Output Load Conditions (see Figure 2)
TEST CONDITION A B Active High Active Low Active High to Z at VOH -0.5V Active Low to Z at VOL +0.5V R1 470 470 470 R2 390 390 390 390 390 CL 35pF 35pF 35pF 5pF 5pF
Table 2 - 0004A
*CL includes Test Fixture and Probe Capacitance.
0213A
C
DC Electrical Characteristics
SYMBOL PARAMETER Output Low Voltage Output High Voltage Input or I/O Low Leakage Current
Over Recommended Operating Conditions
FO
R
N
EW
I/O Active Pull-Up Current Output Short Circuit Current Operating Power Supply Current
pL S
VOL VOH IIL IIH IIL-isp IIL-PU IOS1 ICC2, 4
2E
CONDITION
IOL= 8 mA
D ES IG N
MIN. - 2.4 - - - - - - - - TYP. - - - - - - - 60 40 40
3
MAX. UNITS 0.4 - -10 10 -150 -150 -200 - - - V V A A A A mA mA mA mA
Input or I/O High Leakage Current 3.5V VIN VCC ispEN Input Low Leakage Current 0V VIN VIL 0V VIN VIL VCC = 5V, VOUT = 0.5V -180, -150 VIL = 0.0V, VIH = 3.0V Comm. Others fTOGGLE = 1 MHz Industrial
is
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03
IOH = -4 mA 0V VIN VIL (Max.)
1. One output at a time for a maximum duration of one second. VOUT = 0.5V was selected to avoid test problems by tester ground degradation. Characterized but not 100% tested. 2. Measured using two 16-bit counters. 3. Typical values are at VCC = 5V and TA= 25C. 4. Maximum I CC varies widely with specific device configuration and operating frequency. Refer to the Power Consumption section of this data sheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to estimate maximum I CC .
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4
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Table 2-0007/2032
Specifications ispLSI 2032/A
External Timing Parameters
Over Recommended Operating Conditions
PARAMETER TEST #2 COND. A A A - - - A - - - - A - B C B C - -
4
DESCRIPTION1
-180 - - 180 125 200 3.0 - 0.0 4.0 - 0.0 - - - - - 2.5 2.5 4.0 5.0 7.5 - - - - - - - - - -
-150 5.5 8.0 - - - - -
-135 7.5 10.0 - - -
MIN. MAX. MIN. MAX. MIN. MAX.
UNITS ns ns MHz MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns
2E
tpd1 tpd2 fmax fmax (Ext.) fmax (Tog.) tsu1 tco1 th1 tsu2 tco2 th2 tr1 trw1 tptoeen tptoedis tgoeen tgoedis twh twl
1. 2. 3. 4.
1 Data Prop. Delay, 4PT Bypass, ORP Bypass 2 Data Prop. Delay 3 Clk Frequency with Internal Feedback 3 4 Clk Frequency with Ext. Feedback 5 Clk Frequency, Max. Toggle 6 GLB Reg Setup Time before Clk, 4 PT Bypass 7 GLB Reg. Clk to Output Delay, ORP Bypass 8 GLB Reg. Hold Time after Clk, 4 PT Bypass 9 GLB Reg. Setup Time before Clk 10 GLB Reg. Clk to Output Delay 11 GLB Reg. Hold Time after Clk 12 Ext. Reset Pin to Output Delay 13 Ext. Reset Pulse Duration 14 Input to Output Enable 15 Input to Output Disable 16 Global OE Output Enable 17 Global OE Output Disable
154 111 167 3.0 -
137 100 167 4.0 - 0.0 5.5 - 0.0 - 5.0 - - - - 3.0 3.0
( tsu21+ tco1)
4.0
4.5 7.0
EW
N
10.0 10.0 5.0 5.0 - -
R
FO
18 Ext. Synchronous Clk Pulse Duration, High 19 Ext. Synchronous Clk Pulse Duration, Low
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I2
03
Unless noted otherwise, all parameters use the GRP, 20 PTXOR path, ORP and Y0 clock. Refer to Timing Model in this data sheet for further details. Standard 16-bit counter using GRP feedback. Reference Switching Test Conditions section.
5
D ES IG N
- - 4.5 - - - 8.0 - 11.0 11.0 5.0 5.0 - - 4.5 - - 0.0 - 4.5 5.0 5.5 - 10.0 - 12.0 12.0 6.0 6.0 - - 0.0 - 4.5 - - - - 3.0 3.0
Table 2-0030B-180/2032
S
Specifications ispLSI 2032/A
External Timing Parameters
Over Recommended Operating Conditions
PARAMETER TEST #2 COND. A A A - - - A - - - - A - B C B C - - 1 2 3 4 5 6 7 8 9
4
DESCRIPTION1 Data Propagation Delay, 4PT Bypass, ORP Bypass Data Propagation Delay Clock Frequency with Internal Feedback Clock Frequency, Max. Toggle GLB Reg. Setup Time before Clock, 4 PT Bypass GLB Reg. Clock to Output Delay, ORP Bypass GLB Reg. Hold Time after Clock, 4 PT Bypass GLB Reg. Setup Time before Clock
3 1 tsu2 + tco1
-110 - - 111 10.0 13.0 - - - - -
-80 15.0 18.5 - -
MIN. MAX. MIN. MAX.
UNITS ns ns MHz MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns
2E
tpd1 tpd2 fmax fmax (Ext.) fmax (Tog.) tsu1 tco1 th1 tsu2 tco2 th2 tr1 trw1 tptoeen tptoedis tgoeen tgoedis twh twl
1. 2. 3. 4.
84.0 57.0 83.0 7.5 - 0.0 9.5 - 0.0 - 10.0 - - - - 6.0 6.0
10 GLB Reg. Clock to Output Delay 11 GLB Reg. Hold Time after Clock 12 Ext. Reset Pin to Output Delay 13 Ext. Reset Pulse Duration 14 Input to Output Enable 15 Input to Output Disable 16 Global OE Output Enable 17 Global OE Output Disable
EW
N
R
FO
18 External Synchronous Clock Pulse Duration, High 19 External Synchronous Clock Pulse Duration, Low
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I2
03
Unless noted otherwise, all parameters use the GRP, 20 PTXOR path, ORP and Y0 clock. Refer to Timing Model in this data sheet for further details. Standard 16-bit counter using GRP feedback. Reference Switching Test Conditions section.
6
D ES IG N
77.0 125 5.5 - - - - 5.5 - - - 13.5 - 14.5 14.5 7.0 7.0 - - 8.0 - - 0.0 - 7.5 6.5 9.5 - 19.5 - 24.0 24.0 12.0 12.0 - - 0.0 - 6.5 - - - - 4.0 4.0
Clock Frequency with External Feedback (
)
Table 2-0030B-110/2032
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Specifications ispLSI 2032/A
Internal Timing Parameters1
Over Recommended Operating Conditions
PARAMETER Inputs 21 Dedicated Input Delay 22 GRP Delay 23 4 Product Term Bypass Path Delay (Combinatorial) 24 4 Product Term Bypass Path Delay (Registered) 25 1 Product Term/XOR Path Delay 26 20 Product Term/XOR Path Delay 27 XOR Adjacent Path Delay 3 28 GLB Register Bypass Delay 29 GLB Register Setup Time before Clock 30 GLB Register Hold Time after Clock 31 GLB Register Clock to Output Delay 32 GLB Register Reset to Output Delay - - - - - - - - 1.1 0.7 2.3 3.1 3.6 4.1 4.8 0.2 - - 0.7 1.0 2.8 5.9 3.8 0.7 0.2 1.2 10.0 2.8 2.8 2.2 1.9 1.9 4.1 - - 1.3 0.7 - - #
2
DESCRIPTION
-180
-150
-135
MIN. MAX. MIN. MAX. MIN. MAX. - 0.6 - 0.6 - 1.1 2.4
UNITS
GRP
tgrp
GLB
D ES IG N
1.3 - 2.6 3.1 4.3 4.6 5.0 0.0 - - 0.8 1.2 2.9 6.9 4.1 0.8 0.3 1.3 10.0 2.8 2.8 2.2 2.1 2.1 4.7 - 3.6 - - 3.6 - - 5.0 - - 5.1 - - 0.7 1.8 - - - - 2.5 - - - - - - - 2.1 2.1 - - - 0.3 3.0 - - - - 2.9 - - - - - - - 2.3 2.3 - 5.6 0.0 - - 0.7 1.1 4.4 6.4 5.2 1.3 0.3 1.2 10.0 3.2 3.2 2.8 2.3 2.3 6.4
ORP
37 ORP Bypass Delay
03
torp torpbp
Outputs
36 ORP Delay
2E
t4ptbpc t4ptbpr t1ptxor t20ptxor txoradj tgbp tgsu tgh tgco tgro tptre tptoe tptck
EW
N
0.5 1.8 - - - - 2.5 - - - - - - -
R
33 GLB Product Term Reset to Register Delay 35 GLB Product Term Clock Delay
FO
34 GLB Product Term Output Enable to I/O Cell Delay
Clocks
SE
tgy0 tgy1/2 tgr
is
tob tsl toen todis tgoe
38 Output Buffer Delay
I2
40 I/O Cell OE to Output Enabled 41 I/O Cell OE to Output Disabled 42 Global Output Enable 43 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock) 44 Clock Delay, Y1 or Y2 to Global GLB Clock Line 45 Global Reset to GLB
pL S
39 Output Slew Limited Delay Adder
1.9 1.9 -
U
Global Reset
1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. 3. The XOR adjacent path can only be used by hard macros.
Table 2-0036C-180/2032
7
S
tio tdin
20 Input Buffer Delay
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Specifications ispLSI 2032/A
Internal Timing Parameters1
Over Recommended Operating Conditions
PARAMETER Inputs 21 Dedicated Input Delay 22 GRP Delay 23 4 Product Term Bypass Path Delay (Combinatorial) 24 4 Product Term Bypass Path Delay (Registered) 25 1 Product Term/XOR Path Delay 26 20 Product Term/XOR Path Delay 27 XOR Adjacent Path Delay
3
#2
DESCRIPTION
-110
-80
MIN. MAX. MIN. MAX. - - - 1.7 3.4 1.7 - - - 2.2 4.8
UNITS
GRP
tgrp
GLB
D ES IG N
2.6 - 4.9 4.8 6.2 6.8 7.5 0.1 - - 0.6 1.8 5.9 7.1 7.0 1.5 0.5 1.2 10.0 4.0 4.0 3.0 3.2 3.2 9.0 - 7.2 - - 7.2 - - 8.8 - - 9.2
ORP
37 ORP Bypass Delay
03
torp torpbp
Outputs
36 ORP Delay
2E
t4ptbpc t4ptbpr t1ptxor t20ptxor txoradj tgbp tgsu tgh tgco tgro tptre tptoe tptck
EW
- - 0.5 4.0 - - - - 4.0 - - - - - - - 3.2 3.2 -
- - 0.1 6.0 - - - - 5.5 - - - - - - - 4.6 4.6 -
10.2 0.0 - - 0.4 2.2 8.8 12.8 9.5 2.1 0.6 2.4 10.0 6.4 6.4 5.6 4.6 4.6 12.8
28 GLB Register Bypass Delay 29 GLB Register Setup Time befor Clock 30 GLB Register Hold Time after Clock 31 GLB Register Clock to Output Delay 32 GLB Register Reset to Output Delay 33 GLB Product Term Reset to Register Delay 35 GLB Product Term Clock Delay
N
R
FO
34 GLB Product Term Output Enable to I/O Cell Delay
Clocks
SE
tgy0 tgy1/2 tgr
is
tob tsl toen todis tgoe
38 Output Buffer Delay
I2
40 I/O Cell OE to Output Enabled 41 I/O Cell OE to Output Disabled 42 Global Output Enable 43 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock) 44 Clock Delay, Y1 or Y2 to Global GLB Clock Line 45 Global Reset to GLB
pL S
39 Output Slew Limited Delay Adder
U
Global Reset
1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. 3. The XOR adjacent path can only be used by hard macros.
Table 2-0036C-110/2032
8
S
tio tdin
20 Input Buffer Delay
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Specifications ispLSI 2032/A
ispLSI 2032/A Timing Model
I/O Cell
GRP Feedback
GLB
ORP
I/O Cell
Ded. In
20 PT XOR Delays #25, 26, 27 Reset #45 D
GLB Reg Delay Q #29, 30, 31, 32 RST
EW
Control RE PTs OE #33, 34, CK 35 Y0,1,2 GOE 0 #43, 44 #42
N
tsu
tco
Note: Calculations are based upon timing specifications for the ispLSI 2032/A-180L
Table 2- 0042-16/2032
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= = = 7.7 ns =
Clock (max) + Reg co + Output (tio + tgrp + tptck(max)) + (tgco) + (torp + tob) (#20+ #22+ #35) + (#31) + (#36 + #38) (0.6 + 0.7 + 3.8) + (0.7) + (0.7 + 1.2)
I2
03
th
= = = 1.5 ns =
Clock (max) + Reg h - Logic (tio + tgrp + tptck(max)) + (tgh) - (tio + tgrp + t20ptxor) (#20+ #22+ #35) + (#30) - (#20+ #22+ #26) (0.6 + 0.7 + 3.8) + (1.8) - (0.6 + 0.7 + 4.1)
2E
= = = 2.1 ns =
Logic + Reg su - Clock (min) (tio + tgrp + t20ptxor) + (tgsu) - (tio + tgrp + tptck(min)) (#20+ #22+ #26) + (#29) - (#20+ #22+ #35) (0.6 + 0.7 + 4.1) + (0.5) - (0.6 + 0.7 + 2.5)
FO
Derivations of tsu, th and tco from the Product Term Clock 1
9
R
D ES IG N
ORP Delay #36 #40, 41
0491/2000
I/O Pin (Input)
I/O Delay #20
GRP #22
Reg 4 PT Bypass #24
GLB Reg Bypass #28
ORP Bypass #37
#38, 39
S
#21
Comb 4 PT Bypass #23 I/O Pin (Output)
Specifications ispLSI 2032/A
Power Consumption
Power consumption in the ispLSI 2032 and 2032A devices depends on two primary factors: the speed at which the device is operating and the number of Product Terms Figure 4. Typical Device Power Consumption vs fmax used. Figure 4 shows the relationship between power and operating speed.
120 110 100
ispLSI 2032/A (-150, -180)
ICC (mA)
90 80 70 60 50 40 1 20 40
FO
60
80
U
The ICC estimate is based on typical conditions (VCC = 5.0V, room temperature) and an assumption of two GLB loads on average exists. These values are for estimates only. Since the value of ICC is sensitive to operating conditions and the program in the device, the actual ICC should be verified.
0127A/2032A
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Where: # of PTs = Number of Product Terms used in design # of nets = Number of Signals used in device Max freq = Highest Clock Frequency to the device (in MHz)
pL S
For 2032/A -150, -180: ICC(mA) = 30 + (# of PTs * 0.46) + (# of nets * Max freq * 0.012) For 2032/A -135, -110, -80: ICC(mA) = 21 + (# of PTs * 0.30) + (# of nets * Max freq * 0.012)
I2
ICC can be estimated for the ispLSI 2032/A using the following equation:
03
2E
fmax (MHz)
Notes: Configuration of Two 16-bit Counters Typical Current at 5V, 25 C
10
R
100 120 140 160 180
N
ispLSI 2032/A (-80, -110, -135)
EW
D ES IG N
S
Specifications ispLSI 2032/A
Pin Description
44-PIN PLCC PIN NUMBERS
15, 19, 25, 29, 37, 41, 3, 7, 2 11 35 16, 20, 26, 30, 38, 42, 4, 8, 17, 21, 27, 31, 39, 43, 5, 9, 18, 22, 28, 32, 40, 44, 6, 10
NAME
I/O 0 - I/O 3 I/O 4 - I/O 7 I/O 8 - I/O 11 I/O 12 - I/O 15 I/O 16 - I/O 19 I/O 20 - I/O 23 I/O 24 - I/O 27 I/O 28 - I/O 31 GOE 0 Y0 RESET/Y1
44-PIN TQFP PIN NUMBERS
9, 13, 19, 23, 31 35, 41, 1, 40 5 29 10, 14, 20, 24, 32, 36, 42, 2, 11, 15, 21, 25, 33, 37, 43, 3, 12, 16, 22, 26, 34, 38, 44, 4
48-PIN TQFP PIN NUMBERS
9, 14, 20, 25, 33, 38, 44, 1, 43 5 31 10, 15, 21, 26, 34, 39, 45, 2, 11, 16, 22, 27, 35, 40, 46, 3, 13, 17, 23, 28, 37, 41, 47, 4
DESCRIPTION
Input/Output Pins -- These are the general purpose I/O pins used by the logic array.
Global Output Enable input pin.
ispEN
13
7
7
SDI/IN 02
14
8
8
MODE SDO/IN 12
36 24
30 18
FO
32 19
R
2E
GND VCC NC1
pL S
1,
23
I2
SCLK/Y22
03
33
27
29
17, 39 6, 28
18, 42 6, 30
is
12, 34
12, 24, 36, 48
N
Input -- Dedicated in-system programming enable input pin. This pin is brought low to enable the programming mode. The MODE, SDI, SDO and SCLK controls become active. Input -- This pin performs two functions. When ispEN is logic low, it functions as an input pin to load programming data into the device. SDI/IN0 also is used as one of the two control pins for the isp state machine. When ispEN is high, it functions as a dedicated input pin.
Input -- When in ISP Mode, controls operation of ISP state machine. Output/Input -- This pin performs two functions. When ispEN is logic low, it functions as an output pin to read serial shift register data. When ispEN is high, it functions as a dedicated input pin. Input -- This pin performs two functions. When ispEN is logic low, it functions as a clock pin for the Serial Shift Register. When ispEN is high, it functions as a dedicated clock input. This clock input is brought into the Clock Distribution Network and can be routed to any GLB and/or I/O cell on the device. Ground (GND) VCC No Connect.
Table 2-0002A-08isp/2032
1. NC pins are not to be connected to any active signals, VCC or GND. 2. Pins have dual function capability.
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11
EW
Dedicated Clock input. This clock input is connected to one of the clock inputs of all the GLBs on the device. This pin performs two functions: - Dedicated clock input. This clock input is brought into the Clock Distribution Network, and can optionally be routed to any GLB and/or I/O cell on the device. - Active Low (0) Reset pin which resets all of the GLB and I/O registers in the device.
D ES IG N
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Specifications ispLSI 2032/A
Pin Configuration
ispLSI 2032/A 44-Pin PLCC Pinout Diagram
GOE 0
I/O 27
I/O 26 I/O 25
I/O 24
GND I/O 23
I/O 22
I/O 28 I/O 29 I/O 30 I/O 31 Y0 VCC ispEN
1SDI/IN
7 8 9 10 11 12 13 14 15 16 17
39 38 37 36 35 34 33 32 31 30 29
I/O 18 I/O 17 I/O 16
MODE
ispLSI 2032/A
Top View
RESET/Y1 VCC SCLK/Y21 I/O 15 I/O 14 I/O 13 I/O 12
0
18 19 20 21 22 23 24 25 26 27 28
I/O 8
R
1SDO/IN
I/O 9 I/O 10 I/O 11
I/O 3
I/O 4 I/O 5
I/O 6
I/O 7
GND
N
1
EW
I/O 0 I/O 1 I/O 2
1. Pins have dual function capability.
ispLSI 2032/A 44-Pin TQFP Pinout Diagram
I/O 27
03
2E
GOE 0
I/O 26 I/O 25
I/O 24
GND I/O 23
FO
I/O 22
I2
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22
1 I/O 8
1SDO/IN
pL S
I/O 28 I/O 29 I/O 30 I/O 31
1 2 3 4 5 6 7 8
I/O 21 I/O 20 I/O 19
I/O 18 I/O 17 I/O 16 MODE RESET/Y1 VCC SCLK/Y21 I/O 15 I/O 14 I/O 13 I/O 12
is
Y0 VCC 0
ispLSI 2032/A
Top View
ispEN
1SDI/IN
SE
U
I/O 0 I/O 1 I/O 2
9 10 11
I/O 9 I/O 10 I/O 11
I/O 3
I/O 4 I/O 5
I/O 6
I/O 7
GND
1. Pins have dual function capability.
12
D ES IG N
0123B/2032/A
0851/2032/A
S
6 5 4 3 2 1 44 43 42 41 40
I/O 21 I/O 20 I/O 19
Specifications ispLSI 2032/A
Pin Configuration
ispLSI 2032/A 48-Pin TQFP Pinout Diagram
GOE 0 I/O 27 I/O 26 I/O 25 I/O 24 GND I/O 23 I/O 22 NC1 I/O 21 I/O 20 I/O 19
48 47 46 45 44 43 42 41 40 39 38 37 I/O 28 I/O 29 I/O 30 I/O 31 Y0 VCC ispEN
2SDI/IN
3 4 5 6 7 8 9 10 11 12
34 33
ispLSI 2032/A
Top View
32 31 30 29 28 27 26 25
0
13 14 15 16 17 18 19 20 21 22 23 24
GND 2SDO/IN 1 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 8
R
I/O 9 I/O 10 I/O 11 1NC
N
EW
I/O 0 I/O 1 I/O 2 1NC
1. NC pins are not to be connected to any active signal, Vcc or GND. 2. Pins have dual function capability.
U
SE
is
pL S
I2
03
2E
FO
13
D ES IG N
I/O 17 I/O 16 MODE RESET/Y12 VCC SCLK/Y22 I/O 15 I/O 14 I/O 13 I/O 12
48-Pin TQFP-2032/A
1 2
36 35
NC1 I/O 18
S
Specifications ispLSI 2032/A
Part Number Description
ispLSI XXXX --XXX X XXX X
Device Family Device Number 2032 2032A Speed 180 = 180 MHz fmax 150 = 154 MHz fmax 135 = 137 MHz fmax 110 = 111 MHz fmax 80 = 84 MHz fmax Grade Blank = Commercial I = Industrial Package J = PLCC T44 = TQFP T48 = TQFP Power L = Low
0212A/2032
COMMERCIAL
FAMILY fmax (MHz) 180 180 180 154 154 154 137 137 137 111 111 111 84 84 84 tpd (ns) 5.0 5.0 5.0 5.5 5.5 5.5 7.5 7.5 7.5 10 10 10 15 15 15
N
ORDERING NUMBER ispLSI 2032A-180LJ44
EW
ispLSI 2032/A Ordering Information
ispLSI
pL S
I2
03
2E
FO
R
ispLSI 2032A-180LT44 ispLSI 2032A-180LT48 ispLSI 2032A-150LJ44 ispLSI 2032A-150LT44 ispLSI 2032A-150LT48 ispLSI 2032A-135LJ44 ispLSI 2032A-135LT44 ispLSI 2032A-135LT48 ispLSI 2032A-110LJ44 ispLSI 2032A-110LT44 ispLSI 2032A-110LT48 ispLSI 2032A-80LJ44 ispLSI 2032A-80LT44 ispLSI 2032A-80LT48
is
INDUSTRIAL
tpd (ns) 15 15 15 ORDERING NUMBER ispLSI 2032A-80LJ44I ispLSI 2032A-80LT44I ispLSI 2032A-80LT48I PACKAGE 44-Pin PLCC 44-Pin TQFP 48-Pin TQFP
Table 2-0041B/2032A
FAMILY ispLSI
fmax (MHz) 84 84 84
U
SE
14
D ES IG N
PACKAGE 44-Pin PLCC 44-Pin TQFP 48-Pin TQFP 44-Pin PLCC 44-Pin TQFP 48-Pin TQFP 44-Pin PLCC 44-Pin TQFP 48-Pin TQFP 44-Pin PLCC 44-Pin TQFP 48-Pin TQFP 44-Pin PLCC 44-Pin TQFP 48-Pin TQFP
Table 2-0041A/2032A
S
Specifications ispLSI 2032/A
COMMERCIAL
FAMILY fmax (MHz) 180 180 180 154 154 154 137 137 137 111 111 111 84 84 84 tpd (ns) 5.0 5.0 5.0 5.5 5.5 5.5 7.5 7.5 7.5 10 10 10 15 15 15 ORDERING NUMBER ispLSI 2032-180LJ ispLSI 2032-180LT44 ispLSI 2032-180LT48 ispLSI 2032-150LJ ispLSI 2032-150LT44 ispLSI 2032-150LT48 ispLSI 2032-135LJ ispLSI 2032-135LT44 ispLSI 2032-135LT48 ispLSI 2032-110LJ ispLSI 2032-110LT44 ispLSI 2032-110LT48 ispLSI 2032-80LJ ispLSI 2032-80LT44 ispLSI 2032-80LT48 PACKAGE 44-Pin PLCC 44-Pin TQFP 48-Pin TQFP 44-Pin PLCC 44-Pin TQFP 48-Pin TQFP 44-Pin PLCC 44-Pin TQFP 48-Pin TQFP 44-Pin PLCC 44-Pin TQFP 48-Pin TQFP 44-Pin PLCC 44-Pin TQFP 48-Pin TQFP
Table 2-0041A/2032
ispLSI
INDUSTRIAL
FAMILY ispLSI fmax (MHz) 84 84 84 tpd (ns) 15 15 15
ORDERING NUMBER ispLSI 2032-80LJI ispLSI 2032-80LT44I ispLSI 2032-80LT48I
N
EW
FO
R
U
SE
is
pL S
I2
03
2E
15
D ES IG N
PACKAGE 44-Pin PLCC 44-Pin TQFP 48-Pin TQFP
Table 2-0041C/2032
S

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