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12-Bit 400 MSPS A/D Converter AD12400
FEATURES
400 MSPS sample rate SNR of 63 dBFS @128 MHz SFDR of 70 dBFS @128 MHz VSWR of 1:1.5 Wideband ac-coupled input signal conditioning Enhanced spurious-free dynamic range Single-ended or differential encode signal LVDS output levels Twos complement output data
FUNCTIONAL BLOCK DIAGRAM
AD12400
ADC A POSTPROCESSING DATA READY A
DA0-DA11
CLK DISTRIBUTION AIN ADC B
DB0-DB11
APPLICATIONS
Communications test equipment Radar and satellite subsystems Phased array antennas--digital beam forming Multichannel, multimode receivers Secure communications Wireless and wired broadband communications Wideband carrier frequency systems
CLOCK DISTRIBUTION DIVIDE BY 2
DATA READY B
ENC
ENC
Figure 1.
GENERAL DESCRIPTION
The AD12400 is a 12-bit analog-to-digital converter with a transformer-coupled analog input and digital post processing for enhanced SFDR. The product operates at a 400 MSPS conversion rate with outstanding dynamic performance in wideband carrier systems. The AD12400 requires 3.8 V analog, 3.3 V digital, and 1.5 V digital supplies and provides a flexible encode signal that can be differential or single-ended. No external reference is required. The AD12400 package style is an enclosed 2.9" x 2.6" x 0.6" module. Performance is rated over a 0C to 60C case temperature range.
PRODUCT HIGHLIGHTS
1. 2. 3. 4. Guaranteed sample rate of 400 MSPS. Input signal conditioning with optimized dynamic performance to 180 MHz. Additional performance options available--contact factory. Proprietary Advanced Filter BankTM digital post processing from VCorp(R) Technologies, Inc.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 (c) 2003 Analog Devices, Inc. All rights reserved.
03735-0-001
AD12400 TABLE OF CONTENTS
Specifications..................................................................................... 3 DC Specifications ......................................................................... 3 AC Specifications.......................................................................... 4 Explanation of Test Levels ............................................................... 5 Absolute Maximum Ratings............................................................ 6 ESD Caution.................................................................................. 6 Pin Configuration and Function Descriptions............................. 8 Definitions of Specifications ......................................................... 11 Typical Performance Characteristics ........................................... 13 Theory of Operation ...................................................................... 15 Time-Interleaving ADCs ........................................................... 15 Analog Input ............................................................................... 16 Clock Input.................................................................................. 16 Digital Outputs ........................................................................... 16 Power Supplies ............................................................................ 16 START-UP AND RESET ........................................................... 17 Lead/Lag ...................................................................................... 17 Thermal Considerations............................................................ 17 Package Integrity/Mounting Guidelines ................................. 18 AD12400 Evaluation KIT.......................................................... 19 Power Connector ................................................................... 19 Analog Input ........................................................................... 19 Encode ..................................................................................... 19 Data Outputs........................................................................... 19 Adapter Card .......................................................................... 19 Digital Post Processing Control ........................................... 19 RESET ...................................................................................... 19 Layout Guidelines........................................................................... 25 PCB Interface .............................................................................. 25 Outline Dimensions ....................................................................... 27 Ordering Guide .......................................................................... 27
REVISION HISTORY
Revision 0: Initial Version
Rev. 0 | Page 2 of 28
AD12400 SPECIFICATIONS
DC SPECIFICATIONS
Table 1. VA = 3.8 V, VC = 3.3 V, VD = 1.5 V, Encode = 400 MSPS, 0C TCASE 60C, unless otherwise noted.
Parameter RESOLUTION ACCURACY No Missing Codes Offset Error Gain Error @ 10 MHz Differential Nonlinearity (DNL) Integral Nonlinearity (INL) TEMPERATURE DRIFT Gain Error ANALOG INPUT (AIN) Full-Scale Input Voltage Range Frequency Range Flatness (10 MHz-180 MHz) Input VSWR (50 ) (10 MHz-180 MHz) Analog Input Bandwidth POWER SUPPLY1 Supply Voltage VA VC VD Supply Current IVA (VA = 3.8 V) IVC (VC = 3.3 V) IVD (VD = 1.5 V) Total Power Dissipation ENCODE INPUTS2 Differential Inputs (ENC, ENC) Input Voltage Range Input Resistance Input Capacitance Common-Mode Voltage Single-Ended Inputs (ENC) Input Voltage Input Resistance LOGIC INPUTS (RESET)3 Logic 1 Voltage Logic 0 Voltage Source IIH Source IIL LOGIC OUTPUTS (DRA, DRB, Output Bits)4 Differential Output Voltage Case Temp Test Level Min AD12400JWS Typ 12 Guaranteed -12 -10 0.3 0.5 0.02 3.2 10 0.5 1.5 450 180 1 10 0.5 1.5 450 +12 +10 -12 -10 0.3 0.5 0.02 3.2 180 1 Max Min AD12400KWS Typ 12 Guaranteed +12 +10 LSB %FS LSB LSB %/C V p-p MHz dB Max Unit Bits
Full Full Full 60C 60C 60C 60C Full Full 60C 60C
IV I I V V V V IV IV V V
MHz
Full Full Full Full Full Full Full
IV IV IV I I I I
3.6 3.2 1.475 0.95 400 1.4 7.0
3.8 3.4 1.575 1.11 500 1.8 8.5
3.6 3.2 1.475 0.95 400 1.4 7.0
3.8 3.4 1.575 1.11 500 1.8 8.5
V V V A mA A W
Full 60C 60C 60C Full 60C Full Full 60C 60C
IV V V V IV V IV IV V V
0.4 100 4 3 0.4 2 50 2.5
0.4 100 4 3 0.4 2 50 2.5
V pF V V p-p V V A mA
2.0 0.8 10 1
2.0 0.8 10 1
Full
IV
247
Rev. 0 | Page 3 of 28
454
247
454
mV
AD12400
AD12400JWS LOGIC OUTPUTS Output Drive Current Output Common-Mode Voltage Start-Up Time
1
AD12400KWS +4 1.375 -4 1.125 600 +4 1.375 mA V ms
Full Full Full
IV IV IV
-4 1.125 600
Tested using input frequency of 70 MHz. See Figure 17 for I(VD) variation vs. input frequency. 2 All ac specifications tested by driving ENC single-ended. 3 Refer to Table 5 for logic convention on all logic inputs. 4 Digital Output Logic Levels: DR V = 3.3 V, CLOAD = 8 pF. 3.3 V LVDS R1 = 100 . Specifications subject to change without notice.
AC SPECIFICATIONS1
Table 2. VA = 3.8 V, VC = 3.3 V, VD = 1.5 V, Encode = 400 MSPS, 0C TCASE 60C, unless otherwise noted.
Parameter DYNAMIC PERFORMANCE2 SNR Analog Input 10 MHz @ -1.0 dBFS 70 MHz 128 MHz 180 MHz SINAD3 Analog Input 10 MHz @ -1.0 dBFS 70 MHz 128 MHz 180 MHz Spurious-Free Dynamic Range3 Analog Input 10 MHz @ -1.0 dBFS 70 MHz 128 MHz 180 MHz Image Spur4 Analog Input 10 MHz @ -1.0 dBFS 70 MHz 128 MHz 180 MHz Offset Spur4 Analog Input @ -1.0 dBFS Two-Tone IMD5 F1, F2 @ -6 dBFS SWITCHING SPECIFICATIONS Conversion Rate6 Encode Pulsewidth High (tEH)1 Encode Pulsewidth Low (tEL)1 DIGITAL OUTPUT PARAMETERS Valid Time (tV) Propagation Delay (tPD) Rise Time (tR) (20% to 80%) Fall Time (tF) (20% to 80%) Case Temp Test Level AD12400JWS Min Typ Max AD12400KWS Min Typ Max Unit
Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full 60C
I I I I I I I I I I I I I I I I V
62 61.5 60 60 61 60.5 59 57 69 69 67 62 60 60 56 54
64.4 64 63.5 62.5 64 64 62.5 61 80 84 76 71 75 72 70 70 65
62 61.5 60 60 61 60.5 59 57 69 69 67 62 62 62 62 62
64.4 64 63.5 62.5 64 64 62.5 61 80 84 76 71 75 72 70 70 65
dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS
60C Full 60C 60C Full 60C 60C 60C
V IV V V IV V V V 396
-75 400 1.25 1.25 2.4 1.20 1 1 404 396
-75 400 1.25 1.25 2.4 1.20 1 1 404
dBc MSPS ns ns ns ns ns ns
1.9
3.1
1.9
3.1
Rev. 0 | Page 4 of 28
AD12400
Parameter DR Propagation Delay (tEDR) Data to DR Skew (tEDR - tPD) Pipeline Latency7 Aperture Delay (tA) Aperture Uncertainty (Jitter, tJ)
1 2 3
Case Temp 60C 60C Full 60C 60C
Test Level V V IV V V
AD12400JWS Min Typ Max 3.88 2.68 40 1.6 0.4
AD12400KWS Min Typ Max 3.88 2.68 40 1.6 0.4
Unit ns ns Cycles ns ps rms
All ac specifications tested with a single-ended 2.0 V p-p ENCODE. Dynamic performance guaranteed for analog input frequencies of 10 MHz to 180 MHz. Not including image spur. 4 Image spur will be at fs/2-AIN and the offset spur will be at fs/2. 5 F1 = 70 MHz, F2 = 73 MHz. 6 Parts are tested with 400 MSPS encode. Device can be clocked at lower encode rates, but specifications are not guaranteed. Specifications will be guaranteed by design for encode 400 MSPS 1%. 7 Pipeline latency will be exactly 40 cycles.
EXPLANATION OF TEST LEVELS
I II III IV V VI 100% production tested. 100% production tested at 25C and sample tested at specified temperatures. Sample tested only. Parameter is guaranteed by design and characterization testing. Parameter is a typical value only. 100% production tested at 25C; guaranteed by design and characterization testing for industrial temperature range; 100% production tested at temperature extremes for military devices.
Rev. 0 | Page 5 of 28
AD12400
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter VA to AGND VC to DGND VD to DGND Analog Input Voltage Analog Input Power Encode Input Voltage Encode Input Power Logic Inputs and Outputs to DGND Storage Temperature Range, Ambient Operating Temperature Value 5V 4V 1.65 V 6 V (DC) 18 dBm (AC) 6 V (DC) 12 dBm (AC) 5V -65C to +150C 0C to 60C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. 0 | Page 6 of 28
AD12400
Table 4. Output Coding (Twos Complement)
Code 4095 . . . 2048 2047 . . 0 AIN (V) +1.6 . . . 0 -0.000781 . . -1.6 Digital Output 0111 1111 1111 . . . 0000 0000 0000 1111 1111 1111 . . 1000 0000 0000
N-1 N N+1 N+2 N+3
tEL tEH
ENCODE 400MHZ
1/fS
40 CLOCK CYCLES DATA OUT A DRA DRA N - 40 N - 39 N N+2 N+4
*
N+6 N+8
*
DATA OUT B DRB DRB LEAD LAG N+1 N+3 N+5 N+7
Table 5. Option Pin List With Necessary Associated Circuitry
Active High or Low Low Low Logic Level Type LVTTL LVTTL Default Level High Low Associated Circuitry Within Part 3.74 k Pull-Up 10 k - 60 k Pull-Down
*DATA LOST DUE TO ASSERTION OF LEAD/LAG. LATENCY OF 40 ENCODE CLOCK CYCLES BEFORE DATA VALID. NOTES: 1 IF A SINGLE-ENDED SINEWAVE IS USED FOR ENCODE, USE THE "ZERO CROSSING" POINT (AC-COUPLED) AS THE 50% POINT AND APPLY THE SAME TIMING INFORMATION. 2 THE LEAD/LAG PIN IS USED TO SYNCHRONIZE THE COLLECTION OF DATA INTO EXTERNAL BUFFER MEMORIES. THE LEAD/LAG PIN CAN BE APPLIED SYNCHRONOUSLY OR ASYNCHRONOUSLY TO THE AD12400. IF APPLIED ASYNCHRONOUSLY, LEAD/LAG MUST BE HELD HIGH FOR A MINIMUM OF 5ns TO ENSURE CORRECT OPERATION. THE FUNCTION WILL SHUT OFF DRA AND DRB UNTIL THE LEAD/LAG PIN IS RELEASED. DRA AND DRB WILL RESUME ON THE NEXT VALID DRA AFTER LEAD/LAG IS RELEASED.
Pin Name RESET LEAD/LAG
Figure 3. Timing Diagram
tPD
ENC ENC
3.3V
DATA OUT
100 ENCODE 3.3V 100 ENCODE 100 100 PECL DRIVER
03735-0-003
DR
03735-0-004
DR
tV
Figure 4. Highlighted Timing Diagram
Figure 2. Encode Equivalent Circuit
Rev. 0 | Page 7 of 28
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AD12400 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AIN PIN 1 PIN 119 VA VA VA VA AGND AGND DNC DNC DNC DNC DNC DNC AGND AGND AGND AGND AGND AGND AGND AGND DNC LEAD/LAG DA1+ DA1- DA3+ DA3- DA5+ DA5- DA7+ DA7- DA9+ DA9- DA11+ DA11- DNC DNC VD VD VD VD DB1+ DB1- DB3+ DB3- DB5+ DB5- DB7+ DB7- DB9+ DB9- DB11+ DB11- DNC DNC DNC DNC DNC RESET VC VC
*
ENC
ENC
TOP VIEW
VA VA VA VA AGND AGND DNC DNC DNC DNC DNC DNC DNC AGND AGND AGND AGND AGND AGND AGND DRA DRA DA0+ DA0- DA2+ DA2- DA4+ DA4- DA6+ DA6- DA8+ DA8- DA10+ DA10- DNC PASS VD VD VD VD DB0+ DB0- DB2+ DB2- DB4+ DB4- DB6+ DB6- DB8+ DB8- DB10+ DB10- DNC DNC DRB DRB DNC DNC VC VC
PIN 120
C
JOHNSON SMA-50 OHM CONNECT NO. 142-0711-821 PIN 79
*
PIN 80
2-56 STUDS 4x END VIEW SAMTEC CONNECTOR QTE-060-01-L-D-A-K-TR ENC BOARD
B
ENC
PIN 39
*
PIN 40
AIN
A
BOTTOM VIEW NOTES FOR MATING HALF, USE SAMTEC, INC. PART NO. QSE-60-01-L-D-A-K.
LEFT SIDE VIEW *INTEGRAL GROUND PLANE CONNECTIONS. SECTION A = DGND, PINS 121-124. SECTION B = DGND, PINS 125-128. SECTION C = AGND, PINS 129-132.
PIN 1
PIN 2
Figure 5. Pin Configuration
Rev. 0 | Page 8 of 28
03735-0-005
AD12400
Table 6. Pin Function Descriptions
Pin Number 1, 2, 3, 4 5 6-9, 11, 13-16, 49, 51-52, 79, 96-108 10 12 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41-48 50 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 Mnemonic VC RESET DNC Function Digital Supply, +3.3 V. LVTTL. 0 = Device Reset. Minimum Width = 200 ns. Device resumes operation after 600 ms maximum. Do Not Connect.
DRB DRB DB11- DB10- DB11+ DB10+ DB9- DB8- DB9+ DB8+ DB7- DB6- DB7+ DB6+ DB5- DB4- DB5+ DB4+ DB3- DB2- DB3+ DB2+ DB1- DB0- DB1+ DB0+ VD PASS DA11- DA10- DA11+ DA10+ DA9- DA8- DA9+ DA8+ DA7- DA6- DA7+ DA6+ DA5- DA4- DA5+
Channel B Data Ready. Complement output. Channel B Data Ready. True output. Channel B Data Bit 11. Complement output bit. Channel B Data Bit 10. Complement output bit. Channel B Data Bit 11. True output bit. Channel B Data Bit 10. True output bit. Channel B Data Bit 9. Complement output bit. Channel B Data Bit 8. Complement output bit. Channel B Data Bit 9. True output bit. Channel B Data Bit 8. True output bit. Channel B Data Bit 7. Complement output bit. Channel B Data Bit 6. Complement output bit. Channel B Data Bit 7. True output bit. Channel B Data Bit 6. True output bit. Channel B Data Bit 5. Complement output bit. Channel B Data Bit 4. Complement output bit. Channel B Data Bit 5. True output bit. Channel B Data Bit 4. True output bit. Channel B Data Bit 3. Complement output bit. Channel B Data Bit 2. Complement output bit. Channel B Data Bit 3. True output bit. Channel B Data Bit 2. True output bit. Channel B Data Bit 1. Complement output bit. Channel B Data Bit 0. Complement output bit. DB0 is LSB. Channel B Data Bit 1. True output bit. Channel B Data Bit 0. True output bit. DB0 is LSB. Digital Supply, +1.5 V. LVTTL. Factory use only. (DNC) Channel A Data Bit 11. Complement output bit. Channel A Data Bit 10. Complement output bit. Channel A Data Bit 11. True output bit. Channel A Data Bit 10. True output bit. Channel A Data Bit 9. Complement output bit. Channel A Data Bit 8. Complement output bit. Channel A Data Bit 9. True output bit. Channel A Data Bit 8. True output bit. Channel A Data Bit 7. Complement output bit. Channel A Data Bit 6. Complement output bit. Channel A Data Bit 7. True output bit. Channel A Data Bit 6. True output bit. Channel A Data Bit 5. Complement output bit. Channel A Data Bit 4. Complement output bit. Channel A Data Bit 5. True output bit.
Rev. 0 | Page 9 of 28
AD12400
Pin Number 68 69 70 71 72 73 74 75 76 77 78 80 81-95, 109-112, 129-132* 113-120 121-128* Mnemonic DA4+ DA3- DA2- DA3+ DA2+ DA1- DA0- DA1+ DA0+ LEAD/LAG DRA DRA AGND VA DGND Function Channel A Data Bit 4. True output bit. Channel A Data Bit 3. Complement output bit. Channel A Data Bit 2. Complement output bit. Channel A Data Bit 3. True output bit. Channel A Data Bit 2. True output bit. Channel A Data Bit 1. Complement output bit. Channel A Data Bit 0. Complement output bit. DA0 is LSB. Channel A Data Bit 1. True output bit. Channel A Data Bit 0. True output bit. DA0 is LSB. Typically DNC. See LEAD/LAG note on Page 17. Channel A Data Ready. Complement output. Channel A Data Ready. True output. Analog Ground. Analog Supply, 3.8 V Digital Ground.
*Internal Ground Plane Connections: Section A = DGND, Pins 121-124, Section B = DGND, Pins 125-128, Section C = AGND, Pins 129-132.
Rev. 0 | Page 10 of 28
AD12400 DEFINITIONS OF SPECIFICATIONS
Analog Bandwidth
The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB.
Gain Error
The difference between the measured and ideal full-scale input voltage range of the ADC.
Harmonic Distortion, Second
The ratio of the RMS signal amplitude to the RMS value of the second harmonic component, reported in dBFS.
Aperture Delay
The delay between the 50% point on the rising edge of the ENCODE command and the instant at which the analog input is sampled.
Harmonic Distortion, Third
The ratio of the RMS signal amplitude to the RMS value of the third harmonic component, reported in dBFS.
Aperture Uncertainty (Jitter)
The sample-to-sample variation in aperture delay.
Distortion, Image Spur
The ratio of the RMS signal amplitude to the RMS signal amplitude of the image spur, reported in dBFS. The image spur, a result of gain and phase errors between two time-interleaved conversion channels, is located at fs/2 - fAIN.
Full-Scale Input Voltage Range
This is the maximum peak-to-peak input signal magnitude that will result in a full-scale response, 0 dBFS on a single-tone input signal case. Any magnitude increase from this value will result in an over-range condition.
Distortion, Offset Spur
The ratio of the RMS signal amplitude to the RMS signal amplitude of the offset spur, reported in dBFS. The offset spur, a result of offset errors between two time-interleaved conversion channels, is located at fs/2.
Analog Input VSWR (50 )
The Voltage Standing Wave Ratio is a ratio of the transmitted and reflected signals. The VSWR can be related to input impedance using the following equations:
= ZL - ZS ZL + ZS
Integral Nonlinearity
The deviation of the transfer function from a reference line measured in fractions of 1 LSB using a "best straight line" determined by a least square curve fit.
VSWR =
1- 1+ Z L = Actual Load Impedance Z S = Reference Impedance
Minimum Conversion Rate
The minimum ENCODE rate at which the image spur calibration will degrade no more than 1 dB (when image spur is 70 dB).
Differential Nonlinearity
The deviation of any code width from an ideal 1 LSB step.
Maximum Conversion Rate
The maximum ENCODE rate at which the image spur calibration will degrade no more than 1 dB (when image spur is 70 dB).
Effective Number of Bits (ENOB)
Calculated from the measured SNR based on the equation
ENOB = SNR MEASURED - 1.76 dB 6.02
Output Propagation Delay
The delay between a differential crossing of ENCODE and ENCODE (or zero crossing of a single-ended ENCODE).
Encode Pulsewidth/Duty Cycle
Pulsewidth high is the minimum amount of time the ENCODE pulse should be left in Logic 1 state to achieve rated performance; pulsewidth low is the minimum time the ENCODE pulse should be left in low state. See timing implications of changing tENCH in the Application Notes, Encode Input section. At a specified clock rate of 400 MSPS, these specifications define an acceptable ENCODE duty cycle.
Total Noise
Calculated as follows:
VNOISE = Z x 0.001 x 10
FSdBm -SNRdBc -SIGNALdBFS 10
Full-Scale Input Power
Expressed in dBm. Computed using the following equation:
V 2 FULL -SCALErms POWERFULL -SCALE = 10 log Z INPUT (0.001)
where Z is the input impedance, FS is the full scale of the device for the frequency in question, SNR is the value of the particular input level, and SIGNAL is the signal level within the ADC reported in dB below full scale. This value includes both thermal and quantization noise.
Rev. 0 | Page 11 of 28
AD12400
Offset Error
The DC offset imposed on the input signal by the ADC, reported in LSB (codes).
Spurious-Free Dynamic Range (SFDR)
The ratio of the RMS signal amplitude to the RMS value of the peak spurious spectral component, except the image spur. The peak spurious component may or may not be a harmonic. May be reported in dBc (i.e., degrades as signal level is lowered) or dBFS (always related back to converter full-scale).
Pipeline Latency
The number of clock cycles that the output data will lag the corresponding clock cycle.
Power Supply Rejection Ratio
The ratio of power supply voltage change to the resulting ADC output voltage change.
Two-Tone Intermodulation Distortion Rejection
The ratio of the RMS value of either input tone to the RMS value of the worst third-order intermodulation product; reported in dBc.
Signal-to-Noise-and-Distortion (SINAD)
The ratio of the RMS signal amplitude (set 1 dB below full scale) to the RMS value of the sum of all other spectral components, including harmonics but excluding DC and image spur.
Two-Tone SFDR
The ratio of the RMS value of either input tone to the RMS value of the peak spurious component. The peak spurious component may or may not be an IMD product. May be reported in dBc (i.e., degrades as signal level is lowered) or in dBFS (always related back to converter full-scale).
Signal-to-Noise Ratio (SNR)
The ratio of the RMS signal amplitude (set at 1 dB below full scale) to the RMS value of the sum of all other spectral components, excluding the first five harmonics and DC.
Rev. 0 | Page 12 of 28
AD12400 TYPICAL PERFORMANCE CHARACTERISTICS
NOTE X = Image spur N = Interleaved offset spur
0 -10 -20 -30 -40 -50
dB
0
SNR = 63.3dB SFDR = 75dBc SINAD = 62.9dB IMAGE SPUR = 80.5dBc
-10 -20 -30 -40 -50 -60 -70 X 2
SNR = 61.6dB SFDR = 69.0dBc SINAD = 60.0dB IMAGE SPUR = 70.4dBc
dB
-60 -70 -80 -90 -100 -110 -120 0 20 40 60 80 100 120 140 160 180 200 FREQUENCY (MHz) 2 456
03735-0-006
3 N 4 5 6
03735-0-009
3
XN
-80 -90 -100 -110 -120 0 20 40 60 80 100 120 140 FREQUENCY (MHz) 160 180
200
Figure 6. FFT: fS = 400 MSPS, AIN = 10.123 MHz @ -1.0 dBFS
Figure 9. FFT: fS = 400 MSPS, AIN = 180.123 MHz @ -1.0 dBFS
0 -10 -20 -30 -40 -50
dB dB
0
SNR = 63.1dB SFDR = 78.7dBc SINAD = 62.7dB IMAGE SPUR = 78.8dBc
-10 -20 -30 -40 -50
SFDR = 76.3dBc
2F1 - F2
2X -80 -90 -100 -110 -120 0 20 40 60 80 100 120 140 FREQUENCY (MHz) 160 180 6 5 4
3N
-80 -90 -100
03735-0-007
F2 - F1
-70
F2 + F1
-70
2F1 + F2 2F2 + F1
2F2 - F1
-60
-60
X2 X1
N
-110 -120 0 20 40 60 80 100 120 140 FREQUENCY (MHz) 160 180 200
200
Figure 7. FFT: fS = 400 MSPS, AIN = 65.123 MHz @ -1.0 dBFS
Figure 10. Two-Tone Intermodulation Distortion (25.1 MHz and 28.1 MHz; fS = 400 MSPS)
0 -10 -20 -30 -40 -50
dB
SNR = 62.5dB SFDR = 69.9dBc SINAD = 61.1dB IMAGE SPUR = 73.4dBc
0 -10 -20 -30 -40 -50
dB
SFDR = 77.3dBc
-60 -70 -80 -90 -100 -110 -120 0 20 40 60 80 100 120 140 FREQUENCY (MHz) 160 180 200 3 6 4 5
03735-0-008
X
2 N
2F1 - F2
2F2 - F1
F2 - F1
-70 -80 -90 -100 -110 -120
0
2F2 + F1 2F1 + F2
-60
F2 + F1
N
X2 X1
20
40
60
80 100 120 140 FREQUENCY (MHz)
160
180
200
Figure 8. FFT: fS = 400 MSPS, AIN = 128.123 MHz @ -1.0 dBFS
Figure 11. Two-Tone Intermodulation Distortion (70.1 MHz and 73.1 MHz; fS = 400 MSPS)
Rev. 0 | Page 13 of 28
03735-0-011
03735-0-010
AD12400
0 SFDR = 70dBc -10 -20 -30
95 IMAGE SPUR 90 85
MAGNITUDE (dB)
-40 -50
HARMONICS (dBc)
SECOND HARMONIC 80 75 THIRD HARMONIC 70 65 60
2F1 + F2 2F2 + F1
2F1 - F2
-70 -80 -90
-110 -120 0 20 40 60 80 100 120 140 FREQUENCY (MHz) 160 180 200
03735-0-036
0
20
40
60
80
100
120
140
160
180
ANALOG INPUT FREQUENCY (MHz)
Figure 12. Two-Tone Intermodulation Distortion (178.1 MHz and 182.1 MHz; fs = 400 MSPS) SFDR = 70 dBc
Figure 15. Harmonics vs. Analog Input Frequency
64.6
0.5
64.4
0.4 0.3 0.2 SNR (dBFS) GAIN (dB) 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 10.7 35.0 59.3 83.6 107.9 132.2 156.5 180.8 205.1 229.4 FREQUENCY (MHz)
03735-0-012
64.2 64.0 63.8 63.6 63.4 63.2 63.0 62.8 0 20 40 60 80 100 120 140 160 180 ANALOG INPUT FREQUENCY (MHz)
03735-0-015
Figure 13. Interleaved Gain Flatness
Figure 16. SNR vs. Analog Input Frequency
100 95 90
THIRD HARMONIC
2.2 2.1 2.0
VD SUPPLY CURRENT (A)
DISTORTION (dBFS)
IMAGE SPUR 85 SECOND HARMONIC 80 75 70 65 60 0 10 20 30 40 50 ANALOG INPUT LEVEL (dB) 60 70
03735-0-013
1.9 1.8 1.7 1.6 1.5 1.4 1.3
03735-0-016
1.2 1.1 1.0 0 20 40 60 80 100 120 140 160 180 INPUT FREQUENCY (MHz)
200
Figure 14. 2nd/3rd Harmonics and Image Spur vs. Analog Input Level-- fS = 400 MSPS, AIN = 70 MHz
Figure 17. +VD Current vs. AIN Frequency
Rev. 0 | Page 14 of 28
03735-0-014
-100
F2 - F1 X2 X1
F1 + F2
-60
2F2 - F1
AD12400 THEORY OF OPERATION
The AD12400 uses two high-speed, 12-bit analog-to-digital converters (ADCs) in a time-interleaved configuration to double the sample rate, while maintaining a high level of dynamic range performance. The digital output of each ADC channel is calibrated using a proprietary digital post processing technique, Advanced Filter Bank (AFBTM), from VCorp Technologies. AFB is implemented using a state-of-the-art Field Programmable Gate Array (FPGA) and provides a wide bandwidth, wide temperature match for any gain, phase, and clock timing errors between each ADC channel.
0 -10 -20 -30 -40 -50
dB
1
-60 -70 -80 -90 -100 -110 -120 0 20 40 X
IMAGE SPUR 3 2 4 6 N OFFSET SPUR
5
TIME-INTERLEAVING ADCS
When two ADCs are time-interleaved, gain and/or phase mismatches between each channel will produce an Image Spur at fs/2 - fAIN and an Offset Spur as shown in Figure 18. These mismatches can be the result of any combination of device tolerance, temperature, and frequency deviations.
0 -10 -20 -30 -40 -50
dB
60
80 100 120 140 FREQUENCY (MHz)
160
180
200
Figure 19. AD12400 with AFB Digital Post Processing
The relationship between image spur and channel mismatches is captured in Table 7 for specific conditions. Table 7. Image Spur vs. Channel Mismatch
Gain Error (%) 1 0.25 0.2 0.025 Aperture Delay Error (ps) 15 2.7 1.1 0.5 Image Spur (dBc) -40 -54 -62 -70
1
IMAGE SPUR X OFFSET SPUR
-60 -70 -80 -90 -100 -110 -120 0 20 40 60 80 100 120 140 FREQUENCY (MHz) 160 180 200 5 4 6
03735-0-017
N 2 3
.
For a more detailed description of time-interleaving in ADCs and a design example using the AD12400, refer to "Advanced Digital Post-Processing Techniques Enhance Performance in Time Interleaved ADC Systems," published in the August, 2003 edition of Analog Dialogue. This article can be found at http://www.analog.com/analogDialogue.
Figure 18. Image Spur Due to Mismatches between Two Interleaved ADCs (No AFB Digital Post Processing)
Figure 19 displays the performance of a similar converter with on-board, AFB post processing implemented. The -44 dBFS image spur has been reduced to -77 dBFS and as a result, the dynamic range of this time-interleaved ADC is no longer limited by the channel matching.
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03735-0-018
AD12400
ANALOG INPUT
The AD12400 analog input is ac-coupled using a proprietary, transformer front end circuit that provides 1 dB of gain flatness over the first Nyquist zone and a -3 dB bandwidth of 450 MHz. This front end circuit provides a VSWR of 1.5 (50 ) over the first Nyquist zone, and the typical full-scale input is 3.2 V p-p The MiniCircuits HELA-10 amplifier module can be used to drive the input at these power levels.
65 AIN = 10MHz 64 63 62 AIN = 65MHz
SNR (dB)
AIN = 128MHz 61 60 59 58 57 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 APERTURE JITTER (ps rms) 0.8 0.9 1.0
03735-0-037
CLOCK INPUT
The AD12400 requires a 400 MSPS encode that is divided by 2 and distributed to each ADC channel, 180 out of phase from each other. Internal ac-coupling and bias networks provide the framework for flexible clock input requirements that include single-ended sine-wave, single-ended PECL, and differential PECL. While the AD12400 is tested and calibrated using a single-ended sine-wave, properly designed PECL circuits that provide fast slew rates (>1V/ns) and minimize ringing will result in comparable dynamic range performance. There are two major factors to consider when designing the input clock circuit for the AD12400: aperture jitter and harmonic content. The relationship between aperture jitter and SNR can be characterized using the following equation. The equation assumes a single-tone full-scale input signal.
SNR = -20 log
AIN = 180MHz
Figure 20. SNR vs. Aperture Jitter
In addition to jitter, the harmonic content of single-ended sine wave clock sources must be controlled as well. The clock source used in the test and calibration process has a harmonic performance that is better than 60 dBc. Also, when using PECL or other square-wave clock sources, unstable behavior such as overshoot and ringing can affect phase matching and degrade the image spur performance
DIGITAL OUTPUTS
The AD12400's digital post processing circuit provides two parallel, 12-bit 200 MSPS data output buses. By providing two output busses that operate at one half the conversion rate, the AD12400 eliminates the need for large, expensive, high power demultiplexing circuits. The output data format is twos complement, maintaining the standard set by other high speed A/D converters such as the AD9430 and AD6645. Data-ready signals are provided for facilitating proper timing in the data capture circuit. Finally, the digital post processing circuit can be configured to provide alternate data output formats. Contact the factory for more details.
(2x f A x0t JRMS )2 +
2 2 1 1+ 2 2 xVNOISErms x N + N 1. 5 2 2
f A = Input frequency t JRMS = Aperture jitter N = ADC resolution (bits) = ADC DNL (LSB) = ADC input noise (LSBrms) V NOISE

Figure 20 displays the application of this relationship to fullscale, single-tone input signal on the AD12400, where the DNL was assumed to be 0.4 LSB, and the input noise was assumed to be 0.8 LSBrms. The vertical marker at 0.4 ps displays the SNR at the jitter level present in the AD12400 evaluation system, including the jitter associated with the AD12400 itself.
POWER SUPPLIES
The AD12400 requires three different supply voltages: a 1.5 V supply for the digital post processing circuit, a 3.3 V supply to facilitate digital I/O through the system, and a 3.8 V supply for the analog conversion and clock distribution circuits. The AD12400 incorporates two key features that result in solid power supply rejection ratio (PSRR) performance. First, onboard linear regulators are used to provide an extra level of power supply rejection for the analog circuits. The linear regulator used to supply the A/D converters provides an additional 60 dB of rejection at 100 kHz. Second, in order to address higher frequency noise (where the linear regulators' rejection degrades), the AD12400 incorporates high quality ceramic decoupling capacitors.
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AD12400
While this product has been designed to provide good PSRR performance, systems designers need to be aware of the risks associated with switching power supplies and consider using linear regulators in their high speed ADC systems. Switching power supplies typically produce both conducted and radiated energy that result in common-/differential-mode EMI currents. Any system that requires 12-bit performance has very little room for errors associated with power supply EMI. For example, a system goal of 74 dB dynamic range performance on the AD12400 will require noise currents that are less than 4.5 A and noise voltages of less than 225 V in the analog input path. In addition to the radiation of heat into its environment, the AD12400 module enables flow of heat through the mounting studs and standoffs as they contact the motherboard. As described in the Package Integrity/Mounting Guidelines section, the module should be secured to the motherboard using 2-56 nuts (washer use is optional). The torque on the nuts should not exceed 32 inch ounces. Use of a thermal grease at the standoffs will result in better thermal coupling between the board and module. Depending on the ambient conditions, air flow may be necessary to ensure the components in the module do not exceed their maximum operating temperature. In terms of reliability, the most sensitive component has a maximum junction temperature rating of 125C. Figures 21 and 22 provide a basic guideline for two key thermal management decisions: the use of thermal interface material between the module bottom cover/mother board and airflow. Figure 21 characterizes the typical thermal profile of an AD12400 that is not using thermal interface material. Figure 22 provides the same information for a configuration that uses gap-filling thermal interface material (in this case Thermagon T-Flex 600 series, 0.040" thickness was used). One can see from these profiles that the maximum die temperature is reduced by approximately 2C when thermal interface material is used. Figures 21 and 22 also provide a guideline for determining the airflow requirements for given ambient conditions. For example, a goal of 120C die temperature in a 40C ambient environment without the use of thermal interface material would require an air flow of 100 LFM. See the AD12400 Thermal Management and Measurement Application Note for further details. From a channel matching perspective, the most important consideration will be external thermal influences. It is possible for thermal imbalances in the end application to adversely affect the dynamic performance. Due to the temperature dependence of the image spur, substantial deviation from the factory calibration conditions can have a detrimental effect. Unbalanced thermal influences can cause gradients across the module, and performance degradation may result. Examples of unbalanced thermal influences may include large heat dissipating elements near one side of the AD12400 or obstructed air flow that does not flow uniformly across the module. The thermal sensitivity of the module can be affected by a change in thermal gradient across the module of 2C.
START-UP AND RESET
The AD12400's FPGA configuration is stored in the on-board EPROM and loaded into the FPGA when power is applied to the device. The RESET pin (active low) allows the user to reload the FPGA in case of a low digital supply voltage condition or a power supply glitch. Pulling the RESET pin low will pull the data ready and output bits high until the FPGA has been reloaded. The RESET pin should remain low for a minimum of 200 ns. On the rising edge of the reset pulse, the AD12400 will start loading the configuration into the FPGA. The reload process requires a maximum of 600 ms to complete. Valid signals on the data ready pins indicate that the reset process is complete. Also, system designers need be aware of the thermal conditions of the AD12400 at start-up. If large thermal imbalances are present, the AD12400 may require additional time to stabilize before providing specified image spur performance.
LEAD/LAG
The LEAD/LAG pin is used to synchronize the collection of data into external buffer memories. The LEAD/LAG pin can be applied synchronously or asynchronously to the AD12400. If applied asynchronously, LEAD/LAG must be held high for a minimum of 5 ns to ensure correct operation. The function will shut off DRA and DRB until the LEAD/LAG pin is released. DRA and DRB will resume on the next valid DRA after LEAD/LAG is released. If this feature is not required, tie this pin to DGND.
THERMAL CONSIDERATIONS
The module is rated to operate over a case temperature of 0C to 60C. In order to maintain the tight channel matching and reliability of the AD12400, care must be taken to assure that proper thermal and mechanical considerations have been made and addressed to assure case temperature is kept within this range. Each application will require evaluation of the thermal management as applicable to the system design. The following provides information that should be used in the evaluation of AD12400 thermal management for each specific use.
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AD12400
130 120 110 100 TYPICAL JUNCTION
PACKAGE INTEGRITY/MOUNTING GUIDELINES
The AD12400 is a printed circuit board (PCB) based module designed to provide mechanical stability and support the intricate channel-to-channel matching necessary to achieve high dynamic range performance. The module should be secured to the motherboard using 2-56 nuts (washer use is optional). The torque on the nuts should not exceed 32 inch ounces.
03735-0-019
TEMPERATURE (C)
90 80 70 60 50 40 30 20 NO AIR FLOW 100 LFM AIRFLOW CONDITION 300 LFM CASE
AMBIENT
Figure 21. Typical Temperature vs. Air Flow with No Module/Board Interface Material (Normalized to 60C Module Case Temperature)
130 120 110 100 TYPICAL JUNCTION
TEMPERATURE (C)
The SMA edge connectors (AIN, ENC/ENC) are surface mounted to the board in order to achieve minimum height of the module. When attaching and routing the cables, one must ensure they are stress-relieved and do not apply stress to the SMA connector/board. The presence of stress on the cables may degrade electrical performance and mechanical integrity of the module. In addition to the routing precautions, the smallest torque necessary to achieve consistent performance should be used to secure the system cable to the AD12400's SMA connectors. In no case should the torque exceed 5 inch pounds. Any disturbances to the AD12400 structure, including removing the covers or mounting screws, will invalidate the calibration and result in degraded performance. Refer to the Outline Dimensions section for mounting stud dimensions. Refer also to Figure 37 for PCB interface locations. Mounting stud length will typically accommodate a PCB thickness of 0.093". Consult the factory if board thickness requirements exceed this dimension.
90 80 70 60 50 40 30 20 NO AIR FLOW 100 LFM AIRFLOW CONDITION 300 LFM
03735-0-020
CASE
AMBIENT
Figure 22. Typical Temperature vs. Air Flow with T-FLEX Module/Board Interface Material (Normalized to 60C Module Case Temperature Ambient)
Rev. 0 | Page 18 of 28
AD12400
AD12400 EVALUATION KIT
The AD12400/KIT offers an easy way to evaluate the AD12400. The AD12400/KIT includes the AD12400KWS mounted on an adapter card, the AD12400 evaluation board, the power supply cables, a 225 MHz Buffer Memory FIFO board, and the Dual Analyzer software. The user must supply a clock source, an analog input source, a 1.5 V power supply, a 3.3 V power supply, a 5 V power supply, and a 3.8 V power supply. The clock source and analog input source connect directly to the AD12400KWS. The power supply cables (included) and a parallel port cable (not included) connect to the evaluation board.
Adapter Card
The AD12400KWS is attached to an adapter card that interfaces to the evaluation board through a 120-pin connector, P1, which is on the top side of the evaluation board.
Digital Post Processing Control
The AD12400 has a two-pin jumper labeled AFB that allows the user to enable/disable the digital post processing. The digital post processing is active when the AFB jumper is applied. When the jumper is removed, the FPGA is set to a pass through mode, which will demonstrate to the user the performance of the AD12400 without the digital post processing.
Power Connector
Power is supplied to the board via a detachable 12-lead power strip (three 4 pin blocks). Table 8. Power Connector
VA 3.8 V VC 3.3 V VD 1.5 V* VB 5.0 V Analog supply for the ADC (950 mA typical) Digital supply for the ADC outputs (200 mA typical) Digital supply for the FPGA (2.5 A max, 1.4 A typical) Digital supply for the Buffer memory board (400 mA typical)
RESET
The AD12400KWS's FPGA configuration is stored in an EEPROM and loaded into the FPGA when power is applied to the AD12400. The RESET switch, SW1 (active low), allows the user to reload the FPGA in case of a low voltage condition or a power supply glitch. Depressing the RESET switch will pull the data ready and output bits high. The RESET switch should remain low for a minimum of 200 ns. On the rising edge of the RESET pulse, the AD12400 will start loading the configuration into the on-module FPGA. The reload process requires a maximum of 600 ms to complete. Valid signals on the dataready pins indicate that the reset process is complete. The AD12400 is not compatible with the HSC-ADC-EVALDC/SC hardware or software.
*The power supply cable has approximately 100 mV drop. The VD supply current is dependent upon the analog input frequency. Refer to Figure 17.
Analog Input
The analog input source connects directly to an SMA on the AD12400KWS.
Encode
The single-ended or differential encode signal connects directly to SMA connector(s) on the AD12400KWS. A single-ended sine wave at 10 dBm connected to the Encode SMA is recommended. A low jitter clock source is recommended (<0.5 ps) to properly evaluate the AD12400.
Data Outputs
The AD12400KWS digital outputs are available at the 80-pin connector, P2, on the evaluation board. The AD12400/KIT comes with a Buffer Memory FIFO board connected to P2 that provides the interface to the parallel port of a PC. The Dual Analyzer software is compatible with Windows(R) 95, Windows(R) 98, Windows(R) 2000, and Windows NT(R). The Buffer Memory FIFO board can be removed and an external logic analyzer, or other data acquisition module, can be connected to this connector if required.
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AD12400
Table 9. Evaluation Board Bill of Materials
Item No. 1 2 3 4 5 6 7 8 9 Quantity 2 2 1 1 1 1 3 1 1 REF-DES C3, C5 C4, C6 R9 AFB P2 SW1 J2, J3, J4 P1 PCB
3.3VC
Device Capacitor Capacitor Resistor 2 Pin Header/Jumper 80 Pin Dual Connector Assemble Switch Push Button SPST 4 Pin Header Power Connecter 60 Pin Dual-Socket Assembly AD12400 Interface Bd GS08054
R8 4.02k
Package 603 805 603 Pin Strip Surface Mount 6 MM Pin Strip Surface Mount PCB
Value 0.1 F 25 V 10 F 6.3 V 4.02 k 1% Molex/GC/Weldon Post Header AMP Panasonic Wieland SAMTEC
SPARE1 AFB SPARE1 SPARE2 SPARE2
E14 E18
PASS R9 4.02k H/L_GAIN H/L_GAIN R10 4.02k NYQ NYQ R11 4.02k 3.3VC DITHER OTHER E12 E13 JP2 JP3
3.3VC
3.3VC
DGND
SELECT D 3.3VC DIGITAL J4 1 2 3 DGND 5V 4 AGND DIGITAL J3 1.5VD 1 2 3 4 DGND DGND DGND E22 3.3VC C6 10F 3.3VD C5 0.1F 2 3 EVQ-PAC85R
03735-0-021
3.8V +VA
ANALOG J2 1 2 3 4
5V C4 10F C3 0.1F
5V
SELECT D JP4 E17 E1
3.3VD
DGND
DGND RESET 1 4
DGND 1.5V SENSE
Figure 23. Evaluation Board
Rev. 0 | Page 20 of 28
AD12400
AD12400
P1:A 3.3VC RESET DNC DNC DNC DNC DNC DB11 DB11 DB9 DB9 DB7 DB7 DB5 DB5 DB3 DB3 DB1 DB1 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 121 GND 123 GND 2 3.3VC 4 6 DNC 8 10 DRB 12 14 DNC 16 DNC 18 20 DB10 22 24 DB8 26 28 DB6 30 32 DB4 34 36 DB2 38 40 DB0 122 GND 124 GND DGND 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 AMP104655-9 P2:D DA4 DGND QSE-60-01-L-D-A-K P1:B 1.5VD 41 43 45 47 49 DNC 51 53 DA11 55 57 DA9 59 61 DA7 63 65 DA5 67 69 DA3 71 73 DA1 75 77 LEAD/LAG 79 125 GND 127 GND DGND 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 126 GND 128 GND 1.5VD DA4 DA3 DA3 DA2 DA2 DA1 DA1 DA0 PASS DNC DA10 DA10 DA8 DA8 DA6 DA6 DA4 DA4 DA2 DA2 DA0 DA0 DRA DRA DGND DGND OR OR DA0 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 AMP104655-9 DB4 DB4 DB3 DB3 DB2 DB2 DB1 DB1 DB0 DB0 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 AMP104655-9 P2:C 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 AMP104655-9 P2:B P2:A
DRA DNC DRB DA11 DB10 DB8 DB6 DB4 DB2 DB0 DA10 DA10 DA9 DA9 DA8 DA8 DA7 DA7 DA6 DA6 DA5 DA5 DRA
DRB DRB
DA11
DB11 DB11 DB10 DB10 DB9 DB9 DB8 DB8 DB7 DB7 DB6 DB6 DB5 DB5
DNC DA11 DA9 DA7 DA5 DA3 DA1 DNC
OR OR
QSE-60-01-L-D-A-K P1:C 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 129 131 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 130 GND 132 GND
DGND
AGND
AGND
DNC DNC
WP 3.3VC DNC
DNC DNC DNC DNC DNC
DNC E2 E19
AGND +VA
AGND +VA
GND
AGND
QSE-60-01-L-D-A-K
AGND
Figure 24. Evaluation Board
Rev. 0 | Page 21 of 28
03735-0-022
AD12400
03735-0-023
Figure 25. Power Plane 1
Figure 27. First Ground Plane
03735-0-024
Figure 26. Power Plane 2 Figure 28. Second Ground Plane
Rev. 0 | Page 22 of 28
03735-0-026
03735-0-025
AD12400
03735-0-027
Figure 29. Top Side Copper
Figure 32. Top Silkscreen
03735-0-028
Figure 33. Bottom Silkscreen Figure 30. Bottom Side Copper
03735-0-029
Figure 31. Top Mask
Rev. 0 | Page 23 of 28
Figure 34. Evaluation Adapter Board--Top Silkscreen
03735-0-032
03735-0-031
03735-0-030
AD12400
Figure 35. Evaluation Adapter Board--Analog and Digital Layers
Figure 36. Evaluation Adapter Board--Bottom Silkscreen
03735-0-034
03735-0-033
Rev. 0 | Page 24 of 28
AD12400 LAYOUT GUIDELINES
The AD12400 requires a different approach to traditional high speed analog-to-digital converter system layouts. While the AD12400's internal PCB isolates digital and analog grounds, these planes are tied together through the product's aluminum case structure. Therefore, the decision of isolating the analog and digital grounds on the system PCB has additional factors to consider. For example, if the AD12400 will be attached with conductive thermal interface material to the system PCB, there will be essentially no benefit to keeping the analog and digital ground planes separate. If either no thermal interface material or nonconductive interface material is used, system architects will have to consider the ground loop that will be created if analog and digital planes are tied together directly under the AD12400. This EMI based decision will have to be considered on a case-by-case basis and will be largely dependent on the other sources of EMI in the system. One critical consideration is that a 12-bit performance requirement (-74 dBc) will require keeping conducted EMI currents (referenced to the input of the AD12400) below 4.5 A. All of the characterization and testing of the AD12400 was performed using a system that isolated these ground planes. If thermal interface material is used in the final system design, the following layout factors will need to be considered: open solder mask on the area that contacts the interface material and the thickness of the ground plane. While this should be analyzed in each specific system design, the use of solder mask may negate any advantage achieved by using the thermal interface material, and its use should be carefully considered. The ground plane thickness will not have a major impact on the thermal performance, but if design margin is slight, additional thickness can yield incremental improvements.
PCB INTERFACE
Figure 37 provides the mounting hole footprint for assembling the AD12400 to the second-level assembly. The diagram is referenced to the center of the mating QTE connector. Refer to the QTE/QSE series connector documentation at www.samtec.com for the SMT footprint of the mating connector. The top view of the second-level assembly footprint provides a diagram of the second-level assembly locating tab locations for mating the SAMTEC QTE-060-01-L-A-K-TR terminal strip on the AD12400BWS to a QSE-060-01-L-A-K-TR socket on the second-level assembly. The diagram is referenced to the center of the QTE terminal strip on the AD12400BWS and the mounting holds for the screws, which will hold the AD12400BWS to the second-level assembly board. The relationship of these locating tabs is based on information provided by SAMTEC (connector supplier) and should be verified with SAMTEC by the customer. Mating and unmating forces--the knifing or peeling action of applying force to one end or one side--must be avoided to prevent damage to the connector and guidepost.
Rev. 0 | Page 25 of 28
AD12400
1.184 [30.0673] 1.025 [26.0164] 2x
0, 0 DATUM = CENTER OF CONNECTOR .000 [.0000]
R.0470[R1.19] 6x 1.025 [26.0164] 2x 1.184 [30.0673]
2.159 [54.8258] 2x
0.396 [10.0456] 2x
0.000 [.0000] 0.105 [2.6670] 2x
Figure 37. Top View of Interface PCB Assembly
Rev. 0 | Page 26 of 28
03735-0-035
AD12400 OUTLINE DIMENSIONS
3.190 TYP 2.890 MAX BOARD
PIN 1 AIN
2.590 MAX
2.060 2.040
2.328 TYP
ENC ENC
0.856 TYP
TOP VIEW
0.267 TYP
0.256 TYP
SIDE VIEW JOHNSON SMA-50 OHM CONNECT NO. 142-0711-821
0.700 MAX 2-56 STUDS 4x 0.175 TYP
0.600 MAX
0.200 TYP
SAMTEC CONNECTOR QTE-060-01-L-D-A-K-TR
2.060 2.040
0.270 2x
0.505 TYP 2x
1.773 1.753 BOTTOM VIEW
Figure 38. Outline Dimensions Dimensions shown in inches Tolerances: 0.xx = 10 mils 0.xxx = 5 mils
ORDERING GUIDE
Model AD12400KWS AD12400JWS AD12400/KIT Temperature Range 0C to 60C (Case) 0C to 60C (Case) 25C Package Description 2.9" x 2.6" x 0.6" 2.9" x 2.6" x 0.6" Evaluation Kit
Rev. 0 | Page 27 of 28
AD12400
(c) 2003 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C03735-0-11/03(0)
Rev. 0 | Page 28 of 28

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