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| TPA6211A1 www.ti.com SLOS367B - AUGUST 2003 - REVISED AUGUST 2004 3.1-W MONO FULLY DIFFERENTIAL AUDIO POWER AMPLIFIER FEATURES * * * * * * Designed for Wireless or Cellular Handsets and PDAs 3.1 W Into 3 From a 5-V Supply at THD = 10% (Typ) Low Supply Current: 4 mA Typ at 5 V Shutdown Current: 0.01 A Typ Fast Startup With Minimal Pop Only Three External Components - Improved PSRR (-80 dB) and Wide Supply Voltage (2.5 V to 5.5 V) for Direct Battery Operation - Fully Differential Design Reduces RF Rectification - -63 dB CMRR Eliminates Two Input Coupling Capacitors APPLICATIONS * Ideal for Wireless Handsets, PDAs, and Notebook Computers DESCRIPTION The TPA6211A1 is a 3.1-W mono fully-differential amplifier designed to drive a speaker with at least 3- impedance while consuming only 20 mm2 total printed-circuit board (PCB) area in most applications. The device operates from 2.5 V to 5.5 V, drawing only 4 mA of quiescent supply current. The TPA6211A1 is available in the space-saving 3-mm x 3-mm QFN (DRB) and the 8-pin MSOP (DGN) PowerPADTM packages. Features like -80 dB supply voltage rejection from 20 Hz to 2 kHz, improved RF rectification immunity, small PCB area, and a fast startup with minimal pop makes the TPA6211A1 ideal for PDA/smart phone applications. 8-PIN QFN (DRB) PACKAGE (TOP VIEW) To Battery Cs SHUTDOWN BYPASS IN+ 1 2 3 4 8V O7 GND 6 VDD 5 VO+ APPLICATION CIRCUIT VDD 40 k In From DAC RI 4 3 ININ+ 40 k 1 _ + GND 7 VO+ VO5 8 6 IN- + RI DGN PACKAGE (TOP VIEW) SHUTDOWN BYPASS IN+ IN1 2 3 4 8 7 6 5 VOGND VDD VO+ SHUTDOWN Bias Circuitry 100 k C(BYPASS)(1) 2 (1) C(BYPASS) is optional. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2003-2004, Texas Instruments Incorporated TPA6211A1 SLOS367B - AUGUST 2003 - REVISED AUGUST 2004 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION PACKAGED DEVICES (1) TA -40C to 85C (1) SMALL OUTLINE (DRB) TPA6211A1DRB MSOP PowerPADTM (DGN) TPA6211A1DGN EVALUATION MODULES TPA6211A1EVM The DGN and DRB are available taped and reeled. To order taped and reeled parts, add the suffix R to the part number (TPA6211A1DGNR or TPA6211A1DRBR). Terminal Functions TERMINAL NAME ININ+ VDD VO+ GND VOSHUTDOWN BYPASS Thermal Pad DRB, DGN 4 3 6 5 7 8 1 2 I/O I I I O I O I Negative differential input Positive differential input Power supply Positive BTL output High-current ground Negative BTL output Shutdown terminal (active low logic) Mid-supply voltage, adding a bypass capacitor improves PSRR Connect to ground. Thermal pad must be soldered down in all applications to properly secure device on the PCB. DESCRIPTION ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted (1) UNIT VDD VI TA TJ Tstg Supply voltage Input voltage Continuous total power dissipation Operating free-air temperature Junction temperature Storage temperature DRB DGN -0.3 V to 6 V -0.3 V to VDD + 0.3 V See Dissipation Rating Table -40C to 85C -40C to 150C -65C to 85C 260C 235C Lead temperature 1,6 mm (1/16 Inch) from case for 10 seconds (1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. PACKAGE DISSIPATION RATINGS PACKAGE DGN DRB (1) TA 25C POWER RATING 2.13 W 2.7 W DERATING FACTOR (1) 17.1 mW/C 21.8 mW/C TA= 70C POWER RATING 1.36 W 1.7 W TA= 85C POWER RATING 1.11 W 1.4 W Derating factor based on high-k board layout. 2 TPA6211A1 www.ti.com SLOS367B - AUGUST 2003 - REVISED AUGUST 2004 RECOMMENDED OPERATION CONDITIONS MIN VDD VIH VIL TA Supply voltage High-level input voltage Low-level input voltage Operating free-air temperature SHUTDOWN SHUTDOWN -40 2.5 1.55 0.5 85 TYP MAX 5.5 UNIT V V V C ELECTRICAL CHARACTERISTICS TA = 25C PARAMETER VOS PSRR VIC CMRR Output offset voltage (measured differentially) Power supply rejection ratio Common mode input range Common mode rejection ratio TEST CONDITIONS VI = 0 V differential, Gain = 1 V/V, VDD = 5.5 V VDD = 2.5 V to 5.5 V VDD = 2.5 V to 5.5 V VDD = 5.5 V, VDD = 2.5 V, RL = 4 , VIN+ = VDD, VIN+ = 0 V, RL = 4 , VIN+ = VDD, VIN- = VDD VDD = 5.5 V, VDD = 5.5 V, VIC = 0.5 V to 4.7 V VIC = 0.5 V to 1.7 V VDD = 5.5 V Gain = 1 V/V, VIN- = 0 V or VDD = 3.6 V VIN- = VDD VDD = 2.5 V VDD = 5.5 V Gain = 1 V/V, VIN- = 0 V or VDD = 3.6 V VIN+ = 0 V VDD = 2.5 V VI = 5.8 V VI = -0.3 V 0.5 -63 -63 0.45 0.37 0.26 4.95 3.18 2 2.13 58 3 4 0.01 38 kh RI 40 kh RI MIN -9 TYP 0.3 -85 MAX 9 -60 VDD-0.8 -40 -40 UNIT mV dB V dB Low-output swing V 0.4 V 100 100 5 1 42 kh RI High-output swing | IIH | | IIL | IQ I(SD) High-level input current, shutdown Low-level input current, shutdown Quiescent current Supply current Gain Resistance from shutdown to GND A A mA A V/V k VDD = 2.5 V to 5.5 V, no load V(SHUTDOWN) 0.5 V, VDD = 2.5 V to 5.5 V, RL = 4 RL = 4 100 3 TPA6211A1 SLOS367B - AUGUST 2003 - REVISED AUGUST 2004 www.ti.com OPERATING CHARACTERISTICS TA = 25C, Gain = 1 V/V PARAMETER TEST CONDITIONS VDD = 5 V THD + N= 1%, f = 1 kHz, RL = 3 VDD = 3.6 V VDD = 2.5 V VDD = 5 V PO Output power THD + N= 1%, f = 1 kHz, RL = 4 VDD = 3.6 V VDD = 2.5 V VDD = 5 V THD + N= 1%, f = 1 kHz, RL = 8 PO = 2 W f = 1 kHz, RL = 3 PO = 1 W PO = 300 mW THD+N Total harmonic distortion plus noise PO = 1.8 W f = 1 kHz, RL = 4 PO = 0.7 W PO = 300 mW PO = 1 W f = 1 kHz, RL = 8 PO = 0.5 W PO = 200 mW kSVR SNR Vn CMRR ZI Supply ripple rejection ratio Signal-to-noise ratio Output voltage noise Common mode rejection ratio Input impedance Start-up time from shutdown VDD = 3.6 V, No CBYPASS VDD = 3.6 V, CBYPASS = 0.1 F VDD = 3.6 V, Inputs ac-grounded with Ci = 2 F, V(RIPPLE) = 200 mVpp VDD = 5 V, PO = 2 W, RL = 4 VDD = 3.6 V, f = 20 Hz to 20 kHz, Inputs ac-grounded with Ci = 2 F VDD = 3.6 V, VIC = 1 Vpp No weighting A weighting f = 217 Hz 38 VDD = 3.6 V VDD = 2.5 V VDD = 5 V VDD = 3.6 V VDD = 2.5 V VDD = 5 V VDD = 3.6 V VDD = 2.5 V VDD = 5 V VDD = 3.6 V VDD = 2.5 V f = 217 Hz f = 20 Hz to 20 kHz MIN TYP 2.45 1.22 0.49 2.22 1.1 0.47 1.36 0.72 0.33 0.045% 0.05% 0.06% 0.03% 0.03% 0.04% 0.02% 0.02% 0.03% -80 -70 105 15 12 -65 40 4 27 44 dB dB VRMS dB k s ms W MAX UNIT 4 TPA6211A1 www.ti.com SLOS367B - AUGUST 2003 - REVISED AUGUST 2004 TYPICAL CHARACTERISTICS Table of Graphs FIGURE PO PD THD+N KSVR KSVR Output power Power dissipation Total harmonic distortion + noise Supply voltage rejection ratio Supply voltage rejection ratio GSM Power supply rejection GSM Power supply rejection CMRR Common-mode rejection ratio Closed loop gain/phase Open loop gain/phase IDD Supply current Start-up time vs Supply voltage vs Load resistance vs Output power vs Output power vs Frequency vs Common-mode input voltage vs Frequency vs Common-mode input voltage vs Time vs Frequency vs Frequency vs Common-mode input voltage vs Frequency vs Frequency vs Supply voltage vs Shutdown voltage vs Bypass capacitor 1 2 3, 4 5, 6, 7 8-12 13 14, 15, 16, 17 18 19 20 21 22 23 24 25 26 27 OUTPUT POWER vs SUPPLY VOLTAGE 3.5 f = 1 kHz Gain = 1 V/V PO = 3 , THD 10% PO = 4 , THD 10% P - Output Power - W O P - Output Power - W O 2.5 PO = 3 , THD 1% PO = 4 , THD 1% 2 1.5 PO = 8 , THD 10% PO = 8 , THD 1% 2.5 3.5 OUTPUT POWER vs LOAD RESISTANCE f = 1 kHz Gain = 1 V/V VDD = 5 V, THD 10% 3 VDD = 5 V, THD 1% VDD = 3.6 V, THD 10% 2 VDD = 3.6 V, THD 1% 1.5 1 3 VDD = 2.5 V, THD 10% VDD = 2.5 V, THD 1% 1 0.5 0 2.5 0.5 0 3 3.5 4 VDD - Supply Voltage - V 4.5 5 3 8 13 18 23 28 RL - Load Resistance - Figure 1. Figure 2. 5 TPA6211A1 SLOS367B - AUGUST 2003 - REVISED AUGUST 2004 www.ti.com POWER DISSIPATION vs OUTPUT POWER 0.8 VDD = 3.6 V 0.7 P - Power Dissiaption - W D 4 P - Power Dissiaption - W D 0.6 0.5 0.4 8 0.3 0.2 0.1 0 1 0.8 1.2 1.4 VDD = 5 V POWER DISSIPATION vs OUTPUT POWER 4 8 0.6 0.4 0.2 0 0.3 0.6 0.9 1.2 PO - Output Power - W 1.5 1.8 0 0 0.3 0.6 0.9 1.2 PO - Output Power - W 1.5 1.8 Figure 3. TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER 10 THD+N - Total Harmonic Distortion + Noise - % THD+N - Total Harmonic Distortion + Noise - % 5 2 1 0.5 0.2 0.1 0.05 0.02 0.01 20m 50m 100m 200m 500m 1 2 3 PO - Output Power - W 2.5 V RL = 3 , C(BYPASS) = 0 to 1 F, Gain = 1 V/V 20 10 5 2 1 0.5 Figure 4. TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER RL = 4 , C(BYPASS) = 0 to 1 F, Gain = 1 V/V 2.5 V 0.2 0.1 0.05 0.02 0.01 10m 20m 3.6 V 3.6 V 5V 5V 50m 100m 200m 500m 1 PO - Output Power - W 23 Figure 5. Figure 6. 6 TPA6211A1 www.ti.com SLOS367B - AUGUST 2003 - REVISED AUGUST 2004 TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER 20 THD+N - Total Harmonic Distortion + Noise - % THD+N - Total Harmonic Distortion + Noise - % 10 5 2 1 0.5 0.2 0.1 0.05 0.02 0.01 10m 20m 50m 100m 200m 500m 1 PO - Output Power - W 23 5V 2.5 V 3.6 V RL = 8 , C(BYPASS) = 0 to 1 F, Gain = 1 V/V 10 5 2 1 0.5 TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY VDD = 5 V, RL = 3 ,, C(BYPASS) = 0 to 1 F, Gain = 1 V/V, CI = 2 F 1W 0.2 0.1 2W 0.05 0.02 0.01 0.005 20 50 100 200 500 1k 2k f - Frequency - Hz 5k 10k 20k Figure 7. TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY 10 THD+N - Total Harmonic Distortion + Noise - % THD+N - Total Harmonic Distortion + Noise - % 5 2 1 0.5 1.8 W 0.2 1W 0.1 0.05 0.02 0.01 0.005 20 50 100 200 500 1k 2k f - Frequency - Hz 5k 10k 20k VDD = 5 V, RL = 4 ,, C(BYPASS) = 0 to 1 F, Gain = 1 V/V, CI = 2 F 2W 10 5 2 1 0.5 0.2 0.1 0.05 0.02 0.01 0.005 0.002 0.001 20 50 Figure 8. TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY VDD = 3.6 V, RL = 4 ,, C(BYPASS) = 0 to 1 F, Gain = 1 V/V, CI = 2 F 0.1 W 0.5 W 1W 100 200 500 1k 2k f - Frequency - Hz 5k 10k 20k Figure 9. Figure 10. 7 TPA6211A1 SLOS367B - AUGUST 2003 - REVISED AUGUST 2004 www.ti.com TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY 10 THD+N - Total Harmonic Distortion + Noise - % 5 2 1 0.5 0.4 W 0.2 0.1 0.05 0.02 0.01 0.005 0.002 0.001 20 50 100 200 500 1k 2k f - Frequency - Hz 5k 10k 20k 0.28 W THD+N - Total Harmonic Distortion + Noise - % VDD = 2.5 V, RL = 4 ,, C(BYPASS) = 0 to 1 F, Gain = 1 V/V, CI = 2 F 10 5 2 1 0.5 0.2 0.1 0.05 0.02 0.01 0.005 0.002 0.001 20 TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY VDD = 3.6 V, RL = 8 ,, C(BYPASS) = 0 to 1 F, Gain = 1 V/V, CI = 2 F 0.25 W 0.6 W 0.1 W 50 100 200 500 1k 2k f - Frequency - Hz 5k 10k 20k Figure 11. TOTAL HARMONIC DISTORTION + NOISE vs COMMON MODE INPUT VOLTAGE 0.06 THD+N - Total Harmonic Distortion + Noise - % k SVR - Supply Voltage Rejection Ratio - dB 0.058 0.056 0.054 0.052 0.05 0.048 0.046 0.044 0.042 0.04 0 1 2 3 4 VIC - Common Mode Input Voltage - V 5 VDD = 3.6 V VDD = 2.5 V VDD = 5 V f = 1 kHz PO = 200 mW, RL = 1 kHz +0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 20 50 100 200 Figure 12. SUPPLY VOLTAGE REJECTION RATIO vs FREQUENCY RL = 4 ,, C(BYPASS) = 0.47 F, Gain = 1 V/V, CI = 2 F, Inputs ac Grounded VDD = 3.6 V VDD = 2.5 V VDD = 5 V 500 1k 2k 5k 10k 20k f - Frequency - Hz Figure 13. Figure 14. 8 TPA6211A1 www.ti.com SLOS367B - AUGUST 2003 - REVISED AUGUST 2004 SUPPLY VOLTAGE REJECTION RATIO vs FREQUENCY +0 k SVR - Supply Voltage Rejection Ratio - dB -10 -20 -30 -40 -50 -60 -70 -80 VDD = 5 V -90 -100 20 50 100 200 500 1k 2k 5k 10k 20k VDD = 2.5 V VDD = 3.6 V k SVR - Supply Voltage Rejection Ratio - dB RL = 4 ,, C(BYPASS) = 0.47 F, Gain = 5 V/V, CI = 2 F, Inputs ac Grounded +0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 20 SUPPLY RIPPLE REJECTION RATIO vs FREQUENCY RL = 4 ,, C(BYPASS) = 0.47 F, CI = 2 F, VDD = 2.5 V to 5 V Inputs Floating 50 100 200 500 1k 2k 5k 10k 20k f - Frequency - Hz f - Frequency - Hz Figure 15. SUPPLY VOLTAGE REJECTION RATIO vs FREQUENCY +0 k SVR - Supply Voltage Rejection Ratio - dB -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 20 C(BYPASS) = 1 F C(BYPASS) = 0.47 F 50 100 200 500 1k 2k 5k 10k 20k C(BYPASS) = 0.1 F No C(BYPASS) k SVR - Supply Voltage Rejection Ratio - dB RL = 4 ,, CI = 2 F, Gain = 1 V/V, VDD = 3.6 V 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 0 1 VDD = 2.5 V Figure 16. SUPPLY VOLTAGE REJECTION RATIO vs DC COMMON MODE INPUT RL = 4 ,, CI = 2 F, Gain = 1 V/V, C(BYPASS) = 0.47 F VDD = 3.6 V, f = 217 Hz, Inputs ac Grounded VDD = 3.6 V VDD = 5 V f - Frequency - Hz 2 3 4 DC Common Mode Input - V 5 6 Figure 17. Figure 18. 9 TPA6211A1 SLOS367B - AUGUST 2003 - REVISED AUGUST 2004 www.ti.com GSM POWER SUPPLY REJECTION vs TIME VDD C1 Frequency 217 Hz C1 - Duty 20% C1 Pk-Pk 500 mV Voltage - V RL = 8 VOUT CI = 2.2 F C(BYPASS) = 0.47 F Ch1 100 mV/div Ch4 10 mV/div t - Time - ms 2 ms/div Figure 19. GSM POWER SUPPLY REJECTION vs FREQUENCY VDD - Supply Voltage - dBV 0 -50 -100 VO - Output Voltage - dBV VDD Shown in Figure 19, RL = 8 , CI = 2.2 F, Inputs Grounded -150 -100 -120 -140 -160 -180 0 C(BYPASS) = 0.47 F 400 800 1200 f - Frequency - Hz 1600 2000 Figure 20. 10 TPA6211A1 www.ti.com SLOS367B - AUGUST 2003 - REVISED AUGUST 2004 COMMON MODE REJECTION RATIO vs FREQUENCY +0 CMRR - Common-Mode Rejection Ratio - dB -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 20 50 100 200 500 1k 2k 5k 10k 20k f - Frequency - Hz VDD = 5 V VDD = 2.5 V RL = 4 ,, VIC = 200 mV Vp-p, Gain = 1 V/V, 0 CMRR - Common Mode Rejection Ratio - dB -10 -20 -30 -40 -50 -60 -70 -80 -90 0 COMMON-MODE REJECTION RATIO vs COMMON-MODE INPUT VOLTAGE RL = 4 ,, Gain = 1 V/V, dc Change in VIC VDD = 2.5 V VDD = 3.5 V VDD = 5 V 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VIC - Common Mode Input Voltage - V Figure 21. CLOSED LOOP GAIN/PHASE vs FREQUENCY 40 30 20 10 0 Gain - dB -10 -20 -30 -40 -50 -60 -70 -80 1 10 100 1 k 10 k 100 k f - Frequency - Hz 1M 10 M VDD = 5 V RL = 8 AV = 1 Gain Phase 180 150 120 90 Phase - Degrees 60 30 0 -30 -60 -90 -120 -150 -180 Figure 22. OPEN LOOP GAIN/PHASE vs FREQUENCY 100 90 80 70 60 50 Gain - dB 40 30 20 10 0 -10 -20 -30 -40 100 1k 10 k 100 k f - Frequency - Hz Phase Gain 30 0 -30 -60 -90 -120 -150 -180 1M Phase - Degrees 60 VDD = 5 V, RL = 8 180 150 120 90 Figure 23. Figure 24. 11 TPA6211A1 SLOS367B - AUGUST 2003 - REVISED AUGUST 2004 www.ti.com SUPPLY CURRENT vs SUPPLY VOLTAGE 5 4.5 I DD - Supply Current - mA 4 3.5 3 TA = -40C 2.5 2 1.5 1 0.5 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 0.00001 0 TA = 25C I DD - Supply Current - mA VDD = 5 V 10 TA = 125C 1 SUPPLY CURRENT vs SHUTDOWN VOLTAGE VDD = 5 V VDD = 3.6 V 0.1 VDD = 2.5 V 0.01 0.001 0.0001 VDD - Supply Voltage - V 1 2 3 4 5 Voltage on SHUTDOWN Terminal - V Figure 25. START-UP TIME vs BYPASS CAPACITOR 300 Figure 26. 250 Start-Up Time - ms 200 150 100 50 0 0 0.2 0.4 0.6 0.8 C(Bypass) - Bypass Capacitor - F 1 Figure 27. 12 TPA6211A1 www.ti.com SLOS367B - AUGUST 2003 - REVISED AUGUST 2004 APPLICATION INFORMATION * FULLY DIFFERENTIAL AMPLIFIER The TPA6211A1 is a fully differential amplifier with differential inputs and outputs. The fully differential amplifier consists of a differential amplifier and a common- mode amplifier. The differential amplifier ensures that the amplifier outputs a differential voltage that is equal to the differential input times the gain. The common-mode feedback ensures that the common-mode voltage at the output is biased around VDD/2 regardless of the common- mode voltage at the input. Advantages of Fully Differential Amplifiers * Input coupling capacitors not required: A fully differential amplifier with good CMRR, like the TPA6211A1, allows the inputs to be biased at voltage other than mid-supply. For example, if a DAC has a lower mid-supply voltage than that of the TPA6211A1, the common-mode feedback circuit compensates, and the outputs are still biased at the mid-supply point of the TPA6211A1. The inputs of the TPA6211A1 can be biased from 0.5 V to VDD - 0.8 V. If the inputs are biased outside of that range, input coupling capacitors are required. * Mid-supply bypass capacitor, C(BYPASS), not required: The fully differential amplifier does not require a bypass capacitor. Any shift in the mid-supply voltage affects both positive and negative channels equally, thus canceling at the differential output. Removing the bypass capacitor slightly worsens power supply rejection ratio (kSVR), but a slight decrease of kSVR may be acceptable when an additional component can be eliminated (See Figure 17). Better RF-immunity: GSM handsets save power by turning on and shutting off the RF transmitter at a rate of 217 Hz. The transmitted signal is picked-up on input and output traces. The fully differential amplifier cancels the signal much better than the typical audio amplifier. APPLICATION SCHEMATICS Figure 28 through Figure 31 show application schematics for differential and single-ended inputs. Typical values are shown in Table 1. Table 1. Typical Component Values COMPONENT RI C(BYPASS) CS CI (1) C(BYPASS) is optional. (1) VALUE 40 k 0.22 F 1 F 0.22 F VDD 6 40 k - RI In From DAC + RI 4 3 IN- IN+ 40 k 1 _ + GND 7 VO+ 5 VO- 8 Cs To Battery SHUTDOWN Bias Circuitry 100 k C(BYPASS)(1) 2 (1) C(BYPASS) is optional Figure 28. Typical Differential Input Application Schematic 13 TPA6211A1 SLOS367B - AUGUST 2003 - REVISED AUGUST 2004 www.ti.com VDD 6 40 k RI RI CI 1 4 3 IN- IN+ 40 k _ + GND 7 VO+ 5 VO- 8 Cs To Battery CI - + SHUTDOWN Bias Circuitry 100 k C(BYPASS)(1) 2 (1) C(BYPASS) is optional Figure 29. Differential Input Application Schematic Optimized With Input Capacitors VDD 6 40 k RI RI CI 4 3 IN- IN+ 40 k 1 _ + GND 7 VO+ 5 VO- 8 Cs To Battery CI IN SHUTDOWN Bias Circuitry 100 k C(BYPASS)(1) 2 (1) C(BYPASS) is optional Figure 30. Single-Ended Input Application Schematic 14 TPA6211A1 www.ti.com SLOS367B - AUGUST 2003 - REVISED AUGUST 2004 CF CF VDD 6 Ra - Ca CI 40 k RI RI Ra + Ca SHUTDOWN CI 4 3 IN- IN+ 40 k 1 _ + GND 7 VO+ 5 VO- 8 Cs To Battery Bias Circuitry 100 k C(BYPASS)(1) 2 (1) C(BYPASS) is optional Figure 31. Differential Input Application Schematic With Input Bandpass Filter Selecting Components Resistors (RI) The input resistor (RI) can be selected to set the gain of the amplifier according to equation 1. Gain = RF/RI (1) Input Capacitor (CI) The TPA6211A1 does not require input coupling capacitors when driven by a differential input source biased from 0.5 V to VDD - 0.8 V. Use 1% tolerance or better gain-setting resistors if not using input coupling capacitors. In the single-ended input application, an input capacitor, CI, is required to allow the amplifier to bias the input signal to the proper dc level. In this case, CI and RI form a high-pass filter with the corner frequency defined in Equation 2. 1 fc 2h R C II (2) The internal feedback resistors (RF) are trimmed to 40 k. Resistor matching is very important in fully differential amplifiers. The balance of the output on the reference voltage depends on matched ratios of the resistors. CMRR, PSRR, and the cancellation of the second harmonic distortion diminishes if resistor mismatch occurs. Therefore, 1%-tolerance resistors or better are recommended to optimize performance. Bypass Capacitor (CBYPASS) and Start-Up Time The internal voltage divider at the BYPASS pin of this device sets a mid-supply voltage for internal references and sets the output common mode voltage to VDD/2. Adding a capacitor filters any noise into this pin, increasing kSVR. C(BYPASS)also determines the rise time of VO+ and VO- when the device exits shutdown. The larger the capacitor, the slower the rise time. -3 dB fc 15 TPA6211A1 SLOS367B - AUGUST 2003 - REVISED AUGUST 2004 www.ti.com The value of CI is an important consideration. It directly affects the bass (low frequency) performance of the circuit. Consider the example where RI is 10 k and the specification calls for a flat bass response down to 100 Hz. Equation 2 is reconfigured as Equation 3. 1 C I 2h R f c I (3) In this example, CI is 0.16 F, so the likely choice ranges from 0.22 F to 0.47 F. Ceramic capacitors are preferred because they are the best choice in preventing leakage current. When polarized capacitors are used, the positive side of the capacitor faces the amplifier input in most applications. The input dc level is held at VDD/2, typically higher than the source dc level. It is important to confirm the capacitor polarity in the application. Band-Pass Filter (Ra, Ca, and Ca) It may be desirable to have signal filtering beyond the one-pole high-pass filter formed by the combination of CI and RI. A low-pass filter may be added by placing a capacitor (CF) between the inputs and outputs, forming a band-pass filter. An example of when this technique might be used would be in an application where the desirable pass-band range is between 100 Hz and 10 kHz, with a gain of 4 V/V. The following equations illustrate how the proper values of CF and CI can be determined. Step 1: Low-Pass Filter Substituting RI into equation 6. 1 f c(HPF) 2 10 kh C I Therefore, C I 1 2 10 kh f c(HPF) (8) (9) Substituting 100 Hz for fc(HPF) and solving for CI: CI = 0.16 F At this point, a first-order band-pass filter has been created with the low-frequency cutoff set to 100 Hz and the high-frequency cutoff set to 10 kHz. The process can be taken a step further by creating a second-order high-pass filter. This is accomplished by placing a resistor (Ra) and capacitor (Ca) in the input path. It is important to note that Ra must be at least 10 times smaller than RI; otherwise its value has a noticeable effect on the gain, as Ra and RI are in series. Step 3: Additional Low-Pass Filter Ra must be Set Ra = 1 k f c(LPF) at least 10x smaller than RI, 1 2h R a Ca 1 2h 1k f (10) Therefore, Ca c(LPF) (11) 1 c(LPF) 2RC FF where R is the internal 40 kh resistor F 1 f c(LPF) 2 40 kh C F f Substituting 10 kHz for fc(LPF) and solving for Ca: (4) (5) Ca = 160 pF Figure 32 is a bode plot for the band-pass filter in the previous example. Figure 31 shows how to configure the TPA6211A1 as a band-pass filter. AV Therefore, C F 1 2 40 kh f c(LPF) (6) 12 dB 9 dB Substituting 10 kHz for fc(LPF) and solving for CF: CF = 398 pF Step 2: High-Pass Filter +20 dB/dec -40 dB/dec -20 dB/dec 1 2h R C II where R is the input resistor I f c(HPF) fc(HPF) = 100 Hz fc(LPF) = 10 kHz f Figure 32. Bode Plot (7) Since the application in this case requires a gain of 4 V/V, RI must be set to 10 k. 16 TPA6211A1 www.ti.com SLOS367B - AUGUST 2003 - REVISED AUGUST 2004 Decoupling Capacitor (CS) The TPA6211A1 is a high-performance CMOS audio amplifier that requires adequate power supply decoupling to ensure the output total harmonic distortion (THD) is as low as possible. Power-supply decoupling also prevents oscillations for long lead lengths between the amplifier and the speaker. For higher frequency transients, spikes, or digital hash on the line, a good low equivalent-series-resistance (ESR) ceramic capacitor, typically 0.1 F to 1 F, placed as close as possible to the device VDD lead works best. For filtering lower frequency noise signals, a 10-F or greater capacitor placed near the audio power amplifier also helps, but is not required in most applications because of the high PSRR of this device. V (rms) V O(PP) 22 V Power 2 (rms) R L VDD (12) VO(PP) RL VDD 2x VO(PP) USING LOW-ESR CAPACITORS Low-ESR capacitors are recommended throughout this applications section. A real (as opposed to ideal) capacitor can be modeled simply as a resistor in series with an ideal capacitor. The voltage drop across this resistor minimizes the beneficial effects of the capacitor in the circuit. The lower the equivalent value of this resistance the more the real capacitor behaves like an ideal capacitor. -VO(PP) Figure 33. Differential Output Configuration In a typical wireless handset operating at 3.6 V, bridging raises the power into an 8- speaker from a singled-ended (SE, ground reference) limit of 200 mW to 800 mW. This is a 6-dB improvement in sound power--loudness that can be heard. In addition to increased power, there are frequency-response concerns. Consider the single-supply SE configuration shown in Figure 34. A coupling capacitor (CC) is required to block the dc-offset voltage from the load. This capacitor can be quite large (approximately 33 F to 1000 F) so it tends to be expensive, heavy, occupy valuable PCB area, and have the additional drawback of limiting low-frequency performance. This frequency-limiting effect is due to the high-pass filter network created with the speaker impedance and the coupling capacitance. This is calculated with Equation 13. 1 fc 2h R C LC (13) For example, a 68-F capacitor with an 8- speaker would attenuate low frequencies below 293 Hz. The BTL configuration cancels the dc offsets, which eliminates the need for the blocking capacitors. Low-frequency performance is then limited only by the input network and speaker response. Cost and PCB space are also minimized by eliminating the bulky coupling capacitor. DIFFERENTIAL OUTPUT VERSUS SINGLE-ENDED OUTPUT Figure 33 shows a Class-AB audio power amplifier (APA) in a fully differential configuration. The TPA6211A1 amplifier has differential outputs driving both ends of the load. One of several potential benefits to this configuration is power to the load. The differential drive to the speaker means that as one side is slewing up, the other side is slewing down, and vice versa. This in effect doubles the voltage swing on the load as compared to a ground-referenced load. Plugging 2 x VO(PP) into the power equation, where voltage is squared, yields 4x the output power from the same supply rail and load impedance Equation 12. 17 TPA6211A1 SLOS367B - AUGUST 2003 - REVISED AUGUST 2004 www.ti.com VDD VO(PP) CC RL VO(PP) An easy-to-use equation to calculate efficiency starts out as being equal to the ratio of power from the power supply to the power delivered to the load. To accurately calculate the RMS and average values of power in the load and in the amplifier, the current and voltage waveform shapes must first be understood (see Figure 35). VO -3 dB V(LRMS) IDD fc Figure 34. Single-Ended Output and Frequency Response Increasing power to the load does carry a penalty of increased internal power dissipation. The increased dissipation is understandable considering that the BTL configuration produces 4x the output power of the SE configuration. IDD(avg) Figure 35. Voltage and Current Waveforms for BTL Amplifiers Although the voltages and currents for SE and BTL are sinusoidal in the load, currents from the supply are different between SE and BTL configurations. In an SE application the current waveform is a half-wave rectified shape, whereas in BTL it is a full-wave rectified waveform. This means RMS conversion factors are different. Keep in mind that for most of the waveform both the push and pull transistors are not on at the same time, which supports the fact that each amplifier in the BTL device only draws current from the supply for half the waveform. The following equations are the basis for calculating amplifier efficiency. FULLY DIFFERENTIAL AMPLIFIER EFFICIENCY AND THERMAL INFORMATION Class-AB amplifiers are inefficient, primarily because of voltage drop across the output-stage transistors. The two components of this internal voltage drop are the headroom or dc voltage drop that varies inversely to output power, and the sinewave nature of the output. The total voltage drop can be calculated by subtracting the RMS value of the output voltage from VDD. The internal voltage drop multiplied by the average value of the supply current, IDD(avg), determines the internal power dissipation of the amplifier. 18 TPA6211A1 www.ti.com SLOS367B - AUGUST 2003 - REVISED AUGUST 2004 P Efficiency of a BTL amplifier Where: L P SUP V P , therefore, P L 2 1 h hV P L V rms 2 L , and V LRMS R L V I V 2 P 2R L 1 h V P R L and P SUP Therefore, avg and I avg DD DD DD V DD P hR L VP 2 RL 2 V DD V P h RL 2 P sin(t) dt R 0 L [cos(t)] 0 h P hR L 2V 2V P SUP substituting PL and PSUP into equation 6, Efficiency of a BTL amplifier Where: h VP 4 VDD V P 2P R LL PL = Power delivered to load PSUP = Power drawn from power supply VLRMS = RMS voltage on BTL load RL = Load resistance VP = Peak voltage on BTL load IDDavg = Average current drawn from the power supply VDD = Power supply voltage BTL = Efficiency of a BTL amplifier (14) Therefore, h BTL 2P R LL 4V DD (15) Table 2. Efficiency and Maximum Ambient Temperature vs Output Power Output Power (W) 0.5 1 2.45 3.1 0.5 1 2 2.8 0.5 1 1.36 1.7 (1) (2) Efficiency (%) 27.2 38.4 60.2 67.7 31.4 44.4 62.8 74.3 44.4 62.8 73.3 81.9 Internal Dissipation (W) 1.34 1.60 1.62 1.48 1.09 1.25 1.18 0.97 5-V, 8- Systems 0.625 0.592 0.496 0.375 1.13 1.60 1.86 2.08 85 (2) 85 (2) 85 (2) 85 (2) Power From Supply (W) 1.84 2.60 4.07 4.58 5-V, 4- BTL Systems 1.59 2.25 3.18 3.77 85 (2) 85 (2) 85 (2) 85 (2) Max Ambient Temperature (C) 85 (2) 76 75 82 (1) 5-V, 3- Systems DRB package Package limited to 85C ambient 19 TPA6211A1 SLOS367B - AUGUST 2003 - REVISED AUGUST 2004 www.ti.com Table 2 employs Equation 15 to calculate efficiencies for four different output power levels. Note that the efficiency of the amplifier is quite low for lower power levels and rises sharply as power to the load is increased resulting in a nearly flat internal power dissipation over the normal operating range. Note that the internal dissipation at full output power is less than in the half power range. Calculating the efficiency for a specific system is the key to proper power supply design. For a 2.8-W audio system with 4- loads and a 5-V supply, the maximum draw on the power supply is almost 3.8 W. A final point to remember about Class-AB amplifiers is how to manipulate the terms in the efficiency equation to the utmost advantage when possible. Note that in Equation 15, VDD is in the denominator. This indicates that as VDD goes down, efficiency goes up. A simple formula for calculating the maximum power dissipated, PDmax, may be used for a differential output application: 2V2 DD P Dmax h 2R L (16) PDmax for a 5-V, 4- system is 1.27 W. The maximum ambient temperature depends on the heat sinking ability of the PCB system. The derating factor for the 3 mm x 3 mm DRB package is shown in the dissipation rating table. Converting this to JA: 1 1 45.9C W JA 0.0218 Derating Factor (17) Given JA, the maximum allowable junction temperature, and the maximum internal dissipation, the maximum ambient temperature can be calculated with Equation 18. The maximum recommended junction temperature for the TPA6211A1 is 150C. T A Max T J Max JA P Dmax 150 45.9(1.27) 91.7C (18) Equation 18 shows that the maximum ambient temperature is 91.7C (package limited to 85C ambient) at maximum power dissipation with a 5-V supply. Table 2 shows that for most applications no airflow is required to keep junction temperatures in the specified range. The TPA6211A1 is designed with thermal protection that turns the device off when the junction temperature surpasses 150C to prevent damage to the IC. In addition, using speakers with an impedance higher than 4- dramatically increases the thermal performance by reducing the output current. 20 TPA6211A1 www.ti.com SLOS367B - AUGUST 2003 - REVISED AUGUST 2004 PCB LAYOUT Use the following land pattern for board layout with the 8-pin QFN (DRB) package. Note that the solder paste should use a hatch pattern to fill solder paste at 50% to ensure that there is not too much solder paste under the package. 0.7 mm 1.4 mm 0.33 mm plugged vias (5 places) 0.38 mm 0.65 mm 1.95 mm Solder Mask: 1.4 mm x 1.85 mm centered in package Make solder paste a hatch pattern to fill 50% 3.3 mm Figure 36. TPA6211A1 8-Pin QFN (DRB) Board Layout (Top View) 21 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. 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