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INTEGRATED CIRCUITS
DATA SHEET
TDA8769 12-bit, 60/80/105 Msps Analog-to-Digital Converter (ADC) Nyquist/high IF sampling
Objective specification Supersedes data of 2003 Apr 07 2003 Dec 09
Philips Semiconductors
Objective specification
12-bit, 60/80/105 Msps Analog-to-Digital Converter (ADC) Nyquist/high IF sampling
CONTENTS 1 2 3 4 5 6 7 8 9 10 11 11.1 11.2 11.3 11.4 11.5 11.5.1 11.5.1.1 11.5.1.2 11.5.2 11.5.2.1 11.5.2.2 11.5.2.3 11.5.2.4 11.5.2.5 11.5.2.6 FEATURES APPLICATIONS GENERAL DESCRIPTION QUICK REFERENCE DATA ORDERING INFORMATION BLOCK DIAGRAM PINNING LIMITING VALUES THERMAL CHARACTERISTICS CHARACTERISTICS APPLICATION INFORMATION Output coding and control signals TDA8769 in 3G radio receivers Application diagrams Demonstration board Definitions Static parameters Integral non-linearity (INL) Differential non-linearity (DNL) Dynamic parameters Signal-to-noise and distortion (SINAD) Effective number of bits (ENOB) Total harmonic distortion (THD) Signal-to-noise ratio (SNR) Spurious free dynamic range (SFDR) Intermodulation distortion (IMD2 and IMD3) 12 13 13.1 13.2 13.3 13.4 13.5 14 15 16 PACKAGE OUTLINE SOLDERING
TDA8769
Introduction to soldering surface mount packages Reflow soldering Wave soldering Manual soldering Suitability of surface mount IC packages for wave and reflow soldering methods DATA SHEET STATUS DEFINITIONS DISCLAIMERS
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Philips Semiconductors
Objective specification
12-bit, 60/80/105 Msps Analog-to-Digital Converter (ADC) Nyquist/high IF sampling
1 FEATURES
TDA8769
* Advanced Frequency Modulation (FM) radio * Imaging (camera scanner and medical) * Cable modem or set top box * Radar and satellite hub systems. 3 GENERAL DESCRIPTION
* 12-bit resolution * Optimized for both Nyquist and high IF sampling * High-speed sampling rate up to 105 MHz * Maximum analog input frequency of 330 MHz (see Application section) * Only 2 clock cycles latency * 5 V power supplies and 3.3 V output power supply * Binary or two's-complement CMOS outputs * Programmable Complete Conversion Signal (CCS) CMOS output * In-range CMOS compatible output * CMOS compatible static digital inputs * LVTTL and LVCMOS compatible digital outputs * Differential clock input PECL; sine wave and TTL compatible * Integrated track-and-hold amplifier * Differential analog input * External amplitude range control * Full-scale controllable from 1.5 to 1.9 V (p-p) * Voltage controlled regulator included * Temperature range from -40 to +85 C. 2 APPLICATIONS
The TDA8769 is a BiCMOS 12-bit Analog-to-Digital Converter (ADC) optimized for GSM/EDGE, W-CDMA and CDMA2000 radio transceivers, high data rate radios and other applications such as advanced FM radio and professional imaging. Its main innovation is the RF sampling, based on a high-speed clock of up to 105 Msps combined with high input frequencies of up to 250 MHz. It converts the analog input signal into 12-bit binary coded digital words at a maximum sampling rate of 105 MHz. The TDA8769 analog performances have been proven in various multi-carrier 3G radio receivers, providing the best-in-class Adjacent Channel Selectivity (ACS) up to 80 dB. Moreover the TDA8769 offers the lowest clock cycle latency, which enables competitive and optimized feedback loops in controlled systems. All static digital inputs (TH, CEN, OTC, DEL0 and DEL1) are CMOS compatible and all outputs are LVTTL and LVCMOS compatible. A sine wave clock input signal can also be used. 4 Tbf. QUICK REFERENCE DATA
* Cellular infrastructure (2.5G, 3G, etc.) * Base stations and "Zero-IF" or direct IF sampling subsystems * Wireless and wired broadband communications * Wireless Local Loop (WLL) * Local Multipoint Distribution Service (LMDS) 5 ORDERING INFORMATION
PACKAGE TYPE NUMBER NAME TDA8769HW/6 TDA8769HW/8 TDA8769HW/10 HTQFP48 DESCRIPTION plastic thermal enhanced thin quad flat package; 48 leads; body 7 x 7 x 1.0 mm; heatsink VERSION SOT545-2
SAMPLING FREQUENCY (MHz) 60 80 105
2003 Dec 09
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Philips Semiconductors
Objective specification
12-bit, 60/80/105 Msps Analog-to-Digital Converter (ADC) Nyquist/high IF sampling
6 BLOCK DIAGRAM
TDA8769
handbook, full pagewidth
DEL0 DEL1 CLK CLKN 16 15 39 38
VCCA1 2
VCCA3 3
VCCA4 44
VCCD1 VCCD2 40 17
FSREF
13
VREF REFERENCE
TDA8769
VREF 11 CLOCK DRIVER 36 CCS
19 AMP INN IN TH 47 46 42 & ADC LATCH TRACK LATCH 12 23 to 34 35 22
OTC D0 to D11 VCCO IR
HOLD
CMADC
1
CMADC REFERENCE
POWER MANAGEMENT
n.c.
6 to 10, 12, 14, 21, 45 5 DEC 20 CEN 48 4 43 41 18 37 OGND
MBL884
AGND1 AGND3 AGND4 DGND1 DGND2
Fig.1 Block diagram.
7
PINNING SYMBOL PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 TYPE(1) O P P G I/O - - - - - I - O - I I P DESCRIPTION regulator output common mode ADC output analog supply voltage 1 (5.0 V) analog supply voltage 3 (5.0 V) analog ground 3 decoupling node not connected not connected not connected not connected not connected reference voltage input not connected reference output not connected complete conversion sampling delay input 1 complete conversion sampling delay input 0 digital supply voltage 2 (5.0 V) 4
CMADC VCCA1 VCCA3 AGND3 DEC n.c. n.c. n.c. n.c. n.c. VREF n.c. FSREF n.c. DEL1 DEL0 VCCD2 2003 Dec 09
Philips Semiconductors
Objective specification
12-bit, 60/80/105 Msps Analog-to-Digital Converter (ADC) Nyquist/high IF sampling
SYMBOL DGND2 OTC CEN n.c. IR D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 VCCO CCS OGND CLKN CLK VCCD1 DGND1 TH AGND4 VCCA4 n.c. IN INN AGND1 AGND5 Note 1. P = power supply, G = ground, I = input and O = output. PIN 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 exposed die pad TYPE(1) G I I - O O O O O O O O O O O O O P O G I I P G I G P - I I G G digital ground 2 control input two's complement output (active HIGH) chip enable input (CMOS level; active LOW) not connected in-range output data output bit 11 (MSB) data output bit 10 data output bit 9 data output bit 8 data output bit 7 data output bit 6 data output bit 5 data output bit 4 data output bit 3 data output bit 2 data output bit 1 data output bit 0 (LSB) supply voltage of data output (3.3 V) complete conversion signal output ground of data output complementary clock input clock input digital supply voltage 1 (5.0 V) digital ground 1 track-and-hold enable input (CMOS level; active HIGH) analog ground 4 analog supply voltage 4 (5.0 V) not connected analog input voltage complementary analog input voltage analog ground 1 analog ground 5 DESCRIPTION
TDA8769
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Philips Semiconductors
Objective specification
12-bit, 60/80/105 Msps Analog-to-Digital Converter (ADC) Nyquist/high IF sampling
TDA8769
41 DGND1
48 AGND1
43 AGND4
CMADC VCCA1 VCCA3 AGND3 DEC n.c. n.c. n.c. n.c.
1 2 3 4 5 6
37 OGND
38 CLKN
handbook, full pagewidth
40 VCCD1
44 VCCA4
39 CLK
47 INN
45 n.c.
42 TH
46 IN
36 CCS 35 VCCO 34 D0 33 D1 32 D2 31 D3
TDA8769HW
7 8 9 30 D4 29 D5 28 D6 27 D7 exposed die pad VREF 11 n.c. 12 26 D8 25 D9
n.c. 10
FSREF 13
n.c. 14
DEL1 15
DEL0 16
VCCD2 17
DGND2 18
OTC 19
CEN 20
n.c. 21
IR 22
D11 23
D10 24
MBL885
Fig.2 Pin configuration.
8 Tbf. 9
LIMITING VALUES
THERMAL CHARACTERISTICS SYMBOL PARAMETER thermal resistance from junction to ambient thermal resistance from case to ambient CONDITIONS in free air; (tbf) in free air; (tbf) VALUE 25 (tbf) UNIT K/W K/W
Rth(j-a) Rth(c-a)
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Philips Semiconductors
Objective specification
12-bit, 60/80/105 Msps Analog-to-Digital Converter (ADC) Nyquist/high IF sampling
TDA8769
10 CHARACTERISTICS VCCA = 4.75 to 5.25 V; VCCD = 4.75 to 5.25 V; VCCO = 2.7 to 3.6 V; AGND connected to DGND; Tamb = -40 to +85 C; VIN(p-p) - VINN(p-p) = 1.9 V - 0.5 dBFS; VVREF = VCCA3 - 1.75 V; Vi(CM ) = VCCA3 - 1.6 V; typical values measured at VCCA = VCCD = 5 V, VCCO = 3.0 V, Tamb = 25 C and CL = 10 pF; unless otherwise specified. SYMBOL Supplies VCCA VCCD VCCO ICCA ICCD ICCO Ptot analog supply voltage digital supply voltage output supply voltage analog supply current digital supply current output supply current total power dissipation fCLK = 80 Msps; fi = 21.4 MHz fCLK = 60 Msps; fi = 21.4 MHz fCLK = 80 Msps; fi = 21.4 MHz fCLK = 105 Msps; fi = 21.4 MHz Clock inputs: pins CLK and CLKN; note 2 INPUTS VIL LOW-level input voltage referenced to DGND; VCCD = 5 V PECL mode TTL mode VIH HIGH-level input referenced to DGND; voltage VCCD = 5 V PECL mode TTL mode IIL IIH VCLK LOW-level input current VCLK or VCLKN = 3.52 V VCLK or VCLKN = 0.80 V 3.83 2.0 (tbf) (tbf) - - (tbf) - - - - - - 1.5 4.12 VCCD - - (tbf) (tbf) (tbf) V V A mA A mA V 3.19 DGND - - 3.52 0.8 V V 4.75 4.75 2.7 - - - - - - 5.0 5.0 3.0 109 48 17.5 825 840 855 5.25 5.25 3.6 (tbf) (tbf) (tbf) (tbf) (tbf) (tbf) V V V mA mA mA mW mW mW PARAMETER CONDITIONS TEST(1) MIN. TYP. MAX. UNIT
HIGH-level input VCLK or VCLKN = 3.83 V current VCLK or VCLKN = 2.00 V differential AC input voltage for switching input resistance input capacitance VCLK = VCLK - VCLKN; AC mode; DC voltage level = 2.5 V fCLK = 105 Msps fCLK = 105 Msps
Ri Ci
- -
(tbf) (tbf)
- -
M pF
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Philips Semiconductors
Objective specification
12-bit, 60/80/105 Msps Analog-to-Digital Converter (ADC) Nyquist/high IF sampling
SYMBOL TIMING fclk(min) fclk(max) minimum clock frequency maximum clock frequency TDA8769HW/6 maximum clock frequency TDA8769HW/8 maximum clock frequency TDA8769HW/10 tCLKH tCLKL clock HIGH pulse width fi = 21.4 MHz VTH = VCCD - 60 - - 9 - PARAMETER CONDITIONS TEST(1) MIN. TYP.
TDA8769
MAX.
UNIT
Msps MHz/ Msps MHz/ Msps MHz/ Msps ns ns
80
-
-
105
-
-
(tbf) (tbf)
- -
- -
clock LOW pulse fi = 21.4 MHz width VVREF = VCCA3 - 1.75 V; VTH = HIGH
Analog inputs: pins IN and INN IIL IIH Ri Ci Vi(CM) LOW-level input current - - D D VIN = VINN; output code = 2047 D - - 10 10 8.4 250 - - - 500 VCCA3 - 1.7 A A M fF V
HIGH-level input VVREF = VCCA3 - 1.75 V; current VTH = HIGH input resistance input capacitance common mode input voltage
VCCA3 - 1.2 VCCA3 - 1.6
Digital inputs: pins OTC, SH, DEL1, DEL0 and CEN VIL VIH IIL IIH LOW-level input voltage HIGH-level input voltage LOW-level input current VIL = 0.3VCCD DGND 0.7VCCD (tbf) - - - - - (tbf) 0.3VCCD VCCD V V A A
HIGH-level input VIH = 0.7VCCD current
Voltage controlled regulator output: pin CMADC Vo(CM) IL(CM) common mode output voltage load current - - VCCA3 - 1.6 1 - 2 V mA
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Philips Semiconductors
Objective specification
12-bit, 60/80/105 Msps Analog-to-Digital Converter (ADC) Nyquist/high IF sampling
SYMBOL PARAMETER CONDITIONS TEST(1) - - MIN. TYP. VCCA3 - 1.75 - 1.9 -
TDA8769
MAX.
UNIT
Reference voltage input: pin VREF; note 3 Vref(FS) Vi(p-p) full-scale fixed voltage input voltage (peak-to-peak value) input current fi = 25 MHz; fCLK = 105 Msps Vi = VIN - VINN; VVREF = VCCA3 - 1.75 V; Vi(CM) = VCCA3 - 1.6 V V V
Iref Vo(FS) IL(FS)
- - -
0.3
10
A V mA
Full-scale voltage controlled regulator output: pin FSREF 1.9 V full-scale output voltage load current VCCA3 - 1.75 - 1 2
Digital outputs: pins D11 to D0 and IR OUTPUT LEVELS VOL VOH IOZ LOW-level output voltage HIGH-level output voltage output current in 3-state IOL = 2 mA IOH = -0.4 mA output level between 0.5 V and VCCO CL = 10 pF; note 4 CL = 10 pF CL = 10 pF DGND VCCO - 0.5 -20 - - - DGND + 0.5 V VCCO +20 V A
TIMING; see Fig. 3 td(s) th(o) td(o) tdZH tdZL tdHZ tdLZ sampling delay output hold time output delay - (tbf) - - - - - (tbf) 3.7 4.6 (tbf) - (tbf) - - - - ns ns ns
3-STATE OUTPUT DELAY enable to HIGH state enable to LOW state disable from HIGH state disable from LOW state 2.8 7.5 7.2 2.9 ns ns ns ns
Timing complete conversion signal: pin CCS td(CCS) complete conversion signal delay CL = 10 pF; see Table 4 and Fig 4 DEL0 = LOW; DEL1 = HIGH DEL0 = HIGH; DEL1 = LOW DEL0 = HIGH; DEL1 = HIGH - - - 0 1.2 2.2 - - - ns ns ns
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Philips Semiconductors
Objective specification
12-bit, 60/80/105 Msps Analog-to-Digital Converter (ADC) Nyquist/high IF sampling
SYMBOL PARAMETER CONDITIONS TEST(1) - - MIN. TYP. 1.7 0.4
TDA8769
MAX.
UNIT
Analog signal processing (50% clock duty factor) INL DNL integral non-linearity differential non-linearity offset error fCLK = 20 Msps; fi = 400 kHz fCLK = 20 Msps; fi = 400 kHz; no missing code guaranteed VCCA = VCCD = 5 V; VCCO = 3.0 V; Tamb = 25 C; output code = 2047 (tbf) (tbf) LSB LSB
Eoffset
-
-5
-
mV
EG
gain error VCCA = VCCD = 5 V; amplitude VCCO = 3.0 V; Tamb = 25 C (spread from device to device) analog bandwidth total harmonic distortion TDA8769HW/6 total harmonic distortion TDA8769HW8 total harmonic distortion TDA8769HW/10 fCLK = 105 Msps; -3 dB; full-scale input; note 5 B = Nyquist; note 6 fi = 21.4 MHz B = Nyquist; note 6 fi = 21.4 MHz fi = 50 MHz B = Nyquist; note 6 fi = 21.4 MHz fi = 78 MHz shorted input; VTH = VCCD; fclk = 105 Msps fi = 21.4 MHz; note 7 B = Nyquist fi = 21.4 MHz; note 7 B = Nyquist fi = 50 MHz; note 7 B = Nyquist B = 5 MHz signal-to-noise ratio TDA8769HW/10 fi = 21.4 MHz; note 7 B = Nyquist fi = 78 MHz; note 7 B = Nyquist B = 5 MHz D
(tbf)
-
(tbf)
%FS
B THD
-
330
-
MHz
-
-74
-
dBc
- - - - -
-74 -68 -67 -63 (tbf)
- - - - -
dBc dBc dBc dBc LSB
Nth(rms)
thermal noise (RMS value) signal-to-noise ratio TDA8769HW/6 signal-to-noise ratio TDA8769HW/8
SNR
-
66
-
dBc
- - - - - -
66 66 72.4 64 62 72
- - - - - -
dBc dBc dBc dBc dBc dBc
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Philips Semiconductors
Objective specification
12-bit, 60/80/105 Msps Analog-to-Digital Converter (ADC) Nyquist/high IF sampling
SYMBOL SFDR PARAMETER spurious free dynamic range TDA8769HW/6 spurious free dynamic range TDA8769HW/8 CONDITIONS fi = 21.4 MHz B = Nyquist fi = 21.4 MHz B = Nyquist fi = 50 MHz B = Nyquist B = 5 MHz spurious free dynamic range TDA8769HW/10 fi = 21.4 MHz B = Nyquist fi = 78 MHz B = Nyquist B = 5 MHz ENOB effective number fi = 21.4 MHz; note 8 of bits B = Nyquist TDA8769HW/6 effective number fi = 21.4 MHz; note 8 of bits B = Nyquist TDA8769HW/8 fi = 50 MHz; note 8 B = Nyquist B = 5 MHz effective number fi = 21.4 MHz; note 8 of bits B = Nyquist TDA8769HW/10 fi = 78 MHz; note 8 B = Nyquist B = 5 MHz IM2 second order intermodulation distortion third order intermodulation distortion bit error rate fi1 = 15 MHz and fi2 = 18 MHz; note 10 fclk= 80 Msps fi1 = 15 MHz and fi2 = 18 MHz; note 10 fclk= 80 Msps fi = 25 MHz; VIN = 16LSB at code 2047; fclk = 105 Msps - - 82 (tbf) - - - (tbf) - - - - 67 84 10.6 - - - - 68 - - - 70 80.8 - - - 77 - - 77 - TEST(1) MIN. TYP.
TDA8769
MAX.
UNIT dBc
dBc dBc dBc dBc dBc dBc bit
- - - - - -
10.6 10.3 11.7 10 9.6 11.8
- - - - - -
bit bit bit bit bit bit
dBFS
IM3
dBFS
BER
Notes 1. Explanation tests: a) D = guaranteed by design b) C = guaranteed by characterization c) I = industrially tested for 100%.
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Philips Semiconductors
Objective specification
12-bit, 60/80/105 Msps Analog-to-Digital Converter (ADC) Nyquist/high IF sampling
2. The circuit has two clock inputs: CLK and CLKN. There are 5 modes of operation:
TDA8769
a) PECL mode 1: (DC level varies proportionally with VCCD) CLK and CLKN inputs are at differential PECL levels. b) PECL mode 2: (DC level varies proportionally with VCCD) CLK input is at PECL level and sampling is taken on the falling edge of the clock input signal. A DC level of 3.65 V has to be applied on CLKN decoupled to GND via a 100 nF capacitor. c) PECL mode 3: (DC level varies proportionally with VCCD) CLKN input is at PECL level and sampling is taken on the rising edge of the clock input signal. A DC level of 3.65 V has to be applied on CLK decoupled to GND via a 100 nF capacitor. d) Differential AC driving mode 4: When driving the CLK input directly and with any AC signal of minimum 1 V (p-p) and with a DC level of 2.5 V, the sampling takes place at the falling edge of the clock signal. When driving the CLKN input with the same signal, sampling takes place at the rising edge of the clock signal. It is recommended to decouple the CLKN or CLK input to DGND via a 100 nF capacitor. e) TTL mode 5: CLK input is at TTL level and sampling is taken on the falling edge of the clock input signal. In that case CLKN pin has to be connected to the ground. 3. The ADC input range can be adjusted with an external reference connected to pin VREF. This voltage has to be referenced to VCCA. 4. Output data acquisition: the output data is available after the maximum delay of td(s). 5. The -3 dB analog bandwidth is determined by the 3 dB reduction in the reconstructed output, the input being a full-scale sine wave. 6. The total harmonic distortion is obtained with the addition of the first five harmonics. 7. The signal-to-noise ratio takes into account all harmonics above five and noise up to Nyquist frequency. 8. The effective number of bits, or ENOB, are obtained via a Fast Fourier Transform (FFT). The calculation takes into account all harmonics and noise up to half of the clock frequency (Nyquist frequency). Conversion to signal-to-noise and distortion, or SINAD, is given by SINAD = ENOB x 6.02 + 1.76 dB. 9. Intermodulation measured relative to either tone with analog input frequencies of (tbf) and (tbf) MHz. The two input signals have the same amplitude and the total amplitude of both signals provides full-scale input to the converter (-6 dB below full-scale for each input signal). 10. IM2 is the ratio of the RMS value of either input tone to the RMS value of the worst case second order intermodulation product. IM3 is the ratio of the RMS value of either input tone to the RMS value of the worst case third order intermodulation product.
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Philips Semiconductors
Objective specification
12-bit, 60/80/105 Msps Analog-to-Digital Converter (ADC) Nyquist/high IF sampling
TDA8769
handbook, full pagewidth
CKP
n
50%
td(o) D0 to D11 data n-1 data n th(o) tds(i) VI sample n sample n+1 sample n+2 sample n+3 sample n+4
MDB034
data n+1
VCCO - 0.5 V 0.5 V
Fig.3 Output timing diagram.
handbook, full pagewidth
D0 to D11
td(CCS)
CCS
MBL874
Fig.4 Complete conversion signal timing diagram.
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Philips Semiconductors
Objective specification
12-bit, 60/80/105 Msps Analog-to-Digital Converter (ADC) Nyquist/high IF sampling
11 APPLICATION INFORMATION 11.1 Output coding and control signals
TDA8769
Table 1
Output coding with differential inputs (typical values to AGND); VIN(p-p) - VINN(p-p) = 1.9 V - 0.5 dBFS; VVREF = VCCA3 - 1.75 V VIN(p-p) <2.925 2.925 - : 3.4 : - 3.875 >3.875 Mode selection CHIP ENABLE NOT (CEN) 0 0 1 OUTPUT DATA (D0 TO D11 AND IR) binary; active two's complement; active high impedance VINN(p-p) >3.875 3.875 - : 3.4 : - 2.925 <2.925 0 IR 0 1 BINARY OUTPUTS (D11 TO D0) 000000000000 000000000000 000000000001 : 011111111111 : 111111111110 111111111111 111111111111 TWO'S COMPLEMENT OUTPUTS (D11 TO D0) 100000000000 100000000000 100000000001 : 111111111111 : 011111111110 011111111111 011111111111
CODE Underflow 0 1 : 2047 : 4094 4095 Overflow Table 2
CONTROL INPUT TWO'S COMPLEMENT OUTPUT (OTC) 0 1 don't care Table 3
Track-and-hold selection MODE active inactive; tracking
CONTROL INPUT TRACK-AND-HOLD (TH) 1 0 Table 4 Complete conversion signal selection DEL1 0 0 1 1 11.2 TDA8769 in 3G radio receivers DEL0 0 1 0 1 inactive
OUTPUT SIGNAL active (for timing values, see Chapter 10)
TDA8769 has been proven in many 3G receivers with various operating conditions regarding input frequency, signal input frequency bandwidth and sampling frequency. TDA8769 provides a maximum analog input frequency of 250 MHz. It allows a significant cost reduction of the RF front-end, from two mixers to only one, even in multicarrier architecture. Table 5 shows possible applications with the TDA8769 in High IF sampling mode.
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Philips Semiconductors
Objective specification
12-bit, 60/80/105 Msps Analog-to-Digital Converter (ADC) Nyquist/high IF sampling
Table 5 Examples of possible fi, fclk and fi bandwidth combinations supported fi (MHz) 250 243.95 243.95 243.95 190 106 86 80 70 69.99 27 10.8 fclk (MHz) 9.60 9.60 19.20 52.00 40.00 76.80 76.80 61.44 40.00 58.98 51.2 32.5 fi BW (MHz) 0.20 0.20 0.20 0.20 1.25 5.00 5.00 10.00 5.00 1.25 3.5 0.30 SNR (dB) 66.5 62.6 68.4 65.7 72.0 70.8 72.2 (tbf) 70 (tbf) (tbf) 84.3
TDA8769
SFDR (dBc) 79.9 68.5 77.2 80.0 80.0 83.6 87.1 (tbf) 70 (tbf) (tbf) 83.0
For a dual carrier W_CDMA receiver, the most important parameters are the sensitivity and Adjacent Channel Selectivity (ACS). In W-CDMA, it can be far below the noise floor, is defined by the Sensitivity to Noise Ratio (SENR). Its value is negative due to the gain processing. The Adjacent Channel Power Ratio (ACPR) is the difference between the peak and noise floor. It represents the ratio of the adjacent channel power and the average power of the channel. The ACS is defined by the sum of SENR and ACPR. Figure 5 illustrates the relation between these parameters. On a typical application with the TDA8769 device, the ACS obtained is 80 dB with an ACPR of 70 dB and a SENR of 10 dB. Moreover, the Noise Figure (NF) of the TDA8769 is 31.5 dB.
handbook, full pagewidth
interfering channel
wanted channel
ACS
ACPR
noise floor NF SENR sensitivity thermal noise
MBL875
Fig.5 Adjacent channel selectivity and analog-to-digital converter sensitivity.
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Philips Semiconductors
Objective specification
12-bit, 60/80/105 Msps Analog-to-Digital Converter (ADC) Nyquist/high IF sampling
11.3 Application diagrams
TDA8769
TDA8769
CLK CLKN 270 270
TDA8769
CLK CLKN Q TTL 50 D Q
MDB035
TTL
MDB036
Fig.6 TTL to PECL translator application.
Fig.7 TTL single-ended clock application.
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Philips Semiconductors
Objective specification
12-bit, 60/80/105 Msps Analog-to-Digital Converter (ADC) Nyquist/high IF sampling
TDA8769
tbf
Fig.8 Application diagram.
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Philips Semiconductors
Objective specification
12-bit, 60/80/105 Msps Analog-to-Digital Converter (ADC) Nyquist/high IF sampling
11.4 Demonstration board
TR1 T1_6T_KK81 3 TB1 2 1 AGND CMADC DGND1 AGND1 AGND4 VCCD1 VCCA4 INN OGND CLK CLKN n.c.
TDA8769
handbook, full pagewidth
R125680 J1 C1 IN 220 nF AGND
50 VCCA R3 100 VCCA AGND
VCCD1 DGND ON 1K2 TH S1 VCCD1 DGND DGND R2 50
4 R1 100 5 6
R125680 J2 CLK
AGND
AGND
TH
C14 330 nF
VCCA S2 P1 5 k EXT 1K2 CMADC VCCA1 VCCA3 AGND3 DEC n.c. C4 100 nF AGND TB2 VCCA AGND C5 VCCA 100 nF S3 EXT 1K2 n.c. n.c. n.c. n.c. VREF n.c. 1 2 3 4 5 6 7 8 9
IN
DGND DGND 36 35 34 33 CCS VCCO D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 CSS D0 VCCO PCN12A_44P_2.54DS J1 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 AGND B11 B12 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19
48
47
46
45
44
43
42
41
40
39
38
37
AGND AGND VCCA AGND
IC1
32 31 30 29 28 27 26 25
TDA8769HW
10 11 12 13 FSREF 14 n.c. 15 DEL1 16 DEL0 17 VCCD2 18 DGND2 19 OTC 20 CEN 21 n.c. 22 IR 23 D11 24 D10
VCCA R5 1.2 k P2 1 k R4 2.4 k AGND
DGND VCCD2 ON DEL1 DGND
DGND VCCD2 VCCD2 ON DEL0 DGND VCCD2 ON OTC DGND S6 1K2
DGND
B13 B14 B15 B16 B17 B18 B19 VCCD2 OFF CEN DGND C12 10 nF VCCO IC4 2 5 VCC 3 GND 4 74AHC1GUO4GW R9 50 R125680 J3
S4
S8
S7 1K2
B20 TRIG B21 B22
A20 A21 A22
DGND DGND
FL1 470D_0D0_S C2 330 nF AGND AGND
VCCA (44) (2/3) C3 100 nF C18 10 nF C19 10 nF
DGND R11 150 4
R10 150 1 IR D3 LS6T670
3 AGND
2 VCCO
VCCD1 (40) FL3 470D_0D0_S C13 330 nF DGND DGND DGND VCCD2 (17) FL2 470D_0D0_S C11 330 nF DGND TM3 DGND DGND D1 BYD17G 12 V J5 1 20 V FL4 HF70A08S AGND VCCO (35) OUT 16 V GND DGND DGND DGND DGND C8 4.7 F TM1 R6 750 C9 470 nF IN TP1 240 C10 1F C16 10 nF C6 100 nF C20 10 nF C15 100 nF C17 10 nF
DGND
TM2
IN C7 22 F
MC7805D2T
1 IC2 2 3
LM317D2T
3 IC3 1 ADJ 2
OUT R8
MSTBA2.5_20_5D8 GND J5 2
D2 PWR LGT679_C0 DGND
DGND R7
330 DGND
MBL876
DGND
Fig.9 Demonstration board schematic.
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Philips Semiconductors
Objective specification
12-bit, 60/80/105 Msps Analog-to-Digital Converter (ADC) Nyquist/high IF sampling
TDA8769
J1
TM2
R1 1TB1
C1
J2
C13 FL3
J5
C15 R2 C16 J4 C17 C18 FL4 C19
R3 1 C2 FL1 C4 TB2 C5 R4 P2 S3 R5 IC3 C10 TP1 D3 R10 1
P1 C3 IC1
2
S4 S5
D1
C7
C5 FL2
C9
TM1
R6
R7 R8
S6 S7
IC2
C20
D2
C8
R9 C11 C12 R11
TM3
J3
IC4
C14
TR1
S1 S2
MBL877
MBL878
Fig.10 Component placement, top view.
Fig.11 Component placement, bottom view.
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Philips Semiconductors
Objective specification
12-bit, 60/80/105 Msps Analog-to-Digital Converter (ADC) Nyquist/high IF sampling
TDA8769
MBL879
MBL880
Fig.12 Printed-circuit board tracks, layout 1.
Fig.13 Printed-circuit board tracks, layout 2.
MBL881
Fig.14 Printed-circuit board tracks, layout 3.
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Philips Semiconductors
Objective specification
12-bit, 60/80/105 Msps Analog-to-Digital Converter (ADC) Nyquist/high IF sampling
11.5 11.5.1 Definitions STATIC PARAMETERS where: i = 0 to 2n - 2 Vin = input voltage for code i S = slope of the ideal straight line. 11.5.2 DYNAMIC PARAMETERS
TDA8769
11.5.1.1
Integral non-linearity (INL)
INL is defined as the deviation of the transfer function from a best fit straight line (linear regression computation). The INL of code i is obtained from the following equation: V in ( i ) - V in ( ideal ) INL ( i ) = ---------------------------------------------S where: i = code value Vin = input voltage for code i S = slope of the ideal straight line (code width).
Figure 15 shows the spectrum of a single tone full-scale input sine wave with frequency ft, conforming to coherent sampling and digitized by the ADC under test. Coherent ft M sampling means that --- = ---- , where M is the number of fs N cycles, N the number of samples and both M and N being a relative prime. Remark: The parameter Pnoise used in the following equations includes the power of the random noise, non-linearities, sampling time errors and quantization noise.
11.5.1.2
Differential non-linearity (DNL)
DNL is the deviation in code width from the value of one LSB. The DNL of code i is obtained from the following equation: V in ( i + 1 ) - V in ( i ) DNL ( i ) = -------------------------------------------S
handbook, full pagewidth
0
MBL882
-20 magnitude -40 -60 -80 -100 -120 -140 -160 0 2.5 5 7.5 10 12.5 15 17.5 20 22.5 25 27 measured output range (MHz) IMD3
Fig.15 Spectrum of a full-scale input sine wave with frequency ft.
2003 Dec 09
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Philips Semiconductors
Objective specification
12-bit, 60/80/105 Msps Analog-to-Digital Converter (ADC) Nyquist/high IF sampling
11.5.2.1 Signal-to-noise and distortion (SINAD) 11.5.2.4 Signal-to-noise ratio (SNR)
TDA8769
SINAD is the ratio of the signal power to the noise plus distortion power, excluding the DC component, at a given sample rate and input frequency: P signal SINAD = 10log 10 ------------------------------------- dB. P noise + distortion
SNR is the ratio of the signal power to the noise power, excluding the harmonics and DC component of the signal: P signal SNR = 10log 10 --------------- dB P noise
11.5.2.5 11.5.2.2 Effective number of bits (ENOB)
ENOB is derived from SINAD and gives the theoretical resolution an ideal ADC would require to obtain the same SINAD measured on the actual ADC. A good approximation is: SINAD - 1.76 ENOB = ------------------------------------6.02
Spurious free dynamic range (SFDR)
The SFDR specifies the available signal range as the spectral distance between the amplitude of the fundamental and the amplitude of the largest spurious signal, harmonic and non-harmonic, excluding the DC component. a1 SFDR = 10log 10 ------------------- dB max ( s - )
11.5.2.3
Total harmonic distortion (THD)
11.5.2.6
Intermodulation distortion (IMD2 and IMD3)
THD is the ratio of the power of the harmonics to the power of the signal frequency. The equation for k - 1 harmonics is: P harmonics THD = 10log 10 ------------------------ dB P signal - where: P harmonics = a 2 + a 3 + ... + a k P signal = a 1
2 2 2 2
Figure 16 shows the spectral analysis of a dual tone sine wave input, at frequencies ft1 and ft2, meeting the coherence criterion. The 2nd and 3rd order intermodulation distortion products, IMD2 and IMD3 respectively, are defined with a dual tone input. IMD2 is defined as the ratio of the RMS value of either tone to the RMS value of the second order intermodulation product, IMD3 with the third order intermodulation product. The IMD is given by: P intermod IMD = 10log 10 -------------------- dB P signal -
As usual the value of k = 6 (i.e. the calculation of THD is done with the first 5 harmonics).
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Philips Semiconductors
Objective specification
12-bit, 60/80/105 Msps Analog-to-Digital Converter (ADC) Nyquist/high IF sampling
where: P intermod = a P signal = a a
2 im ( ft ) 2 2 im ( ft1 - ft2 )
TDA8769
-a
2
im ( ft1 + ft2 )
+a
2
im ( ft1 - 2ft2 )
+a
2
im ( ft1 + 2ft2 )
+...+a
2
im ( 2ft1 - ft2 )
+a
2
im ( f2t1 + ft2 )
ft1
+a
2
ft2
.
is the power of the intermodulation component at ft.
handbook, full pagewidth
MBL883
a1
magnitude SFDR
a2
a3
ak
measured output range (MHz)
Fig.16 Spectral analysis with dual tone.
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Philips Semiconductors
Objective specification
12-bit, 60/80/105 Msps Analog-to-Digital Converter (ADC) Nyquist/high IF sampling
12 PACKAGE OUTLINE
HTQFP48: plastic thermal enhanced thin quad flat package; 48 leads; body 7 x 7 x 1 mm; exposed die pad
TDA8769
SOT545-2
c y exposed die pad side X
Dh 36 37 25 24 ZE A
e Eh wM bp pin 1 index 48 1 wM 12 ZD vM A 13 detail X Lp L E HE A A2 A1 (A 3)
bp e D HD
B vM B
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) A UNIT max. mm 1.2 A1 0.15 0.05 A2 1.05 0.95 A3 0.25 bp 0.27 0.17 c 0.20 0.09 D(1) 7.1 6.9 Dh 4.6 4.4 E(1) 7.1 6.9 Eh 4.6 4.4 e 0.5 HD 9.1 8.9 HE 9.1 8.9 L 1 Lp 0.75 0.45 v 0.2 w 0.08 y 0.08 ZD(1) ZE(1) 0.89 0.61 0.89 0.61 7 0
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT545-2 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION
ISSUE DATE 99-08-04 03-04-07
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Philips Semiconductors
Objective specification
12-bit, 60/80/105 Msps Analog-to-Digital Converter (ADC) Nyquist/high IF sampling
13 SOLDERING 13.1 Introduction to soldering surface mount packages
TDA8769
To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results: * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250 C or 265 C, depending on solder material applied, SnPb or Pb-free respectively. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 13.4 Manual soldering
This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. 13.2 Reflow soldering
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 270 C depending on solder paste material. The top-surface temperature of the packages should preferably be kept: * below 225 C (SnPb process) or below 245 C (Pb-free process) - for all BGA, HTSSON-T and SSOP-T packages - for packages with a thickness 2.5 mm - for packages with a thickness < 2.5 mm and a volume 350 mm3 so called thick/large packages. * below 240 C (SnPb process) or below 260 C (Pb-free process) for packages with a thickness < 2.5 mm and a volume < 350 mm3 so called small/thin packages. Moisture sensitivity precautions, as indicated on packing, must be respected at all times. 13.3 Wave soldering
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems.
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Philips Semiconductors
Objective specification
12-bit, 60/80/105 Msps Analog-to-Digital Converter (ADC) Nyquist/high IF sampling
13.5 Suitability of surface mount IC packages for wave and reflow soldering methods PACKAGE(1) BGA, HTSSON..T(3), LBGA, LFBGA, SQFP, SSOP..T(3), TFBGA, USON, VFBGA DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP, HSQFP, HSSON, HTQFP, HTSSOP, HVQFN, HVSON, SMS PLCC(5), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO, VSSOP CWQCCN..L(8), PMFP(9), WQCCN..L(8) Notes not suitable not suitable(4) suitable not not recommended(5)(6) recommended(7)
TDA8769
SOLDERING METHOD WAVE REFLOW(2) suitable suitable suitable suitable suitable not suitable
not suitable
1. For more detailed information on the BGA packages refer to the "(LF)BGA Application Note" (AN01026); order a copy from your Philips Semiconductors sales office. 2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 3. These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature exceeding 217 C 10 C measured in the atmosphere of the reflow oven. The package body peak temperature must be kept as low as possible. 4. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. 5. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 6. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 7. Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 8. Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered pre-mounted on flex foil. However, the image sensor package can be mounted by the client on a flex foil by using a hot bar soldering process. The appropriate soldering profile can be provided on request. 9. Hot bar or manual soldering is suitable for PMFP packages.
2003 Dec 09
26
Philips Semiconductors
Objective specification
12-bit, 60/80/105 Msps Analog-to-Digital Converter (ADC) Nyquist/high IF sampling
14 DATA SHEET STATUS LEVEL I DATA SHEET STATUS(1) Objective data PRODUCT STATUS(2)(3) Development DEFINITION
TDA8769
This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN).
II
Preliminary data Qualification
III
Product data
Production
Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 15 DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 16 DISCLAIMERS Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
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Philips Semiconductors - a worldwide company
Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
(c) Koninklijke Philips Electronics N.V. 2003
SCA75
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
R78/02/pp28
Date of release: 2003
Dec 09
Document order number:
9397 750 11706

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