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ANALOG IP BLOCK PECL_RX - CMOS PECL Receiver
DATA SHEET
PROCESS
C35B3 (0.35um)
DESCRIPTION
The PECL_RX is a 3.3 V PECL differential line receiver featuring an operating frequency up to 311 MHz (622 Mb/s) and accepting standard F100K levels (referred to the positive supply). The PECL_RX accepts (750 mV) differential input signals and translates them to CMOS output levels. With the companion line driver (PECL_TX ) it can be used for high speed applications. The cell PECL_RX requires the PERXBIAS cell for biasing. PERXBIAS can drive up to 3 PECL_RX cells. An external voltage reference must be used. The PECL_RX can be set in power down mode.
FEATURES
! ! ! ! ! ! ! ! ! PECL_RX area: 0.1 mm2, size: x = 300 m y = 340 m PERXBIAS size: x = 382 m y = 375 m 3.3 V 10% supply voltage 622 Mb/s transmission speed 1 ns max. propagation delay Power dissipation 23 mW at 3.3 V static without PERXBIAS Junction temperature -40 - 125C Output levels fully compatible with F100K PECL Family Power down mode
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Datasheet: PECL_RX - C35
TECHNICAL DATA FOR PECL_RX
(Tjunction = -40 to 125 C, VDDPECL = VDDCMOS = VDDA = +3.0 V to +3.6 V, XPD = High, SIM = Low, unless otherwise specified)
DC CHARACTERISTICS
Symbol VID Parameter Differential Input VID = |VINP - VINN| VICM VIH VIL VHYS VOH VOL Common Mode Input Voltage VICM = (VINP + VINN) / 2 Input Voltage High Input Voltage Low Hysteresis Output Voltage High Output Voltage Low Referred to VDDPECL Referred to VDDPECL -1.165 -1.830 25 CMOS levels -0.870 -1.475 100 V V mV V V Referred to VDDPECL -1.5 -1.3 -1.1 V Conditions Min 250 Typ 750 Max 900 Units mV
AC CHARACTERISTICS
CL = 1 pF at each output, unless otherwise specified Symbol tPD tSKD1 tSKD2 tTLH tTHL Cload Cin fMAX TXS Parameter 1) Propagation Delay Differential Pulse Skew 1) Differential Channel to Channel Skew 1) Rise Time 2) Fall Time 2) Load Capacitance Input Capacitance Operating Frequency Transmission Rate @622 Mb/s 700 311 622 150 150 300 300 Conditions Min 600 Typ 800 Max 1000 80 100 600 600 1 900 311 622 Unit ps ps ps ps ps pF fF MHz Mb/s
POWER REQUIREMENTS
Symbol ICCDC ICCAC ICCPD Pdiss_DC Pdiss_AC Pdiss_PD Parameter DC Current Consumption AC Current Consumption Power Down Current Consumption DC Power Consumption AC Power Consumption Power Consumption in Power Down Mode Conditions Without PERXBIAS Cload = 1 pF @622 Mb/s, without PERXBIAS XPD = Low, without PERXBIAS Without PERXBIAS Cload = 1 pF @622 Mb/s, without PERXBIAS XPD = Low, without PERXBIAS 23 36 Min Typ 7 11 Max 10 15 300 36 54 1.08 Unit mA mA A mW mW mW
1) 2)
Including the package: SOIC28, pins 5-10 or 19-24 for VOUTP and VOUTN Specified at 20% and 80% of the output voltage
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Datasheet: PECL_RX - C35
TECHNICAL DATA FOR PERXBIAS
(Tjunction = -40 to 125 C, VDDA = +3.0 V to +3.6 V, XSIM = High, unless otherwise specified)
POWER REQUIREMENTS
Symbol ICC Pdiss Parameter DC Current Consumption Power Consumption Conditions Min Typ 1.2 4 Max 2 7.2 Unit mA mW
REFERENCE CHARACTERISTICS
Symbol VREF Parameter Reference Voltage Conditions Min 1.20 Typ 1.22 Max 1.24 Unit V
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Datasheet: PECL_RX - C35
SYMBOL OF PECL_RX
PIN LIST OF PECL_RX
Pin VDDPECL VDDA VDDCMOS VSSPECL VSSCMOS IREFP IREFN VMID Description Positive Supply for PECL Receiver Positive Supply Positive Supply for CMOS Output Buffer Negative Supply Negative Supply Bias Current Bias Current Voltage Reference Power Down Test Pin Positive Input Negative Input Pos. PECL Output Neg. PECL Output Type Supply Supply Supply Supply Supply Analog Analog Analog Digital Digital Analog Analog Digital Digital
XPD High High Low
VINP High Low X
VINN Low High X
VOUTP High Low High
VOUTN Low High Low
XPD SIM VINP VINN VOUTP VOUTN
SYMBOL OF PERXBIAS
PIN LIST OF PERXBIAS
Pin VDDA VSSA IREFP1 IREFP2 IREFP3 IREFN1 IREFN2 IREFN3 VMID XSIM VREF Description Positive Supply Negative Supply Bias Current Bias Current Bias Current Bias Current Bias Current Bias Current Voltage Reference Test Pin External Reference Voltage Type Supply Supply Analog Analog Analog Analog Analog Analog Analog Digital Analog
THEORY OF OPERATION
The PECL_RX is a differential line receiver which accepts low voltage input signals according to F100K standard. The input signal lines must be 50 transmission lines. At the receiver input each signal has to be terminated to the voltage level VT (where VT = VDDPECL - 2 V) with an external termination resistor of 50 , but also other termination schemes are possible. The cell PECL_RX can be set in power down mode. It requires the PERXBIAS cell for biasing. PERXBIAS can drive up to 3 PECL_RX cells. An external voltage reference must be used.
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Datasheet: PECL_RX - C35
APPLICATION
! ! ! ! ! High Speed Backplane Driver Complementary Clock Drivers Level Translator System Interconnects ATM Applications ! ! ! ! SDH Applications High-Resolution Imaging Applications Laser Printers Digital Copiers
TYPICAL APPLICATION1)
VDDA 1 F VSSA 3) VDDA
external
chip internal
6)
SNAP BACK 100pF 22pF
1) 4)
VDDA VDD VDD 1 F VSS DATA 50 transmission lines DATAN
3)
1) 7) 4) 7) 7)
100pF
22pF
VT 50
complementary CMOS signals (to digital core) 50 VT VSS 3) 4)
from transmitter VDDA + 2V VT VREF 1 F
5)
100pF
22pF VSSA
3) 4)
VREF (external reference) 180pF
3)
2)
SNAP BACK 1nF VSSA
6)
1) 2) 3) 4) 5) 6) 7)
Each power pin must have its own set of blocking capacitors. An external reference must be used. VSSA and VSS must be connected on the PCB level. The two power pads can be bonded to one package pin (double bonding). Two more PECL_RX cells can be driven with IREFxx of the PERXBIAS cell. If an output IREFxx is not used it must be left unconnected. The PECL part of the chip has to be separated from the rest of the chip by use of snap backs (cell PWRCUT_DIG_P_SNAP_SNAP). The cells VDD3R1P and VDD3R2P are not in the standard library, they are part of the IP-block.
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Datasheet: PECL_RX - C35
Contact
austriamicrosystems AG A 8141 Schloss Premstatten, Austria T. +43 (0) 3136 500 5333 F. +43 (0) 3136 500 5755 support@austriamicrosystems.com
Copyright
Copyright (c) 2002 austriamicrosystems. Trademarks registered (R). All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. To the best of its knowledge, austriamicrosystems asserts that the information contained in this publication is accurate and correct.
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